CN108777899B

CN108777899B - Control circuit for generating multipath irregular signals and lighting system

Info

Publication number: CN108777899B
Application number: CN201810668433.2A
Authority: CN
Inventors: 曹进伟; 陈孟邦; 蔡荣怀; 邹云根; 张丹丹; 雷先再; 田再梅
Original assignee: Zongren Technology Pingtan Co ltd
Current assignee: Zongren Technology Pingtan Co ltd
Priority date: 2018-06-26
Filing date: 2018-06-26
Publication date: 2024-01-02
Anticipated expiration: 2038-06-26
Also published as: CN108777899A

Abstract

The invention belongs to the technical field of integrated circuits, and provides a control circuit for generating multipath irregular signals and a lighting system; the control circuit includes: a first oscillator unit, a second oscillator unit, a first frequency dividing unit, a second frequency dividing unit, and a first output unit; the first oscillator unit generates a first oscillation signal; the second oscillator unit generates a second oscillation signal; the first frequency dividing unit divides the frequency of the first oscillating signal for multiple times according to the power-on reset signal to obtain multiple frequency division signals; the second frequency dividing unit divides the frequency of the second oscillating signal for a plurality of times according to the power-on reset signal to obtain a trigger signal; the first output unit carries out a first logic operation on the trigger signal and the multipath frequency division signal according to the power-on reset signal to obtain a driving signal with extremely poor multipath regularity; the invention can effectively solve the problems that the integrated circuit in the prior art can not generate a driving signal with poor regularity, and the realized circuit has single function and can not be universally applied.

Description

Control circuit for generating multipath irregular signals and lighting system

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a control circuit for generating multipath irregular signals and a lighting system.

Background

In the traditional technology, a large-scale integrated circuit is generally adopted to generate a driving signal so as to realize corresponding circuit functions; however, as the requirements of the electronic circuits are increasing, the performance parameters of the driving signals generated by the integrated circuits are becoming more complex; the conventional integrated circuit generally adopts some signal generating chips to generate some signals with strong regularity, and although the signals with strong regularity can drive the electronic elements to realize more complex functions at the same time, in consideration of some special functional requirements in the electronic circuit, if the signals with strong regularity generated by the conventional integrated circuit cannot realize better circuit functions; taking the illumination of an LED (Light Emitting Diode ) lamp as an example, in order to obtain a better light ornamental effect, people need to generate irregular driving signals through an electronic circuit so as to realize the disordered flashing of a plurality of LED lamps, so that a good visual effect is brought to people; however, the integrated circuit in the conventional technology can only generate a driving signal with strong regularity, and cannot drive a plurality of LED lamps to achieve a better messy flash effect.

Therefore, the integrated circuit in the prior art generally adopts a signal generating chip to generate only multiple paths of driving signals with stronger regularity, the circuit structure of the integrated circuit is fixed, the driving signals with extremely poor regularity are difficult to generate, the circuit function realized by the traditional integrated circuit is single, the compatibility is poor, the integrated circuit cannot be universally applied, and the use experience of a user is low.

Disclosure of Invention

The invention provides a control circuit for generating multipath irregular signals and a lighting system, and aims to solve the problems that an integrated circuit cannot generate driving signals with poor regularity in the prior art, so that the circuit function realized by the integrated circuit is single and cannot be universally applied.

A first aspect of the present invention provides a control circuit for generating a plurality of irregular signals, comprising:

a first oscillator unit configured to generate a first oscillation signal;

a second oscillator unit configured to generate a second oscillation signal;

the first frequency dividing unit is connected with the first oscillator unit and is configured to divide the frequency of the first oscillating signal for N times according to a power-on reset signal to obtain L paths of frequency division signals;

the second frequency division unit is connected with the second oscillator unit and is configured to divide the frequency of the second oscillation signal for M times according to the power-on reset signal to obtain a trigger signal; and

The first output unit is connected with the first frequency division unit and the second frequency division unit and is configured to perform a first logic operation on the trigger signal and the L paths of frequency division signals according to the power-on reset signal to obtain L paths of driving signals;

wherein N, L and M are positive integers greater than or equal to 2 and L is less than or equal to N.

In one embodiment thereof, the first oscillator unit includes: the first inverter comprises a first NAND gate, a second NAND gate, a first resistor, a first capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter;

the first end of the first resistor, the first end of the first capacitor and the input end of the first inverter are commonly connected to the input end of the second inverter, the output end of the second inverter is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the first NAND gate, the first input end of the first NAND gate and the output end of the second NAND gate are commonly connected to the input end of the fourth inverter, the output end of the first inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to the second input end of the first NAND gate, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter and the second end of the first capacitor are commonly connected to the input end of the sixth inverter, the output end of the sixth inverter and the second end of the first resistor are commonly connected to the input end of the seventh inverter, and the output end of the seventh inverter is connected to the first divider.

In one embodiment thereof, the second oscillator unit includes: a third NAND gate, a fourth NAND gate, a second resistor, a second capacitor, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, and a fifteenth inverter;

the first end of the second resistor, the first end of the second capacitor and the input end of the eighth inverter are commonly connected to the input end of the ninth inverter, the output end of the ninth inverter is connected to the first input end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the output end of the third NAND gate, the first input end of the third NAND gate and the output end of the fourth NAND gate are commonly connected to the input end of the eleventh inverter, the output end of the eighth inverter is connected to the input end of the tenth inverter, the output end of the tenth inverter is connected to the second input end of the third NAND gate, the output end of the eleventh inverter is connected to the input end of the twelfth inverter, the output end of the twelfth inverter and the second end of the second capacitor are commonly connected to the input end of the thirteenth inverter, the output end of the thirteenth inverter and the second end of the second resistor are commonly connected to the input end of the fourteenth inverter, and the output end of the fifteenth inverter is connected to the input end of the fourteenth inverter.

In one embodiment, the first frequency dividing unit includes: a sixteenth inverter and a first T flip-flop array; the first T trigger array comprises N cascaded T triggers, in the first T trigger array, a reset signal input end of each stage of T trigger is used for being connected with the power-on reset signal, a Q output end of each stage of T trigger is used for outputting the frequency division signal, a Q output end of the ith stage of T trigger is connected with a CKB input end of the (i+1) th stage of T trigger, and a QB output end of the ith stage of T trigger is connected with a CK input end of the (i+1) th stage of T trigger;

the CKB input end of a first-stage T trigger in the first T trigger array is connected with the output end of the sixteenth inverter, and the CK input end of the first-stage T trigger in the first T trigger array and the input end of the sixteenth inverter are connected with the first oscillator unit; wherein i is any positive integer between 1 and N-1.

In one embodiment, the second frequency dividing unit includes: seventeenth inverter, eighteenth inverter and second T flip-flop array; the second T trigger array comprises M cascaded T triggers, in the second T trigger array, the reset signal input end of each stage of T trigger is used for being connected with the power-on reset signal, the Q output end of the j-th stage of T trigger is connected with the CKB input end of the j+1th stage of T trigger, and the QB output end of the j-th stage of T trigger is connected with the CK input end of the j+1th stage of T trigger;

The input end of the seventeenth inverter and the CK input end of a first-stage T trigger in the second T trigger array are commonly connected with the second oscillator unit, the QB output end of an Mth-stage T trigger in the second T trigger array is connected with the input end of the eighteenth inverter, and the output end of the eighteenth inverter is connected with the first output unit; wherein j is any positive integer between 1 and M-1.

In one embodiment thereof, the first output unit includes: a nineteenth inverter and a D flip-flop array; the D trigger array comprises L cascaded D triggers, wherein in the D trigger array, the reset signal input end of each stage of D trigger is used for being connected with the power-on reset signal, the D input end of each stage of D trigger is connected with one path of frequency division signal, the Q output end of each stage of D trigger is used for outputting one path of driving signal, the CKB input end of each stage of D trigger is connected with the output end of the nineteenth inverter, and the CK input end of each stage of D trigger and the input end of the nineteenth inverter are connected with the second frequency division unit.

In one embodiment thereof, the method further comprises: and the power-on reset unit is connected with the first frequency division unit, the second frequency division unit and the first output unit and is configured to be connected with a direct-current power supply and generate the power-on reset signal.

In one embodiment thereof, the power-on reset unit includes: the first PMOS tube, the third capacitor, the twenty-first inverter and the twenty-second inverter;

the source electrode of the first PMOS tube is connected with the direct current power supply, the grid electrode of the first PMOS tube is grounded, the drain electrode of the first PMOS tube and the first end of the third capacitor are commonly connected with the input end of the twenty-first inverter, the second end of the third capacitor is grounded, the output end of the twenty-first inverter is connected with the input end of the twenty-first inverter, the output end of the twenty-first inverter is connected with the input end of the twenty-second inverter, and the output end of the twenty-second inverter is used for outputting the power-on reset signal.

In one embodiment thereof, the method further comprises: the second output unit is connected with the first output unit and is configured to perform a second logic operation on the L paths of driving signals to obtain a multipath driving optimized signal;

the second output unit comprises a plurality of signal optimization modules, and each signal optimization module comprises a logic gate and an inverter; the logic gate comprises at least two input ends, one input end of the logic gate is connected with one path of driving signal, the output end of the logic gate is connected with the input end of the inverter, and the output end of the inverter is used for outputting one path of driving optimization signal.

The second aspect of the invention provides a lighting system, which comprises the control circuit and a plurality of LED lamps which are connected with the control circuit and are in disordered flash under the drive of the L-path driving signals.

In the control circuit for generating the multipath irregular signals, the first oscillator unit generates the first oscillating signal, the second oscillator unit generates the second oscillating signal, the first oscillating signal is divided by the first frequency dividing unit for multiple times to obtain multipath frequency dividing signals, the second oscillating signal is divided by the second frequency dividing unit for multiple times to obtain trigger signals, and the first output unit performs first logic operation on the trigger signals and the multipath frequency dividing signals according to the power-on reset signals to obtain multipath irregular driving signals, and as parameters such as frequency, phase and the like among all paths of driving signals have irregularity and randomness, multiple circuit functions can be realized through the driving signals, and the control circuit can be widely applied to various industrial fields; meanwhile, the control circuit can generate driving signals with any path number, so that the control circuit has strong compatibility, high expandability and wide application range; the integrated circuit effectively solves the problems that the integrated circuit in the prior art cannot generate driving signals with poor regularity, the realized circuit has single function and cannot be universally applied.

Drawings

Fig. 1 is a block diagram of a control circuit for generating multiple irregular signals according to an embodiment of the present invention;

fig. 2 is a circuit configuration diagram of a first oscillator unit according to an embodiment of the present invention;

fig. 3 is a circuit configuration diagram of a second oscillator unit according to an embodiment of the present invention;

fig. 4 is a circuit configuration diagram of a first frequency dividing unit according to an embodiment of the present invention;

fig. 5 is a circuit configuration diagram of a second frequency dividing unit according to an embodiment of the present invention;

fig. 6 is a circuit configuration diagram of a first output unit according to an embodiment of the present invention;

FIG. 7 is a block diagram of another control circuit for generating multiple irregular signals according to an embodiment of the present invention;

FIG. 8 is a circuit configuration diagram of a power-on reset unit according to an embodiment of the present invention;

fig. 9 is a circuit configuration diagram of a second output unit according to an embodiment of the present invention;

fig. 10 is a block diagram of a lighting system according to an embodiment of the present invention.

Detailed Description

Fig. 1 shows a block configuration of a control circuit 10 for generating multiple irregular signals according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, which is described in detail as follows:

As shown in fig. 1, the control circuit 10 includes: a first oscillator unit 101, a second oscillator unit 102, a first frequency dividing unit 103, a second frequency dividing unit 104, and a first output unit 105, wherein the first oscillator unit 101 generates a first oscillation signal H0, and the second oscillator unit 102 generates a second oscillation signal L0; the first oscillation signal H0 generated by the first oscillator unit 101 has a specific frequency and phase, and the second oscillation signal L0 generated by the second oscillator unit 102 also has a specific frequency and phase, and optionally, parameters of the first oscillation signal H0 and parameters of the second oscillation signal L0 may be the same or different, which is not limited herein, wherein the parameters of the oscillation signals include, but are not limited to: the period, frequency, phase, amplitude of the signal; in this embodiment, the parameters of the first oscillation signal H0 and the parameters of the second oscillation signal L0 are different, wherein the first oscillation signal H0 is a high-frequency signal, and the period of the high-frequency signal is between 10 microseconds and 900 microseconds; the second oscillation signal L0 is a low-frequency signal, and the period of the low-frequency signal is between 10 ms and 900 ms; preferably, the period of the first oscillation signal H0 and the period of the second oscillation signal L0 need to satisfy the following conditions: the period of the first oscillation signal H0 and the period of the second oscillation signal L0 are both prime numbers, and the period of the second oscillation signal L0 divided by the period of the first oscillation signal H0 does not belong to an integer within 64; when the period of the first oscillation signal H0 and the period of the second oscillation signal L0 satisfy the condition, the control circuit 10 will be able to generate the multi-drive signal D with worse regularity; since the first oscillation signal H0 and the second oscillation signal L0 both have a specific oscillation frequency, the control circuit 10 can output multiple driving signals having different frequencies after performing multiple frequency division and logic operation on the first oscillation signal H0 and the second oscillation signal L0, so as to implement more complex circuit functions.

The first frequency dividing unit 103 is connected with the first oscillator unit 101, the first oscillator unit 101 transmits a first oscillating signal H0 to the first frequency dividing unit 103, and the first frequency dividing unit 103 carries out N times of frequency division on the first oscillating signal H0 according to the power-on reset signal POR to obtain an L-path frequency division signal Q; the power-on reset signal POR is generated by a power-on reset unit, and each power component in the first frequency dividing unit 103 can be driven to perform reset operation through the power-on reset signal POR; specifically, each time the first frequency dividing unit 103 divides the first oscillation signal H0 once, the frequency of the first oscillation signal H0 changes, and after the first frequency dividing unit 103 divides the first oscillation signal H0N times, each of the obtained frequency-divided signals Q has a specific frequency, and then the L-way frequency-divided signal Q has multiple frequencies.

The second frequency division unit 104 is connected with the second oscillator unit 102, and the second frequency division unit 104 divides the second oscillation signal L0 for M times according to the power-on reset signal POR to obtain a trigger signal L1; wherein the power-on reset signal POR can play a reset role in the second frequency division unit 104; the second frequency dividing unit 104 divides the frequency of the second oscillating signal L0 by M times, so that the frequency of the second oscillating signal L0 can be changed, and the generated trigger signal L1 has a specific frequency and phase; the first output unit 105 is connected with the first frequency division unit 103 and the second frequency division unit 104, and the first output unit 105 performs a first logic operation on the trigger signal L1 and the L-path frequency division signal Q according to the power-on reset signal POR to obtain an L-path driving signal D; since the frequency of the divided signal Q can be randomly changed by performing a logic operation on the divided signal Q in the first output unit 105, after the first output unit 105 performs a first logic operation on the trigger signal L1 and the L-path divided signal Q, the frequency and the phase of each path of driving signal D are randomly generated, which has an arbitrary property; the frequency and phase of the L-path driving signal D generated by the first output unit 105 have a very irregular characteristic; further, when the output end of the first output unit 105 is connected with the external electronic device and the first output unit 105 transmits the L-path driving signal D to the external electronic device, the frequency and the phase of the L-path driving signal D have the characteristics of randomness and randomness, so that the external electronic device can be driven by the multi-path driving signal D to realize various complex circuit functions, thereby meeting the actual demands of people in various industrial fields.

The N, the L, and the M are positive integers greater than or equal to 2, and L is less than or equal to N.

According to the embodiment of the invention, the first frequency dividing unit 103 divides the first oscillating signal H0 for multiple times according to the power-on reset signal POR to obtain a multi-channel frequency dividing signal Q, the second frequency dividing unit 104 divides the second oscillating signal L0 for multiple times according to the power-on reset signal POR to obtain a trigger signal L1, and the frequency of the first frequency dividing unit 103 dividing the first oscillating signal H0 can be adjusted according to actual needs, so that frequency dividing signals Q with different frequencies can be obtained, and the frequency of the second frequency dividing unit 104 dividing the second oscillating signal L0 can be adjusted according to actual needs, so that the control circuit 10 has extremely high expandability; meanwhile, the first output unit 105 is used for carrying out first logic operation on the multipath frequency division signal Q to obtain an irregular multipath driving signal D, and the phase and the frequency of the multipath driving signal D have randomness and discretionary property, so that the multipath driving signal D can drive the electronic circuit to realize various circuit functions so as to meet various requirements of technicians; the number of the driving signals D generated by the control circuit 10 can be adjusted according to the specific functions of the electronic circuit, so that the compatibility is extremely strong, and the method can be widely applied to various industrial technical fields; the problem that the integrated circuit cannot generate driving signals with poor regularity in the traditional technology, so that the circuit function realized by the integrated circuit is single and cannot be universally applied to various industrial fields is effectively solved.

As an alternative implementation manner, fig. 2 shows a circuit structure of a first oscillator unit 101 provided in an embodiment of the present invention, and as shown in fig. 2, the first oscillator unit 101 includes: a first NAND gate NAND1, a second NAND gate NAND2, a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a seventh inverter INV7; the first end of the first resistor R1, the first end of the first capacitor C1 and the input end of the first inverter INV1 are commonly connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the first input end of the second NAND gate NAND2, the second input end of the second NAND gate NAND2 is connected to the output end of the first NAND gate NAND1, the first input end of the first NAND gate NAND1 and the output end of the second NAND gate NAND2 are commonly connected to the input end of the fourth inverter INV4, the output end of the first inverter INV1 is connected to the input end of the third inverter INV3, the output end of the third inverter INV3 is connected to the second input end of the first NAND gate NAND1, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 and the second end of the first capacitor C2 are commonly connected to the input end of the sixth inverter INV6, the output end of the sixth inverter 6 and the second end of the first resistor R1 are commonly connected to the input end of the seventh inverter INV7, and the output end of the seventh inverter 103 is connected to the first inverter 7; the output end of the seventh inverter INV7 is the output end of the first frequency dividing unit 103, and is used for transmitting the first oscillation signal H0 to the first frequency dividing unit 103.

As an alternative implementation manner, fig. 3 shows a circuit structure of the second oscillator unit 102 provided in the embodiment of the present invention, and as shown in fig. 3, the second oscillator unit 102 includes: a third NAND gate NAND3, a fourth NAND gate NAND4, a second resistor R2, a second capacitor C2, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, and a fifteenth inverter INV15; the first end of the second resistor R2, the first end of the second capacitor C2 and the input end of the eighth inverter INV8 are commonly connected to the input end of the ninth inverter INV9, the output end of the ninth inverter INV9 is connected to the first input end of the fourth NAND gate NAND4, the second input end of the fourth NAND gate NAND4 is connected to the output end of the third NAND gate NAND3, the first input end of the third NAND gate NAND3 and the output end of the fourth NAND gate NAND4 are commonly connected to the input end of the eleventh inverter INV11, the output end of the eighth inverter INV8 is connected to the input end of the tenth inverter INV10, the output end of the tenth inverter INV10 is connected to the second input end of the third NAND gate INV 3, the output end of the eleventh inverter INV11 is connected to the input end of the thirteenth inverter INV12, the output end of the thirteenth inverter INV12 and the second end of the second capacitor C2 are commonly connected to the input end of the thirteenth inverter INV13, the output end of the thirteenth inverter 13 and the second end of the second resistor R2 are commonly connected to the input end of the fourteenth inverter INV14, the output end of the fourteenth inverter is connected to the fifteenth inverter unit 15; the output end of the fifteenth inverter INV15 is the output end of the second oscillator unit 102, and is used for transmitting the second oscillation signal L0 to the second frequency dividing unit 104.

As an alternative implementation manner, fig. 4 shows a circuit structure of the first frequency dividing unit 103 provided in the embodiment of the present invention, and as shown in fig. 4, the first frequency dividing unit 103 includes: sixteenth inverter INV16 and first T flip-flop array 1031; the first T flip-flop array 1031 includes N cascaded T flip-flops, in the first T flip-flop array 1031, a reset signal input terminal R of each stage of T flip-flop is connected to a power-on reset signal POR, and a reset operation can be performed on each T flip-flop in the first frequency division unit 1031 through the power-on reset signal POR; the Q output end of each stage T trigger is used for outputting a frequency division signal Q, the Q output end of the ith stage T trigger ZTRi is connected with the CKB input end of the (i+1) th stage T trigger ZTRi+1, and the QB output end of the ith stage T trigger ZTRi is connected with the CK input end of the (i+1) th stage T trigger ZTRi+1; the CKB input of the first stage T flip-flop ZTR1 in the first T flip-flop array 1031 is connected to the output end of the sixteenth inverter INV16, and the CK input of the first stage T flip-flop ZTR1 in the first T flip-flop array 1031 and the input end of the sixteenth inverter INV16 are commonly connected to the first oscillator unit 101 for accessing the first oscillation signal H0.

The i is any positive integer between 1 and N-1.

In the circuit structure of the first frequency dividing unit 103 shown in fig. 4, since the first T flip-flop array 1031 includes a plurality of T flip-flops, and the T flip-flops are electronic components commonly used in the art, when the first T flip-flop array 1031 is connected to the first oscillating signal H0, the first T flip-flop array 1031 performs multiple frequency division on the first oscillating signal H0 by using the signal flipping and holding functions of the plurality of T flip-flops, so as to obtain L-path frequency division signals Q1, Q2 … QL-1, QL; specifically, in combination with the circuit structure of the first frequency dividing unit 103 in fig. 4, when the first oscillation signal H0 sequentially passes through each stage of T flip-flop, it is equivalent to that each stage of T flip-flop performs a frequency dividing operation on the first oscillation signal H0; further, in the first T flip-flop array 1031, the frequency-divided signal Q outputted from the Q output terminal of each stage of T flip-flop has different frequencies and phases; thus, L T flip-flops are optionally selected from the first T flip-flop array 1031, and the signals output by the Q outputs of the L T flip-flops are combined into an L divided signal Q, and then the L divided signal Q has a plurality of frequencies and phases; as a preferred embodiment, in order to enable the frequency and phase of the L-th divided signal Q to have randomness and disorder, in the first T flip-flop array 1031, signals output by Q outputs of the N-l+1th to N-th T flip-flops are preferentially selected to form the L-th divided signals Q1, Q2 … QL-1, QL, and at this time, the frequency and phase of the divided signal Q are less regular due to multiple frequency divisions, so that the control circuit 10 can drive the electronic circuit to implement multiple complex circuit functions.

It should be noted that, in the circuit structure of the first frequency dividing unit 103, since the first T flip-flop array 1031 divides the first oscillation signal H0 multiple times to obtain the L-path divided signals Q1, Q2 … QL-1, QL, the period of each path of divided signal is an integer multiple of the period of the first oscillation signal H0, and the period of each path of divided signal is different.

As an alternative implementation manner, fig. 5 shows a circuit structure of the second frequency dividing unit 104 provided by the embodiment of the present invention, and as shown in fig. 5, the second frequency dividing unit 104 includes: seventeenth inverter INV17, eighteenth inverter INV18, and second T flip-flop array 1041; the second T flip-flop array 1041 includes M cascaded T flip-flops ZTR1, ZTR2 … ZTRM-1, ZTRM, in the second T flip-flop array 1041, a reset signal input terminal R of each stage of T flip-flop is connected to a power-on reset signal POR, and a reset operation is performed on the T flip-flops in the second T flip-flop array 1041 by the power-on reset signal POR; the Q output end of the jth stage T trigger ZTRj is connected with the CKB input end of the jth+1th stage T trigger ZTRj+1, and the QB output end of the jth stage T trigger ZTRj is connected with the CK input end of the jth+1th stage T trigger ZTRj+1; an input end of the seventeenth inverter INV17 and a CK input end of the first stage T flip-flop ZTR1 in the second T flip-flop array 1041 are commonly connected to the second oscillator unit 102, for accessing the second oscillation signal L0; the QB output end of the mth stage T flip-flop ZTRM in the second T flip-flop array 1041 is connected to the input end of the eighteenth inverter INV18, the output end of the eighteenth inverter INV18 is connected to the first output unit 105, and the output end of the eighteenth inverter INV18 is the output end of the second frequency dividing unit 104, for transmitting the trigger signal L1 to the first output unit 105.

The j is any positive integer between 1 and M-1.

According to the above circuit structure of the second frequency dividing unit 104, the second T flip-flop array 1041 includes M cascaded T flip-flops, and since the T flip-flops have functions of holding and turning signals, when the second T flip-flop array 1041 is connected to the second oscillating signal L0, the plurality of T flip-flops divide the second oscillating signal L0 for multiple times, so that the frequency and the phase of the second oscillating signal L0 can be changed, and the second T flip-flop array 1041 can generate the triggering signals L1 with different frequencies and phases; specifically, in practical applications, a person skilled in the art may select different numbers of T flip-flops in the second frequency dividing unit 104, for example, M may be 10, 11 or 12, and if the number of T flip-flops included in the second T flip-flop array 1041 is greater, the frequency of the second T flip-flop array 1041 for dividing the second oscillating signal L0 is also greater, so that the number of T flip-flops in the second T flip-flop array 1041 can be changed, and further trigger signals L1 with different frequencies can be obtained, thereby having extremely high scalability.

As an alternative implementation manner, fig. 6 shows a circuit structure of the first output unit 105 provided by the embodiment of the present invention, and as shown in fig. 6, the first output unit 105 includes: nineteenth inverter INV19 and D flip-flop array 1051; the D flip-flop array 1051 includes L cascaded D flip-flops ZDR1, ZDR2 … ZDRL-1, ZDRL, in the D flip-flop array 1051, a reset signal input terminal R of each stage of D flip-flop is connected to a power-on reset signal POR, a reset operation is performed on each stage of D flip-flop in the D flip-flop array 1051 by the power-on reset signal POR, a D input terminal of each stage of D flip-flop is connected to a path of frequency division signal, and in combination with the circuit structure of the first frequency division unit 103, the D input terminal of each stage of D flip-flop is respectively connected to the Q output terminal of the T flip-flop in the first T flip-flop array 1031; the Q output end of each stage of D trigger is used for outputting a path of driving signal, and the driving signal can drive the electronic circuit to realize corresponding functions; the CKB input end of each stage D flip-flop is commonly connected to the output end of the nineteenth inverter INV19, and the CK input end of each stage D flip-flop and the input end of the nineteenth inverter INV19 are commonly connected to the second frequency division unit 104, for accessing the trigger signal L1.

Specifically, the D trigger is used as an electronic component commonly used in the traditional technology and has the processing function of digital signals; in the D flip-flop array 1051, each stage of D flip-flop performs a logic operation on the trigger signal L1 and one frequency division signal to output one driving signal, and as described above, since the phase and the frequency of the L frequency division signal Q generated by the first frequency division unit 103 have randomness and randomness, after the D flip-flop array 1051 performs the first logic operation on the trigger signal L1 and the L frequency division signal Q, the frequency and the phase of the obtained L driving signal D also have irregularity, and the logic operation performed on the trigger signal L1 and the frequency division signal Q by the T flip-flop will enhance the randomness and the randomness of the multi-path driving signal D; since the frequency and phase of the multiplex driving signal D are very irregular, when the first output unit 105 transmits the multiplex driving signal D to an external electronic circuit, the electronic circuit can implement more complex circuit functions through the multiplex driving signal D.

In order to better explain the working principle of the control circuit 10 in the embodiment of the present invention, referring to fig. 1-6, the working steps of the control circuit 10 are described through a specific application scenario, where the application scenario is to apply the control circuit 10 to a plurality of LED lamps to achieve the technical effect of messy flash, specifically as follows:

In the traditional technology, light sources with different brightness and frequency are emitted through a plurality of LED lamps, namely, the disordered flashing effect is achieved, and good visual aesthetic feeling can be brought to people through disordered flashing through the LED lamps, so that disordered flashing through the LED lamps is widely applied to various fields of curtain wall design, billboard propaganda and the like of high-rise buildings; in this application scenario, if a technician needs 4 LED lamps to achieve the effect of messy flashing, in this application scenario, parameters of the control circuit 10 are set as follows:

N＝7；L＝4；M＝14；

the first oscillation signal H0 generated by the first oscillator unit 101 at this time is a high-frequency signal, and the period of the first oscillation signal H0 is 200 microseconds; the second oscillation signal L0 generated by the second oscillator unit 102 is a low frequency signal, and the period of the second oscillation signal L0 is 200 milliseconds; the first frequency dividing unit 103 divides the first oscillation signal H0 7 times to obtain 4 paths of irregular frequency division signals Q1, Q2, Q3 and Q4, and the second frequency dividing unit 104 divides the second oscillation signal L0 14 times to obtain a trigger signal L1, since the phase of the trigger signal L1 obtained by the second frequency dividing unit 104 is random, and the phase of the trigger signal L1 has a rising edge and a falling edge; according to the control logic between the input signal and the output signal of the D flip-flop in the conventional technology, the signal phase of the Q output of the D flip-flop keeps consistent with the signal phase of the D input of the D flip-flop only when the signal connected to the CK input of the D flip-flop is a rising edge, and the signal phase of the Q output of the D flip-flop keeps consistent with the signal phase of the D input of the D flip-flop whenever the signal connected to the CK input of the D flip-flop is a rising edge, so that the signal period output by the Q output of the D flip-flop is an integer multiple of the signal period input by the CK input of the D flip-flop.

Specifically, in combination with the circuit structure of the first output unit 105 in the embodiment of the present invention, since in the D flip-flop array 1051, the D input terminal of each stage of D flip-flop is connected to one path of frequency division signal, the CK input terminal of each stage of D flip-flop is connected to the trigger signal L1, and the CKB input terminal of each stage of D flip-flop is connected to the inverse signal of the trigger signal L1, the phase timing of the driving signal output by the Q output terminal of each stage of D flip-flop is determined by the phase timing of the trigger signal L1 and the phase timing of the frequency division signal; if the frequencies of the 4-way frequency-divided signals Q1, Q2, Q3 and Q4 and the frequency of the trigger signal L1 have the characteristic of extremely poor regularity, the frequencies and phases of the 4-way driving signals D1, D2, D3 and D4 outputted by the first output unit 105 also have the characteristic of extremely poor regularity; specifically, if the trigger signal L1 is a rising edge, the 4-way frequency-divided signals Q1, Q2, Q3 and Q4 generated by the first frequency-dividing unit 103 are all at a high level, in the D trigger array 1051, the signal connected to the D input end of each stage of D trigger is at a high level, the signal connected to the CK input end of each stage of D trigger is at a rising edge, the signal connected to the CKB input end of each stage of D trigger is at a falling edge, according to the control logic between the input signal and the output signal of the D trigger, the driving signal output by the Q output end of each stage of D trigger is at a high level at this time, and the 4-way driving signals D1, D2, D3 and D4 output by the first output unit 105 always maintain at a high level until the next rising edge occurs in the trigger signal L1, the phase of the driving signal is changed according to the phase of the frequency-divided signal; therefore, each time the rising edge occurs in the trigger signal L1, the phase of the driving signal output by the Q output terminal of the D flip-flop is consistent with the phase of the frequency-divided signal, and the phase of the driving signal is maintained until the next rising edge occurs in the trigger signal L1, so that the first output unit 105 performs logic operation on the trigger signal L1 and the 4-way frequency-divided signals Q1, Q2, Q3 and Q4 to obtain 4-way driving signals D1, D2, D3 and D4.

Therefore, according to the working principle of the first output unit 105, the phase period of the driving signal D generated by the first output unit 105 is determined according to the phase period of the trigger signal L1 and the phase period of the frequency-dividing signal Q, and if the phases of the trigger signal L1 and the frequency-dividing signal Q are both irregularly distributed, or the phases of the first oscillation signal H0 and the second oscillation signal L0 are both irregularly distributed, the phase of the driving signal D is irregular; specifically, when the phase of the trigger signal L1 rises, the level state of the frequency-divided signal Q is uncertain, so that the level state of the driving signal D output by the Q output end of the D flip-flop is also uncertain, that is, each path of driving signal D can be in a high level state or a low level state, so that the phase and the frequency of the driving signal D are very irregular, and have randomness and discretion; further, if the period of the first oscillation signal H0 and the period of the second oscillation signal L0 are prime numbers, the phase of the trigger signal L1 and the phase of the frequency-divided signal Q have higher randomness, and the matching degree of the two signals is lower, so that the control circuit 10 can generate a multi-path driving signal D with poorer regularity, and further drive a plurality of LED lamps to achieve better disordered flash effect.

As a preferred embodiment, in the circuit structure, a plurality of logic gates, such as an exclusive-or gate, an and gate, or an not gate, are added between the first frequency dividing unit 103 and the first output unit 105, the L-path frequency dividing signal Q is logically operated by the plurality of logic gates, and then the signal after being logically operated is transmitted to the D input end of the D flip-flop in the first output unit 105, so that the multi-path driving signal D output by the D flip-flop array 1051 has higher disorder and poorer regularity.

In combination with the application scenario of the present invention, the first frequency dividing unit 103 divides the first oscillation signal H0 for multiple times to obtain the multiple frequency dividing signal Q, and the second frequency dividing unit 104 divides the second oscillation signal L0 for multiple times to obtain the trigger signal L1, where the phase and frequency of the frequency dividing signal Q and the phase and period of the trigger signal L1 are uncertain and random, so that when the first output unit 105 performs the first logic operation on the trigger signal L1 and the multiple frequency dividing signal Q to obtain the multiple driving signal D, the phase of the driving signal D is also uncertain and has randomness and arbitrary, and further the control circuit 10 generates the multiple driving signal D with extremely poor regularity, and the multiple LED lamps can be driven to perform irregular flash through the multiple driving signal D, thereby bringing good user experience to the viewer; the number of driving signals generated by the control circuit 10 can be adjusted according to the number of the LED lamps according to the circuit composition structure of the control circuit 10, for example, the control circuit 10 can generate 4 paths, 5 paths or 6 paths of driving signals so as to realize the disordered flashing of the LED lamps with different numbers, so that the control circuit 10 has extremely strong compatibility, high expandability and wide application range; therefore, the problems that the regularity of a plurality of LED lamp driving signals generated by an integrated circuit in the prior art is too strong, the messy flashing effect realized by a plurality of LED lamps is poor, and the visual experience of a user is poor are solved.

As a preferred implementation manner, fig. 7 shows another circuit structure of the control circuit 10 for generating multiple irregular signals according to the embodiment of the present invention, and compared to the module structure of the control circuit 10 shown in fig. 1, the control circuit 10 shown in fig. 7 further includes a power-on reset unit 701 and a second output unit 702, specifically:

the power-on reset unit 701 is connected with the first frequency division unit 103, the second frequency division unit 102 and the first output unit 105, the power-on reset unit 701 is connected with the direct current power supply VDD and generates a power-on reset signal POR, the power-on reset unit 701 transmits the power-on reset signal POR to other circuit units in the control circuit 10, and the power-on reset signal POR can realize the reset function in the control circuit 10; the second output unit 702 is connected with the first output unit 105, the first output unit 105 transmits the L-path driving signal D to the second output unit 702, and the second output unit 702 performs a second logic operation on the L-path driving signal D to obtain a multi-path driving optimized signal DL; as described above, since the L driving signals generated by the first output unit 105 have extremely poor regularity, after the second output unit 702 performs the second logic operation on the L driving signals, the phase and frequency of the obtained multi-path driving optimized signal DL have higher randomness and randomness, which is equivalent to the control circuit 10 performing the logic operation on the trigger signal L1 and the L frequency-divided signal Q twice, and at this time, the multi-path driving optimized signal DL output by the control circuit 10 has higher irregularity; therefore, in the module structure of the control circuit 10 shown in fig. 7, when the first output unit 105 is connected to the external electronic device through the second output unit 702, and when the second output unit 702 transmits the multi-path driving optimization signal DL to the external electronic device, the external electronic device can achieve a better shuffle effect according to the multi-path driving optimization signal DL, thereby improving the practicability of the control circuit 10.

As an alternative implementation manner, fig. 8 shows a circuit structure of a power-on reset unit 701 provided by an embodiment of the present invention, and as shown in fig. 8, the power-on reset unit 701 includes: the first PMOS transistor PMOS1, the third capacitor C3, the twenty-first inverter INV20, the twenty-first inverter INV21 and the twenty-second inverter INV22; the source of the first PMOS transistor PMOS1 is connected to the dc power supply VDD, the gate of the first PMOS transistor PMOS1 is grounded GND, the drain of the first PMOS transistor PMOS1 and the first end of the third capacitor C3 are commonly connected to the input end of the twentieth inverter C20, the second end of the third capacitor C3 is grounded GND, the output end of the twentieth inverter INV20 is connected to the input end of the twenty-first inverter INV21, the output end of the twenty-first inverter INV21 is connected to the input end of the twenty-second inverter INV22, and the output end of the twenty-second inverter INV22 is the output end of the power-on reset unit 701, for outputting the power-on reset signal POR.

According to the circuit structure of the power-on reset unit 701, when the power-on reset unit 701 is just powered on, the first PMOS transistor PMOS1 is turned on, the dc power supply VDD charges the third capacitor C3 through the first PMOS transistor PMOS1, and the third capacitor C3 charges to have a delay effect in the charging process; during the charging process of the third capacitor C3, the power-on reset signal POR output by the power-on reset unit 701 maintains a high level state of 1 microsecond to 10 microseconds; after the third capacitor C3 is charged, the power-on reset signal POR becomes a low level state; the power-on reset unit 701 further transmits a power-on reset signal POR to other units (including the first frequency dividing unit 103, the second frequency dividing unit 102 and the first output unit 105) in the control circuit 10, so as to implement a reset operation of the other units in the control circuit 10.

It can be understood that in the embodiment of the present invention, the power-on reset signal POR can play a role in resetting in the control circuit 10, the T flip-flop and the D flip-flop in the control circuit 10 perform a resetting operation according to the power-on reset signal, and in the practical application field, the control circuit 10 can also use other functional signals to achieve the resetting effect, and only the other functional signals used are required to achieve the same resetting function as the power-on reset signal POR in the present embodiment, so that the control circuit 10 can also achieve a corresponding signal processing function.

As an alternative embodiment, the second output unit 702 includes a plurality of signal optimization modules, each of which includes a logic gate and an inverter; the logic gate comprises at least two input ends, one input end of the logic gate is connected with one path of driving signal, the output end of the logic gate is connected with the input end of the inverter, and the output end of the inverter is used for outputting one path of driving optimization signal; therefore, in the second output unit 702, after the multiple logic gates perform logic operation on the multiple driving signals D, randomness and randomness of frequency and phase of the driving signals D are further enhanced, and the second output unit 702 can output the multiple driving optimized signals with poorer regularity, so as to drive the electronic circuit to realize better circuit functions.

Optionally, in the optimization module of the second output unit 702, the logic gate is: exclusive or gate, nand gate, nor gate, or and gate.

For better illustrating the working principle of the second output unit 702, fig. 9 shows a circuit structure of the second output unit 702 according to an embodiment of the present invention, and the circuit structure of the first output unit 105 shown in fig. 6 is combined; as shown in fig. 9, the second output unit 702 includes 6 signal optimization modules 7021, AND logic gates in each signal optimization module 7021 may be an AND gate AND, an OR gate OR, an exclusive OR gate XOR, etc., AND one input end of each logic gate is randomly connected to one driving signal D, so that the driving optimization signal DL generated by the logic operation of the signal optimization module 7021 has great randomness AND contingency, AND further, the phase AND the frequency of the multiple driving optimization signal DL output by the second logic operation of the second output unit 702 are very irregular, AND accordingly, the electronic circuit realizes a more complex circuit effect according to the multiple driving optimization signal DL.

According to the embodiment of the invention, the control circuit 10 comprises the first output unit 105 and the second output unit 702, on one hand, the first output unit 105 carries out the first logic operation on the trigger signal L1 and the multipath frequency division signal Q to obtain the multipath driving signal D, and the phase and the frequency of multipath driving have randomness and randomness; on the other hand, the second output unit 702 performs the second logic operation on the multi-path driving signal D to obtain a multi-path driving optimized signal DL with worse regularity, which is equivalent to that the control circuit 10 sequentially performs the logic operation on the trigger signal L1 and the multi-path frequency-division signal Q twice, so as to avoid the problem that the multi-path driving signal output by the first output unit 105 may still have stronger regularity; the randomness and the irregularity of the multipath driving optimized signal DL can be greatly enhanced by carrying out the second logic operation on the multipath driving signal D, so that the multipath irregular driving optimized signal DL can be comprehensively ensured to drive the electronic circuit to realize better circuit effect; in addition, as the signal optimization module in the second output unit 702 can be adjusted according to actual needs, the second output unit 702 can output drive optimization signals DL with any path number, has higher compatibility, and can be widely applied to different industrial fields; therefore, the problems that the regularity of the driving signals generated by the integrated circuit in the traditional technology is strong, the realized circuit function is single, and the universal applicability is not realized are effectively solved.

As an alternative implementation, fig. 10 shows a module structure of a lighting system 100 provided by an embodiment of the present invention, where the lighting system 100 includes a control circuit 10 and a plurality of LED lamps 1001 as described above; the plurality of LED lamps 1001 are respectively connected with the control circuit 10, the control circuit 10 transmits a multi-path driving signal D to the plurality of LED lamps, and then the plurality of LED lamps are subjected to disordered flashing under the driving of the multi-path driving signal D; according to the above discussion, since the driving signal D generated by the control circuit 10 has a very irregular characteristic, the plurality of LED lamps can achieve a very good disordered flash effect according to the multiplexed driving signal D, thereby enhancing user experience; therefore, the technician can apply the illumination system 100 to the fields of commercial billboards, curtain walls of high-rise buildings, city landscape lamps and the like, and has extremely high practical application value.

It should be noted that, the control circuit 10 is only applied to the technical field of implementing the random flash of the LED lamp, and this is only an embodiment and does not constitute a technical limitation on the control circuit 10 for generating multiple irregular signals in the present invention; it will be appreciated that, in practical applications, the control circuit 10 may be applied by a person skilled in the relevant art in other fields of robot movement design, unmanned aerial vehicle flight path control, etc., so long as the essential inventive concept and circuit structure are consistent with the control circuit 10 in the present invention, which still falls within the scope of protection of the present invention. Meanwhile, herein, numbers such as plural and multiple are each referred to as being greater than 1; relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities. And the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or structure that comprises a list of elements is inherent to the element. Further, herein, "greater than," "less than," "exceeding," and the like are understood to not include the present number; "above", "below", "within" and the like are understood to include this number.

Claims

1. A control circuit for generating a plurality of irregular signals, comprising:

a first oscillator unit configured to generate a first oscillation signal;

a second oscillator unit configured to generate a second oscillation signal;

wherein the N, L, and M are positive integers greater than or equal to 2, and L is less than or equal to N;

the first frequency dividing unit includes: a sixteenth inverter and a first T flip-flop array; the first T trigger array comprises N cascaded T triggers, in the first T trigger array, a reset signal input end of each stage of T trigger is used for being connected with the power-on reset signal, a Q output end of each stage of T trigger is used for outputting the frequency division signal, a Q output end of the ith stage of T trigger is connected with a CKB input end of the (i+1) th stage of T trigger, and a QB output end of the ith stage of T trigger is connected with a CK input end of the (i+1) th stage of T trigger;

The CKB input end of a first-stage T trigger in the first T trigger array is connected with the output end of the sixteenth inverter, and the CK input end of the first-stage T trigger in the first T trigger array and the input end of the sixteenth inverter are connected with the first oscillator unit; wherein i is any positive integer between 1 and N-1;

the second frequency division unit includes: seventeenth inverter, eighteenth inverter and second T flip-flop array; the second T trigger array comprises M cascaded T triggers, in the second T trigger array, the reset signal input end of each stage of T trigger is used for being connected with the power-on reset signal, the Q output end of the j-th stage of T trigger is connected with the CKB input end of the j+1th stage of T trigger, and the QB output end of the j-th stage of T trigger is connected with the CK input end of the j+1th stage of T trigger;

2. The circuit of claim 1, wherein the first oscillator unit comprises: the first inverter comprises a first NAND gate, a second NAND gate, a first resistor, a first capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter;

3. The control circuit of claim 1, wherein the second oscillator unit comprises: a third NAND gate, a fourth NAND gate, a second resistor, a second capacitor, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, and a fifteenth inverter;

4. The control circuit of claim 1, wherein the first output unit comprises: a nineteenth inverter and a D flip-flop array; the D trigger array comprises L cascaded D triggers, wherein in the D trigger array, the reset signal input end of each stage of D trigger is used for being connected with the power-on reset signal, the D input end of each stage of D trigger is connected with one path of frequency division signal, the Q output end of each stage of D trigger is used for outputting one path of driving signal, the CKB input end of each stage of D trigger is connected with the output end of the nineteenth inverter, and the CK input end of each stage of D trigger and the input end of the nineteenth inverter are connected with the second frequency division unit.

5. The control circuit of claim 1, further comprising: and the power-on reset unit is connected with the first frequency division unit, the second frequency division unit and the first output unit and is configured to be connected with a direct-current power supply and generate the power-on reset signal.

6. The control circuit of claim 5, wherein the power-on reset unit comprises: the first PMOS tube, the third capacitor, the twenty-first inverter and the twenty-second inverter;

7. The control circuit of any of claims 1-6, further comprising: the second output unit is connected with the first output unit and is configured to perform a second logic operation on the L paths of driving signals to obtain a multipath driving optimized signal;

8. A lighting system comprising the control circuit of any one of claims 1-7, and a plurality of LED lamps, which are connected to the control circuit and are flash-disturbed by the L driving signals.