CN208609172U - Imitate the integrated circuit and warning device of alarm song - Google Patents

Abstract

The utility model belongs to electronic circuit technology field, provides a kind of integrated circuit and warning device for imitating alarm song；The integrated circuit includes: control module, oscillator module, frequency division module, beat module, address module, ROM module, audio-frequency module and output module；Wherein control module obtains trigger signal and reset signal, can control the work or halted state of the integrated circuit by trigger signal, audible device circulation can be driven to sound the alarm by reset signal；When trigger signal is the first level state, oscillator module generates oscillator signal, multiplex coding signal is obtained by carrying out repeatedly frequency dividing for oscillator signal, if changing the coded combination in multiplex coding signal, audio-frequency module has obtained the audio signal with different audio frequencies after dividing to oscillator signal；Solve the problems, such as that existing integrated circuit can not change the audio frequency of alarm song and circuit structure and can not carry out flexible design by the utility model.

Description

Imitate the integrated circuit and warning device of alarm song

Technical field

The utility model belongs to electronic circuit technology field more particularly to a kind of integrated circuit for imitating alarm song and alarm Device.

Background technique

In existing fire fighting truck alarm device, the prior art realizes that fire fighting truck is issued often through simulation sound chip The function of alarm song passes through the simulation sound chip by the IC design containing simulation sound chip in alarm device Driving audible device circulation sends out fire fighting truck alarm song；Therefore, the integrated electricity to sound the alarm is imitated in existing fire fighting truck In road the prior art has at least the following problems: 1, due to realizing generation alarm song using simulation sound chip, when will simulate sound chip When applying in the integrated circuit for imitating alarm song, which can only intelligently drive the police of audible device generation fixed frequency Report sound, the i.e. audio frequency of the alarm song can not be adjusted；2, it is described imitate alarm song integrated circuit circuit structure without Method carries out simplifying design, and flexibility is low, reduces applicable generality of the integrated circuit in fire fighting truck warning device.

Utility model content

The utility model provides a kind of integrated circuit and warning device for imitating alarm song, it is intended to solve existing imitation police The integrated circuit of report sound can not change alarm song audio frequency and the problem of circuit structure can not carry out flexible design.

The utility model first aspect provides a kind of integrated circuit for imitating alarm song, comprising:

Pull up signal is accessed, is configured to obtain trigger signal and reset signal according to the pull up signal, clock signal Control module；

It is connect with the control module, is configured to generate oscillator signal when the trigger signal is the first level state Oscillator module；

It is connect with the control module and the oscillator module, is configured to believe the oscillation according to the reset signal Number carry out for the first time frequency dividing obtain the frequency division module of the clock signal and fractional frequency signal；

It connect, is configured to according to the reset signal to the fractional frequency signal with the control module and the frequency division module It carries out second of frequency dividing and obtains the beat module of carry signal；

It connect, is configured to according to the reset signal and the carry signal with the beat module and the control module Obtain the address module of the road N address signal；

It is connect with the address module, is configured to generate the ROM module of the road N encoded signal according to the road N address signal；

It connect, is configured to according to the road N encoded signal to the oscillation with the oscillator module and the ROM module Signal carries out third time frequency dividing and obtains the audio-frequency module of audio signal；And

It connect, is configured in the trigger signal in the first level state with the control module and the audio-frequency module Logical operation is carried out to the audio signal and obtains the output module of sound driver signal；

Wherein the N is the positive integer more than or equal to 8.

The utility model second aspect provides a kind of warning device, including integrated circuit as described above, and:

It is connect with the integrated circuit, is configured to sound an alarm letter according to the sound driver signal that the integrated circuit generates Number audible device.

The utility model acquired advantageous effects compared with the existing technology are as follows: in the integrated of above-mentioned imitation alarm song In circuit, since control module obtains trigger signal and reset signal according to pull up signal, clock signal, pass through the trigger signal Level state be can control the imitation alarm song integrated circuit be connected or shutdown, can make to integrate by the reset signal Modules in circuit, which execute, resets operation, and then audible device circulation is driven to sound the alarm, and scalability is strong, improves The applicable generality of the integrated circuit；Coded combination by changing the road N encoded signal is the audio frequency of changeable audio signal Rate, and then audible device is driven to generate the alarm song with different audio frequencies, improve the practicability of fire fighting truck；To effectively Ground, which solves, to be imitated the integrated circuit of alarm song in the prior art and can not change the audio frequency of alarm song and flexibility is low asks Topic.

Detailed description of the invention

Fig. 1 is a kind of application system frame diagram of integrated circuit for imitating alarm song provided by the embodiment of the utility model；

Fig. 2 is a kind of function structure chart of integrated circuit for imitating alarm song provided by the embodiment of the utility model；

Fig. 3 is a kind of function structure chart of control module provided by the embodiment of the utility model；

Fig. 4 is a kind of circuit structure diagram of power on reset unit provided by the embodiment of the utility model；

Fig. 5 is a kind of circuit structure diagram of signal generation unit provided by the embodiment of the utility model；

Fig. 6 is a kind of circuit structure diagram of oscillator module provided by the embodiment of the utility model；

Fig. 7 is a kind of circuit structure diagram of frequency division module provided by the embodiment of the utility model；

Fig. 8 is a kind of circuit structure diagram of beat module provided by the embodiment of the utility model；

Fig. 9 is a kind of circuit structure diagram of address module provided by the embodiment of the utility model；

Figure 10 is a kind of function structure chart of ROM module provided by the embodiment of the utility model；

Figure 11 is a kind of circuit structure diagram of translator unit provided by the embodiment of the utility model；

Figure 12 is a kind of circuit structure diagram of cell encoder provided by the embodiment of the utility model；

Figure 13 is a kind of circuit structure diagram of audio-frequency module provided by the embodiment of the utility model；

Figure 14 is a kind of circuit structure diagram of compound flip-flop array provided by the embodiment of the utility model；

Figure 15 is a kind of circuit structure diagram of output module provided by the embodiment of the utility model；

Figure 16 is a kind of internal circuit configuration figure of compound trigger provided by the embodiment of the utility model.

Specific embodiment

The utility model discloses a kind of integrated circuit 10 for imitating alarm song, which is mainly used in fire-fighting In vehicle 400, wherein figure 1 illustrate the application system frames of integrated circuit 10 provided by the utility model embodiment；Optionally, Audible device 20 is loudspeaker or piezo etc..

Fig. 2 shows the modular structure of the integrated circuit 10 provided by the embodiment of the utility model for imitating alarm song, such as Fig. 2 It is shown, the integrated circuit 10 are as follows: control module 101, oscillator module 102, frequency division module 103, beat module 104, address mould Block 105, ROM module 106, audio-frequency module 107 and output module 108；Wherein, control module 101 accesses pull up signal TG, root Trigger signal EN and reset signal RESET is generated according to pull up signal TG and clock signal S1；Since control module 101 is generated Trigger signal EN has varying level state, such as high level, low level, i.e. controllable by the level state of trigger signal EN The conducting of modules or off state in integrated circuit 10；Reset signal RESET can be used for realizing each in integrated circuit 10 The reset of a unit operates, and so that the integrated circuit 10 is made a sound driving signal BD, BDB to the circulation of audible device 20, passes through sound Sound driving signal BD, the BDB driving circulation of audible device 20 sends out alarm song.

Oscillator module 102 is connect with control module 101, and trigger signal EN is transmitted to oscillator mould by control module 101 Block 102, when trigger signal EN is the first level state, 102 outputting oscillation signal OSC of oscillator module；Optionally, the touching Signalling EN is that the first level state is high level state or low level state, is not limited this herein；As a kind of excellent The embodiment of choosing, trigger signal EN herein are that the first level state refers to that trigger signal EN is high level state, that is, are only had When the trigger signal EN generated of control module 101 is high level state, oscillator module 102 just understands outputting oscillation signal OSC；Conversely, the second electrical level state refers to low level state, then oscillator mould if trigger signal EN is second electrical level state Block 102 stops working, and can't generate oscillator signal OSC；Therefore pass through the i.e. controllable oscillation of the level state of trigger signal EN Device module 102 stops or normal operating conditions.

Frequency division module 103 is connect with oscillator module 102 and control module 101, and frequency division module 103 is according to reset signal RESET carries out frequency dividing for the first time to oscillator signal OSC and obtains clock signal S1 and fractional frequency signal H1；Optionally, clock signal S1 Frequency and the frequency of fractional frequency signal H1 can be identical or not identical, on the one hand, integrated circuit 10 to fractional frequency signal H1 after Sound driver signal BD, BDB with specific frequency can be obtained in the continuous signal processing that carries out, and on the other hand, frequency division module 103 will Clock signal S1 is transmitted in control module 101, generates trigger signal EN by clock signal S1 drive control module 101； Beat module 104 is connect with frequency division module 103 and control module 101, and beat module 104 is according to reset signal RESET to frequency dividing Signal H1 carries out second of frequency dividing and obtains carry signal RLCK；Since the fractional frequency signal H1 generated of frequency division module 103 has spy Fixed audio frequency obtains carry signal RLCK after beat module 104 carries out second dividing to fractional frequency signal H1, the carry Signal can play the role of carry in integrated circuit 10, and integrated circuit 10 makes a sound driving letter to the circulation of audible device 20 Number BD, BDB, and then audible device 20 is driven switch broadcasting alarm song in order.

Address module 105 is connect with beat module 104 and control module 101, and control module 101 is by reset signal RESET It is transmitted to address module 105, based on reset signal RESET to realize that address module 105 carries out reset operation；Beat module 104 Carry signal RLCK is transmitted to address module 105, carry signal RLCK has the function of carry, address in address module 105 Module 105 obtains the road N address signal Q according to reset signal RESET and carry signal RLCK, and the road N address signal Q has a variety of Coded combination；ROM module 106 is connect with address module 105, and the road N address signal Q is transmitted to ROM module by address module 105 106, ROM module 106 generates the road N encoded signal D according to the road N address signal, and wherein encoded signal D in the road N has Multiple Code group It closes, if the wherein all the way coding in the encoded signal D of the road N changes, the generated sound driver signal BD of integrated circuit 10, The audio frequency of BDB can also occur to change accordingly, since the road N encoded signal D is combined with Multiple Code, then corresponding hair Acoustic equipment 20 produces the alarm song with a variety of audio frequencies under the driving of sound driver signal BD, BDB.

Audio-frequency module 107 is connect with oscillator module 102 and ROM module 106, and audio-frequency module 107 is according to the road N encoded signal D carries out third time frequency dividing to oscillator signal OSC and obtains audio signal TONE, as noted previously, as being generated by ROM module 106 The road N encoded signal D have a variety of different code combination modes, when ROM module 106 will be with particular code combination When the road N encoded signal D is transmitted to audio-frequency module 107, audio-frequency module 107 is according to the different code combinations pair of the road N encoded signal D After oscillator signal OSC carries out third time frequency dividing, to obtain the audio signal TONE with different audio frequencies；Illustratively, if N =8, the code combination of the encoded signal D on 8 tunnel generated of ROM module 106 are as follows: 01111101, at this point, audio-frequency module 107 Audio frequency according to the code combination mode of encoded signal D audio signal TONE generated is 545.4 hertz；It follows that If changing an arbitrary code in the encoded signal of the road N, it is equivalent to the code combination mode for changing the road N encoded signal, then Audio-frequency module 107 has just correspondingly generated the audio signal TONE with different audio frequencies, and then audible device 20 is driven to send out Provide the alarm song of different audio frequencies；Therefore, in integrated circuit 10, by changing the road N generated of ROM module 106 The code combination mode of encoded signal D can correspondingly adjust the audio frequency of alarm song, easy to operate, to improve collection At the applicable generality of circuit 10, the integrated circuit for overcoming imitation alarm song in the prior art can not change the audio of alarm song Frequency reduces the usage experience sense of user.

Output module 108 is connect with control module 101 and audio-frequency module 107, when the triggering generated of control module 101 is believed When number EN is the first level state, output module 108 to audio signal TONE carry out logical operation obtain sound driver signal BD, BDB；Output module 108 is also connect with audible device 20 simultaneously, and sound driver signal BD, BDB are transmitted to hair by output module 108 Acoustic equipment 20, and then audible device 20 is driven to sound the alarm；Thus, only working as the triggering generated of control module 101 Signal EN be the first level state when, output module 108 can just be connected and to audible device 20 make a sound driving signal BD, BDB, warning device 300 is in normal operating conditions at this time；Preferably, it is high that the trigger signal EN, which is the first level state, Level state；Therefore, pass through the i.e. controllable output module of the low and high level state of the trigger signal generated of control module 101 108 conducting or off state, so control integrated circuit 10 whether to audible device 20 make a sound driving signal BD, BDB, it is easy to operate, further simplify the structure of circuit；

It should be noted that N described above is the positive integer more than or equal to 8.

As an alternative embodiment, Fig. 3 shows the mould of control module 101 provided by the embodiment of the utility model Block structure is described in detail such as shown in figure 3, the control module 101 includes power on reset unit 1011 and signal generation unit 1012 Under:

Power on reset unit 1011 accesses DC power supply VDD and generates power-on reset signal POR, the power-on reset signal POR is used to carry out control module 101 during electrifying startup electrification reset protection, and then realizes and guarantee the integrated circuit 10 Normal work；Wherein signal generation unit 1012 is connect with power on reset unit 1011, and power on reset unit 1011 will power on Reset signal POR is transmitted to control signal generation unit 1012, and signal generation unit 1012 is according to power-on reset signal POR and upper The inversion signal TGB of signal TG is drawn to generate reset signal RESET, signal generation unit 1012 is according to reset signal RESET, clock Signal S1 and pull up signal TG generates trigger signal EN, and wherein clock signal S1 is generated by frequency division module 103, specifically, controlling In the modular structure of molding block 101, signal generation unit 1012 can generate reset signal RESET and trigger signal EN simultaneously.

As an alternative embodiment, Fig. 4 shows power on reset unit provided by the embodiment of the utility model 1011 circuit structure, power on reset unit 1011 include: the second PMOS tube PMOS2, the second capacitor C2, the 25th reverser INV25, the 26th reverser INV26 and the 27th reverser INV27；Wherein, the source electrode of the second PMOS tube PMOS2 connects The grounded-grid GND of DC power supply VDD, the second PMOS tube PMOS2, the drain electrode of the second PMOS tube PMOS2 and the 25th is reversely The input terminal of device INV25 is connected to the first end of the second capacitor C2 altogether, and the second end of the second capacitor C2 is grounded GND, and the 25th is anti- To the input terminal of the 26th reverser INV26 of output termination of device INV25, the output termination of the 26th reverser INV26 The output of the input terminal of 27th reverser INV27, the 27th reverser INV27 terminates signal generation unit 1012, uses In power-on reset signal POR is transmitted to signal generation unit 1012.

As an alternative embodiment, Fig. 5 shows signal generation unit provided by the embodiment of the utility model 1012 circuit structure, signal generation unit 1012 include: the first PMOS tube PMOS1, the first reverser INV1, the second reverser INV2, third reverser INV3, the 4th reverser INV4, the 5th reverser INV5, the 6th reverser INV6, the first nor gate NOR1, the second nor gate NOR2, the first d type flip flop ZDR1 and the first T trigger ZTR1.

Wherein the source electrode of the first PMOS tube PMOS1 meets DC power supply VDD, the grounded-grid GND of the first PMOS tube PMOS1, The drain electrode of first PMOS tube PMOS1 and the input terminal of the first reverser INV1 access pull up signal TG, specifically, due to first The drain electrode of PMOS tube PMOS1 and the external control button of input terminal of the first reverser INV1, when control button is pressed, this phase It is triggered over the ground when in control button, pull up signal TG is low level signal；If control button is not pressed, pulled up due to existing Resistance, pull up signal TG is high level signal at this time；The input of second reverser INV2 terminates frequency division module 103, for accessing Clock signal S1；The output end of second reverser INV2 and the input terminal of the 4th reverser INV4 are connected to the first d type flip flop altogether The CK input terminal of ZDR1, the CKB input terminal of the first d type flip flop ZDR1 of output termination of the 4th reverser INV4, third reverser The inversion signal TGB of the input terminal access pull up signal TG of INV3, the first input end of the first nor gate NOR1 connect reset Unit 1011, for accessing power-on reset signal POR；The second of the first nor gate NOR1 of output termination of third reverser INV3 Input terminal, the input terminal of the 5th reverser INV5 of output termination of the first nor gate NOR1, the output end of the 5th reverser INV5 For output reset signal RESET；The reset of the reset signal input terminal R of first d type flip flop ZDR1 and the first T trigger ZTR1 Signal input part R is connected to the output end of the 5th reverser INV5 altogether, when the output end of the 5th reverser INV5 is by reset signal When RESET is transmitted to the first d type flip flop ZDR1 and the first T trigger ZTR1, the first d type flip flop ZDR1 and the first T trigger ZTR1 executes reset operation under the driving of reset signal RESET；The Q output of first d type flip flop ZDR1 connects the first T trigger The CK input terminal of ZTR1, the CKB input terminal of the first T trigger ZTR1 of QB output termination of the first d type flip flop ZDR1, first is reversed The D input terminal of the output end of device INV1 and the first d type flip flop ZDR1 are connected to the first input end of the second nor gate NOR2 altogether, and first The Q output of T trigger ZTR1 connects the second input terminal of the second nor gate NOR2, the output termination the 6th of the second nor gate NOR2 The output end of the input terminal of reverser INV6, the 6th reverser INV6 exports trigger signal EN.

As an alternative embodiment, Fig. 6 shows oscillator module 102 provided by the embodiment of the utility model Circuit structure, as shown in fig. 6, oscillator module 102 includes: first capacitor C1, first resistor R1, the 7th reverser INV7, Eight reverser INV8, the 9th reverser INV9, the tenth reverser INV10, the 11st reverser INV11, the 12nd reverser INV12, the first NAND gate NAND1, the second NAND gate NAND2 and third NAND gate NAND3.

Wherein, the input terminal of the first end of first capacitor C1, the first end of first resistor R1 and the 7th reverser INV7 It is connected to the input terminal of the 8th reverser INV8 altogether, the output of the 8th reverser INV8 terminates the input terminal of the 9th reverser INV9, The first input end of the first NAND gate NAND1 of output termination of 7th reverser INV7, the second input of the first NAND gate NAND1 Terminate the output end of the second NAND gate NAND2, the first of the output end of the first NAND gate NAND1 and the second NAND gate NAND2 is defeated Enter the first input end that end is connected to third NAND gate NAND3 altogether, the output of the 9th reverser INV9 terminates the second NAND gate NAND2 The second input terminal, third NAND gate NAND3 second input termination control module 101, for accessing trigger signal EN；Third The input terminal of the tenth reverser INV10 of output termination of NAND gate NAND3, the output end of the tenth reverser INV10 and the first electricity The second end for holding C1 is connected to the input terminal of the 11st reverser INV11, the output end of the 11st reverser INV11 and the first electricity altogether The second end of resistance R1 is connected to the input terminal of the 12nd reverser INV12 altogether, and the output end of the 12nd reverser INV12 is oscillator The output end of module 102 is configured as output to oscillator signal OSC.

As an alternative embodiment, Fig. 7 shows the electricity of frequency division module 103 provided by the embodiment of the utility model Line structure, as shown in fig. 7, frequency division module 103 include: the 13rd reverser INV13, it is the 14th reverser INV14, the 15th anti- To device INV15 and the first T flip-flop array 1031；Wherein, the first T flip-flop array 1031 includes N+1 mutually cascade T The reset signal input terminal R of trigger, every level-one T trigger in the first T flip-flop array 1031 is connected to control module altogether 101, for reset signal RESET to be transmitted in every level-one T trigger in the first T flip-flop array 1031, and then the first T Flip-flop array 1031 is executed according to reset signal RESET resets operation；In the first T flip-flop array 1031, i-stage T touching The Q output of hair device ZTRi connects the CKB input terminal of i+1 grade T trigger ZTRi+1, the QB output end of i-stage T trigger ZTRi The CK input terminal of i+1 grade T trigger ZTRi+1 is connect, the i is 1 to any positive integer between N.

The input of 13rd reverser INV13 terminates oscillator module 102, for accessing oscillator signal OSC；13rd is anti- The input terminal of output end and the 14th reverser INV14 to device INV13 is connected to the first order in the first T flip-flop array 1031 altogether The CKB input terminal of T trigger, the output of the 14th reverser INV14 terminate first order T touching in the first T flip-flop array 1031 The CK input terminal of device is sent out, the Q output of N+1 grades of T triggers connects the 15th reverser in the first T flip-flop array 1031 The input terminal of INV15, the output end output frequency division signal H1 of the 15th reverser INV15.

It should be noted that after above-mentioned first T flip-flop array 1031 carries out first time frequency dividing to oscillator signal OSC Obtain clock signal S1 and fractional frequency signal H1；Specifically, the Q output of the first order T trigger in the first T flip-flop array 1031 End or QB output end export clock signal S1, the output end output frequency division signal H1 of the 15th reverser；Further, it divides Clock signal S1 is transmitted to control module 101 by module 103, and after 103 output frequency division signal H1 of frequency division module, integrates electricity Road 10 continues to divide to fractional frequency signal H1, and then obtains suitable audio frequency.

As an alternative embodiment, Fig. 8 shows the electricity of beat module 104 provided by the embodiment of the utility model Line structure, as shown in figure 8, beat module 104 includes: the 16th reverser INV16, the 17th reverser INV17, the 2nd D touching Send out device ZDR2, third d type flip flop ZDR3, the 2nd T trigger ZTR2 and the 3rd T trigger ZTR3.

Wherein, the input of the 16th reverser INV16 terminates frequency division module 103, for accessing fractional frequency signal H1；16th The CKB input terminal of the output end of reverser INV16, the CKB input terminal of the second d type flip flop ZDR2 and third d type flip flop ZDR3 It is connected to the input terminal of the 17th reverser INV17 altogether, the output end of the 17th reverser INV17 and third d type flip flop ZDR3's CK input terminal is connected to the CK input terminal of the second d type flip flop ZDR2, the reset signal input terminal R of the second d type flip flop ZDR2, second altogether The reset signal input terminal R of the reset signal input terminal R of T trigger ZTR2 and the 3rd T trigger ZTR3 are connected to control mould altogether Block 101, for accessing reset signal RESET, beat module 104 is executed according to reset signal RESET resets operation；2nd D touching The Q output of hair device ZDR2 meets the D input terminal of third d type flip flop ZDR3, the 3rd D of QB output termination of the second d type flip flop ZDR2 The QB output of the D input terminal and third d type flip flop ZDR3 of reset signal the input terminal R, the second d type flip flop ZDR2 of trigger ZDR3 End is connected to the CK input terminal of the 2nd T trigger ZTR2 altogether, and the Q output of third d type flip flop ZDR3 connects the 2nd T trigger ZTR2's The Q output of CKB input terminal, the 2nd T trigger ZTR2 connects the CKB input terminal of the 3rd T trigger ZTR3, the 2nd T trigger The CK input terminal of the 3rd T trigger ZTR3 of QB output termination of ZTR2, the QB output end output carry letter of the 2nd T trigger ZTR2 Number RLCK.

As an alternative embodiment, Fig. 9 shows the electricity of address module 105 provided by the embodiment of the utility model Line structure, as shown in figure 9, address module 105 includes: eighteen incompatibilities to device INV18, the 19th reverser INV19 and the 2nd T Flip-flop array 1051；Wherein, the 2nd T flip-flop array 1051 includes N number of cascade T trigger, in the 2nd T flip-flop array In 1051, the Q output of every level-one T trigger exports address signal all the way, the reset signal input terminal R of every level-one T trigger It is connected to control module 101 altogether, for accessing reset signal RESET, the 2nd T flip-flop array 1051 is according to reset signal RESET Carry out reset operation；The Q output of j-th stage T trigger ZTRj connects the CKB input terminal of+1 grade of T trigger ZTRj+1 of jth, j-th stage The CK input terminal of QB output termination+1 grade of T trigger ZTRj+1 of jth of T trigger ZTRj, wherein the j is 1 between N-1 Any positive integer.

Eighteen incompatibilities terminate beat module 104 to the input of device INV18, for accessing carry signal RLCK；Eighteen incompatibilities The input terminal of output end and the 19th reverser INV19 to device INV18 is connected to the 1st in the 2nd T flip-flop array 1051 altogether The CKB input terminal of grade T trigger, the output of the 19th reverser INV19 terminate the 1st grade of T in the 2nd T flip-flop array 1051 The CK input terminal of trigger.

As an alternative embodiment, Figure 10 shows the mould of ROM module 106 provided by the embodiment of the utility model Block structure, as shown in Figure 10, ROM module 106 include translator unit ROWDEC_F and cell encoder ROM_512, decoder Unit R OWDEC_F is connect with address module 105, and translator unit ROWDEC_F generates decoded signal X < 0 according to address signal Q: 31>；Optionally, a part of address signal in the address signal Q of the road N can be transmitted to translator unit by address module 105 ROWDEC_F；Wherein decoded signal X<0:31>is transmitted to cell encoder ROM_512 by translator unit ROWDEC_F, specifically , decoded signal X<0:31>includes 32 segment signals.

Wherein cell encoder ROM_512 is connect with translator unit ROWDEC_F and address module 105, translator unit Decoded signal X<0:31>is transmitted to cell encoder ROM_512 by ROWDEC_F, and address module 105 can be by the road N address signal Q In another part address signal be transmitted to cell encoder ROM_512, cell encoder ROM_512 according to decoded signal X < 0:31 > and address signal Q generates the road N encoded signal D.

As an alternative embodiment, Figure 11 shows translator unit provided by the embodiment of the utility model The circuit structure of ROWDEC_F, Figure 12 show the circuit knot of cell encoder ROM_512 provided by the embodiment of the utility model Structure, in conjunction with Figure 11 and Figure 12 it is found that translator unit ROWDEC_F is made of multiple CMOS tubes and the interconnection of multiple reversers, Similar, cell encoder ROM_512 is made of multiple CMOS tubes and the interconnection of multiple reversers；It is more by what is inputted Road address signal Q controls the conducting or shutdown of CMOS tube, so that there is the output of ROM module 105 road N of different code combination to compile Code signal D.

As a preferred embodiment, in the modular structure of above-mentioned ROM module 105, translator unit ROWDEC_ The leakproof electric signal input end of F and the leakproof electric signal input end of cell encoder ROM_512 are connected to control module 101 altogether, match It is set to access trigger signal EN, with the leaky for preventing ROM module 105 from occurring during stopping working.

Optionally, Figure 13 shows the circuit structure of audio-frequency module 107 provided by the embodiment of the utility model, such as Figure 13 institute Show, audio-frequency module 107 include: the 20th reverser INV20, the 21st reverser INV21, the 22nd reverser INV22, 23rd reverser INV23, the 24th reverser INV24, third nor gate NOR3, the 4th T trigger ZTR4 and multiple Close flip-flop array 1071.

Wherein, compound flip-flop array 1071 is configured to believe oscillation to according to the road N encoded signal D as frequency dividing device Number OSC is repeatedly divided；Specifically, compound flip-flop array 1071 is cascaded by N number of compound trigger and at least one XOR gate It forms, coding is believed all the way for the reset signal input terminal J access of compound trigger described in every level-one in compound flip-flop array 1071 Number, the input of the 20th reverser INV20 terminates oscillator module 102, for accessing oscillator signal OSC；Compound trigger battle array The reversed clock signal input terminal CKB of every compound trigger of level-one is connected to the output end of the 20th reverser INV20 altogether in column, multiple The positive clock signal input terminal CK for closing every compound trigger of level-one in flip-flop array is connected to the 21st reverser INV21 altogether Output end, the 21st reverser INV21 input termination the 20th reverser INV20 output end.

It should be noted that the compound trigger in above-mentioned compound flip-flop array 1071 includes N number of compound trigger, In compound trigger and the T trigger and d type flip flop of the art there is similar signal processing function, but compound touching The difference of hair device and the T trigger and d type flip flop of this field is that the compound trigger in the utility model embodiment also has Positive control terminal PS and Reverse Turning Control end PSB, the then signal accessed by forward direction control terminal PS and Reverse Turning Control end PSB The signal condition that the positive output end Q and inverse output terminal QB for controlling compound trigger are exported, i.e. the utility model embodiment In compound trigger have more signal control terminals, in order to clearly illustrate compound touching in the utility model embodiment The principle of work and power of device is sent out, Figure 16 shows the internal circuit configuration of compound trigger provided by the utility model embodiment, such as Shown in Figure 16, compound trigger is cascaded by reverser, CMOS tube and adder.

Wherein third nor gate NOR3 has N-1 input terminal, and the input of third nor gate NOR3 terminates compound trigger The output of the positive output end Q of compound trigger in array 1071, third nor gate NOR3 terminate the 22nd reverser INV22 Input terminal, every compound trigger of level-one is anti-in the output end of the 22nd reverser INV22, compound flip-flop array 1071 It is connected to the CKB input terminal of the 4th T trigger ZTR4 altogether to the input terminal of control terminal PSB and the 23rd reverser INV23, the The positive control terminal PS of every compound trigger of level-one in the output end and compound flip-flop array 1071 of 23 reverser INV23 It is connected to the CK input terminal of the 4th T trigger ZTR4, QB output the 24th reverser of termination of the 4th T trigger ZTR4 altogether The output end of the input terminal of INV24, the 24th reverser INV24 is configured as output to audio signal TONE；It should be noted that In above-mentioned audio-frequency module 107, the reset signal input termination control module 101 of the 4th T trigger ZTR4 resets letter for accessing Number RESET.

As an alternative embodiment, attached drawing 14 shows provided by the embodiment of the utility model multiple as N=8 The circuit structure of flip-flop array 1071 is closed, as shown in figure 14, compound flip-flop array 1071 includes 8 cascade compound triggerings Device and 3 XOR gates, the compound flip-flop array 1071 carry out oscillator signal OSC to obtain having different audios after repeatedly dividing The audio signal TONE of frequency；Wherein the frequency dividing mode of compound flip-flop array 1071 has the code combination side of 8 tunnel encoded signal D Formula determines.

As an alternative embodiment, Figure 15 shows output module 108 provided by the embodiment of the utility model Circuit structure, as shown in figure 15, output module 108 include: the 4th NAND gate NAND4, the 5th NAND gate NAND5, the 28th Reverser INV28, the 29th reverser INV29, the 30th reverser INV30, the 31st reverser INV31, the 30th Two reverser INV32, the 33rd reverser INV33 and the 34th reverser INV34；Wherein, the second eighteen incompatibilities are to device The second input terminal of the input terminal of INV28 and the 4th NAND gate NAND4 are connected to audio-frequency module 107 altogether, are used for incoming audio signal TONE；Second eighteen incompatibilities terminate the first input end of the 5th NAND gate NAND5, the 4th NAND gate NAND4 to the output of device INV28 First input end and the second input terminal of the 5th NAND gate NAND5 be connected to control module 101 altogether, for accessing trigger signal The input terminal of the 29th reverser INV29 of output termination of EN, the 4th NAND gate NAND4, the 29th reverser INV29's The input terminal of the 30th reverser INV30 of output termination, the output of the 30th reverser INV30 terminate the 31st reverser The input terminal of INV31, the output end sending and receiving acoustic equipment 20 of the 31st reverser INV31, for passing sound driver signal BD Transport to audible device 20；The input terminal of the 32nd reverser INV32 of output termination of 5th NAND gate NAND5, the 32nd The input terminal of the 33rd reverser INV33 of output termination of reverser INV32, the output end of the 33rd reverser INV33 The input terminal of the 34th reverser INV34 is connect, the output end sending and receiving acoustic equipment 20 of the 34th reverser INV34, being used for will Sound driver signal BDB is transmitted to audible device 20.

By the utility model embodiment, in integrated circuit 10, control module 10 generates trigger signal EN and resets letter Number RESET, the work and halted state of integrated circuit, reset signal can be controlled by the level state of trigger signal EN RESET plays the role of reset in integrated circuit 10, and then drives audible device 20 that can cyclically sound the alarm, because This, integrated circuit 10 has circuit structure simple, that scalability is strong, and the flexibility with higher of integrated circuit 10；Together When being changed due to the code combination of multiplex coding signal that ROM module 106 generates, the obtained sound of audio-frequency module 107 Frequency signal TONE also has different audio frequencies, and then audible device 20 is driven to issue the alarm with different audio frequencies Sound.

It should be noted that, in this document, such as multiple, multichannel, multiple and a variety of etc the number referred both to greater than 1 Amount.

Claims (10)

1. a kind of integrated circuit for imitating alarm song characterized by comprising

Pull up signal is accessed, is configured to obtain the control of trigger signal and reset signal according to the pull up signal, clock signal Module；

It is connect with the control module, is configured to generate the oscillation of oscillator signal when the trigger signal is the first level state Device module；

Connect with the control module and the oscillator module, be configured to according to the reset signal to the oscillator signal into Frequency dividing obtains the frequency division module of the clock signal and fractional frequency signal to row for the first time；

It is connect with the control module and the frequency division module, is configured to carry out the fractional frequency signal according to the reset signal Second of frequency dividing obtains the beat module of carry signal；

It is connect with the beat module and the control module, is configured to be obtained according to the reset signal and the carry signal The address module of the road N address signal；

It is connect with the address module, is configured to generate the ROM module of the road N encoded signal according to the road N address signal；

It connect, is configured to according to the road N encoded signal to the oscillator signal with the oscillator module and the ROM module It carries out third time frequency dividing and obtains the audio-frequency module of audio signal；And

It connect, is configured to when the trigger signal is in the first level state to institute with the control module and the audio-frequency module It states audio signal progress logical operation and obtains the output module of sound driver signal；

Wherein the N is the positive integer more than or equal to 8.

2. integrated circuit according to claim 1, which is characterized in that the control module includes:

It is configured to access DC power supply and generates the power on reset unit of power-on reset signal；

It connect, is configured to according to the power-on reset signal and the pull-up with the power on reset unit and the frequency division module The inversion signal of signal generates the reset signal, and is believed according to the reset signal, the clock signal and the pull-up Number generate the signal generation unit of the trigger signal.

3. integrated circuit according to claim 2, which is characterized in that the signal generation unit include: the first PMOS tube, First reverser, the second reverser, third reverser, the 4th reverser, the 5th reverser, the 6th reverser, the first nor gate, Second nor gate, the first d type flip flop and the first T trigger；

Wherein the source electrode of first PMOS tube meets DC power supply, the grounded-grid of first PMOS tube, the first PMOS The drain electrode of pipe and the input terminal of first reverser are configured to access the pull up signal, the input terminal of second reverser Connect the frequency division module, the input terminal of the output end of second reverser and the 4th reverser is connected to the first D altogether The CK input terminal of trigger, the output of the 4th reverser terminate the CKB input terminal of first d type flip flop, the third The input terminal of reverser is configured to access the inversion signal of the pull up signal, and the first input end of first nor gate meets institute State power on reset unit, the output of the third reverser terminates the second input terminal of first nor gate, described first or The output of NOT gate terminates the input terminal of the 5th reverser, the reset signal input terminal of the first d type flip flop and the first T touching The reset signal input terminal of hair device is connected to the output end of the 5th reverser altogether, and the Q output of first d type flip flop meets institute The CK input terminal of the first T trigger is stated, the QB output of first d type flip flop terminates the CKB input of the first T trigger The D input terminal of end, the output end of first reverser and first d type flip flop is connected to the first of second nor gate altogether Input terminal, the Q output of the first T trigger connect the second input terminal of second nor gate, second nor gate Output terminates the input terminal of the 6th reverser, and the output end of the 6th reverser is configured as output to the trigger signal.

4. integrated circuit according to claim 1, which is characterized in that the oscillator module includes: first capacitor, first Resistance, the 7th reverser, the 8th reverser, the 9th reverser, the tenth reverser, the 11st reverser, the 12nd reverser, One NAND gate, the second NAND gate and third NAND gate；

Wherein, the input terminal of the first end of the first capacitor, the first end of the first resistor and the 7th reverser It is connected to the input terminal of the 8th reverser altogether, the output of the 8th reverser terminates the input terminal of the 9th reverser, The output of 7th reverser terminates the first input end of first NAND gate, the second input terminal of first NAND gate Connect the output end of second NAND gate, the first input end of the output end of first NAND gate and second NAND gate is total It is connected to the first input end of the third NAND gate, the second of output termination second NAND gate of the 9th reverser is defeated Enter end, the second input of the third NAND gate terminates the control module, the output termination of the third NAND gate described the The input terminal of ten reversers, the output end of the tenth reverser and the second end of the first capacitor are connected to the described 11st altogether The input terminal of reverser, the output end of the 11st reverser and the second end of the first resistor are connected to the described 12nd altogether The output end of the input terminal of reverser, the 12nd reverser is configured as output to the oscillator signal.

5. integrated circuit according to claim 1, which is characterized in that the frequency division module includes: the 13rd reverser, 14 reversers, the 15th reverser and the first T flip-flop array；

Wherein, the first T flip-flop array includes N+1 mutually cascade T triggers, in the first T flip-flop array The reset signal input terminal of every level-one T trigger be connected to the control module altogether, in the first T flip-flop array, i-th The Q output of grade T trigger connects the CKB input terminal of i+1 grade T trigger, the QB output termination i+1 grade of i-stage T trigger The CK input terminal of T trigger, the i are 1 to any positive integer between N；

The input of 13rd reverser terminates the oscillator module, the output end of the 13rd reverser and described the The input terminal of 14 reversers is connected to the CKB input terminal of first order T trigger in the first T flip-flop array altogether, and described The output of 14 reversers terminates the CK input terminal of first order T trigger in the first T flip-flop array, the first T touching The Q output of N+1 grades of T triggers connects the input terminal of the 15th reverser, the 15th reverser in hair device array Output end be configured as output to the fractional frequency signal.

6. integrated circuit according to claim 1, which is characterized in that the beat module includes: the 16th reverser, 17 reversers, the second d type flip flop, third d type flip flop, the 2nd T trigger and the 3rd T trigger；

Wherein, the input of the 16th reverser terminates the frequency division module, the output end of the 16th reverser, described The CKB input terminal of the CKB input terminal of second d type flip flop and the third d type flip flop is connected to the 17th reverser altogether Input terminal, the output end of the 17th reverser and the CK input terminal of the third d type flip flop are connected to the 2nd D triggering altogether The CK input terminal of device, the reset signal input terminal of the reset signal input terminal of second d type flip flop, the 2nd T trigger And the reset signal input terminal of the 3rd T trigger is connected to the control module, the Q output of second d type flip flop altogether The D input terminal of the third d type flip flop is terminated, the QB output of second d type flip flop terminates the reset of the third d type flip flop The QB output end of signal input part, the D input terminal of second d type flip flop and the third d type flip flop is connected to the 2nd T altogether The CK input terminal of trigger, the Q output of the third d type flip flop connect the CKB input terminal of the 2nd T trigger, and described The Q output of two T triggers meets the CKB input terminal of the 3rd T trigger, the QB output termination institute of the 2nd T trigger The CK input terminal of the 3rd T trigger is stated, the QB output end of the 2nd T trigger is configured as output to the carry signal.

7. integrated circuit according to claim 1, which is characterized in that the address module includes: eighteen incompatibilities to device, 19 reversers and the 2nd T flip-flop array；

Wherein, the 2nd T flip-flop array includes N number of cascade T trigger, each in the 2nd T flip-flop array The Q output of grade T trigger is configured as output to address signal all the way, and the reset signal input terminal of every level-one T trigger is connected to altogether The control module, the Q output of j-th stage T trigger connect the CKB input terminal of+1 grade of T trigger of jth, j-th stage T trigger The CK input terminal of QB output termination+1 grade of T trigger of jth, wherein the j is 1 to any positive integer between N-1；

The eighteen incompatibilities terminate the beat module to the input of device, and the eighteen incompatibilities are to the output end of device and the described tenth The input terminal of nine reversers is connected to the CKB input terminal of the 1st grade of T trigger in the 2nd T flip-flop array altogether, and the described tenth The output of nine reversers terminates the CK input terminal of the 1st grade of T trigger in the 2nd T flip-flop array.

8. integrated circuit according to claim 1, which is characterized in that the ROM module includes:

It is connect with the address module, is configured to generate the translator unit of decoded signal according to the address signal；

It connect, is configured to raw according to the decoded signal and the address signal with the translator unit and the address module At the cell encoder of the road N encoded signal.

9. integrated circuit according to claim 1, which is characterized in that the audio-frequency module includes: the 20th reverser, 21 reversers, the 22nd reverser, the 23rd reverser, the 24th reverser, third nor gate, the 4th T touching Send out device and

It is configured to the compound flip-flop array repeatedly divided according to the road N encoded signal to the oscillator signal；

Wherein the compound flip-flop array is made of N number of compound trigger and the cascade of at least one XOR gate, the compound triggering The reset signal input terminal of compound trigger described in every level-one accesses encoded signal all the way, the 20th reverser in device array Input terminate the oscillator module, the reversed clock signal of every compound trigger of level-one is defeated in the compound flip-flop array Enter the output end that end is connected to the 20th reverser altogether, the forward direction of every compound trigger of level-one in the compound flip-flop array Clock signal input terminal is connected to the output end of the 21st reverser altogether, and the input of the 21st reverser terminates institute State the output end of the 20th reverser；

Wherein the third nor gate has N-1 input terminal, and the input of the third nor gate terminates the compound trigger The positive output end of compound trigger in array, the output of the third nor gate terminate the input of the 22nd reverser End, the Reverse Turning Control of every compound trigger of level-one in the output end of the 22nd reverser, the compound flip-flop array The input terminal of end and the 23rd reverser is connected to the CKB input terminal of the 4th T trigger altogether, and the described 23rd The positive control terminal of every compound trigger of level-one is connected to described altogether in the output end of reverser and the compound flip-flop array The CK input terminal of four T triggers, the QB output of the 4th T trigger terminate the input terminal of the 24th reverser, institute The output end for stating the 24th reverser is configured as output to the audio signal.

10. a kind of warning device, which is characterized in that including integrated circuit as described in any one of claim 1 to 9, and:

It is connect with the integrated circuit, is configured to the sound driver signal signal an alert generated according to the integrated circuit Audible device.