CN108616792A - Imitate the integrated circuit and warning device of alarm song - Google Patents
Imitate the integrated circuit and warning device of alarm song Download PDFInfo
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- 238000005516 engineering process Methods 0.000 abstract description 4
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- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 description 6
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- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 description 3
- 101150070189 CIN3 gene Proteins 0.000 description 3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
- H04R3/12—Circuits for transducers, loudspeakers or microphones for distributing signals to two or more loudspeakers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R2430/00—Signal processing covered by H04R, not provided for in its groups
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Abstract
The invention belongs to electronic technology fields, provide a kind of integrated circuit and warning device imitating alarm song；The integrated circuit includes：Control module, oscillator module, audio-frequency module, address module, ROM module and output module, wherein control module access push button signalling, and generate enable signal and reset signal according to push button signalling, oscillator signal and cycle signal；Audio-frequency module is adjusted the frequency of oscillator signal according to the roads N encoded signal to obtain note signal；Address module generates N+2 road address signals according to note signal and generates cycle signal according to the roads N+2 address signal；ROM module carries out coding and decoding to the roads N address signal and generates the roads N encoded signal；When enable signal is the first level state, output module can export sound driver signal；Existing alarm device integrated circuit can be efficiently solved through the invention can not generate the alarm song with different frequency, the small problem of the scope of application.
Description
Technical field
The invention belongs to electronic technology field more particularly to a kind of integrated circuits and warning device imitating alarm song.
Background technology
In the prior art, alarm device is independent as police car, essential electronic equipment, inside the alarm device
Integrated circuit it is often extremely complex, need when in use by the alarm device configuration on police car.Therefore, in existing police car
In alarm device, in order to realize warning function, the integrated circuit inside the alarm device is often extremely complex, leads to the police
The volume of reporting device is larger；And in the process of moving due to police car, alarm device needs to carry out to send out for a long time, repeatedly same
Kind alarm song, and the circuit structure of integrated circuit is set in advance in existing alarm device, and electricity is integrated in alarm device to pass through
The alarm acoustic frequency that road is sent out is single, can not be applicable in by the Application of integrated circuit in the alarm device of different type police car
Range is smaller.
Invention content
The present invention provides a kind of integrated circuit and warning device imitating alarm song, it is intended to solve in existing alarm device
It is complicated existing for integrated circuit, the alarm song with different frequency can not be generated, and then what is resulted in a smaller scope of application asks
Topic.
First aspect present invention provides a kind of integrated circuit imitating alarm song, including：
Push button signalling is accessed, is configured to generate enable signal according to the push button signalling, oscillator signal and cycle signal
With the control module of reset signal；
It is connect with control module, is configured to generate the oscillator signal when the enable signal is the first level state
Oscillator module；
It is connect with the oscillator module, is configured to adjust the frequency of the oscillator signal according to the roads N encoded signal
Section obtains the audio-frequency module of note signal, wherein the N is the positive integer more than or equal to 7；
It is connect with the audio-frequency module, the control module, is configured to generate the roads N+2 address letter according to the note signal
Number and generate the address module of the cycle signal according to the roads N+2 address signal；
It is connect with described address module and the audio-frequency module, is configured to that the roads N+2 address signal encode to translate
Code generates the ROM module of the roads N encoded signal；And
It connect, is configured to when the enable signal is the first level state with described address module and the control module
The output module that logical operation generates sound driver signal is carried out to the inversion signal of described address signal.
Second aspect of the present invention provides a kind of warning device, including integrated circuit as described above, and：
It is connect with the integrated circuit, is configured to send out alarm signal according to the sound driver signal that the integrated circuit generates
Number audio frequency apparatus.
Acquired advantageous effects are the present invention compared with the existing technology：In the integrated circuit of above-mentioned imitation alarm song
In, the reset signal generated by control module carries out reset operation to each signal in said integrated circuit, you can realizing should
The function of alarm song loop play；The alarm device can be made to send out tool by setting the note code in the roads the N encoded signal
There are many alarm songs of frequency, simplify the circuit structure of the integrated circuit, and it is general to improve being applicable in for the integrated circuit and police car
All over property；To efficiently solve, integrated circuit structure inside alarm device in the prior art is complicated, can not generate with not
Same frequency alarm song, the problem of resulting in a smaller scope of application.
Description of the drawings
Fig. 1 is a kind of function structure chart of integrated circuit imitating alarm song provided in an embodiment of the present invention；
Fig. 2 is a kind of function structure chart of control module provided in an embodiment of the present invention；
Fig. 3 is a kind of circuit structure diagram of power on reset unit provided in an embodiment of the present invention；
Fig. 4 is a kind of circuit structure diagram of control signal generation unit provided in an embodiment of the present invention；
Fig. 5 is a kind of circuit structure diagram of oscillator module provided in an embodiment of the present invention；
Fig. 6 is a kind of circuit structure diagram of audio-frequency module provided in an embodiment of the present invention；
Fig. 7 is a kind of function structure chart of address module provided in an embodiment of the present invention；
Fig. 8 is the circuit structure diagram that a kind of address signal provided in an embodiment of the present invention generates unit；
Fig. 9 is the circuit structure diagram that a kind of cycle signal provided in an embodiment of the present invention generates unit；
Figure 10 is a kind of function structure chart of ROM module provided in an embodiment of the present invention；
Figure 11 is a kind of circuit structure diagram of translator unit provided in an embodiment of the present invention；
Figure 12 is a kind of circuit structure diagram of cell encoder provided in an embodiment of the present invention；
Figure 13 is a kind of circuit structure diagram of output module provided in an embodiment of the present invention；
Figure 14 is a kind of function structure chart of warning device provided in an embodiment of the present invention；
Figure 15 is a kind of function structure chart of police car provided in an embodiment of the present invention；
Figure 16 is a kind of internal circuit configuration figure of compound trigger provided in an embodiment of the present invention.
Specific implementation mode
Fig. 1 shows the modular structure of the integrated circuit 10 provided in an embodiment of the present invention for imitating alarm song, for the ease of
Illustrate, illustrate only with the relevant part of the embodiment of the present invention, details are as follows：
As shown in Figure 1, the integrated circuit 10 of the imitation alarm song includes control module 101, oscillator module 102, audio
Module 103, address module 104, ROM module 105 and output module 106；Wherein control module 101 accesses push button signalling TG,
And enable signal EN and reset signal RESET is generated according to push button signalling TG, oscillator signal OSC and cycle signal SET, this is multiple
Position signal RESET is configured to that the cycle-index of 10 the played alarm song of integrated circuit is arranged, when the alarm of the integrated circuit 10
When sound all finishes, reset signal RESET is played reset role；Oscillator module 102 and 101 two-way company of control module
It connects, oscillator module 102 can be to 101 outputting oscillation signal OSC of control module, while control module 101 also can be to oscillator
Module 102 exports enable signal EN, wherein when the enable signal EN that control module 101 exports is the first level state, oscillation
Device module 102 generates oscillator signal OSC；Specifically, the i.e. controllable oscillator module of level state for passing through enable signal EN
102 conductings or off state, if enable signal EN is in the first level state, oscillator module 102 works normally simultaneously
Outputting oscillation signal OSC；If conversely, when enable signal EN is in second electrical level state, oscillator module 102 just stops work
Make, the oscillator module 102 can't outputting oscillation signal OSC at this time；Preferably, first level state is high level
State, the second electrical level state are low level state；Optionally, oscillator signal OSC is square wave.
Audio-frequency module 103 is connect with oscillator module 102, and audio-frequency module 103 is according to the roads N encoded signal D to oscillator signal
It is the positive integer more than or equal to 7 that the frequency of OSC, which is adjusted and obtains note signal TONE, wherein N,；In order to keep this integrated
The frequency for the alarm song that circuit 10 generates is adjustable, integrated by the way that this can be changed in adjusting N road encoded signal D per coding all the way
The alarm acoustic frequency that circuit 10 ultimately generates, the i.e. integrated circuit 10 have the function of frequency dividing；By setting the roads the N encoded signal
Per the code of encoded signal all the way in D, to which the roads N encoded signal D is combined with Multiple Code；And in the encoded signal D of the roads N
Each code combination all represent a kind of corresponding frequency note；Such as audio-frequency module 103 receives 6 tunnel encoded signals, wherein
The code combination of this 6 tunnel encoded signal D0~D6 is 0101010, and audio-frequency module 103 is based on 6 tunnel encoded signal D0~D6 at this time
Produce the note signal TONE with specific frequency；It should when therefore by the code combination mode of change N road encoded signal D
Integrated circuit 10 generates the alarm song with multi-frequency.
Address module 104 is connect with control module 101, audio-frequency module 103, and wherein audio-frequency module 103 is by note signal
TONE is transmitted to address module 104, and note signal TONE has the function of realizing carry, ensures that the integrated circuit 10 can follow
The broadcasting alarm song in order of ring；Address module 104 generates N+2 road address signal Q according to note signal TONE, and according to N+
2 road address signal Q generate cycle signal SET, and cycle signal SET is arranged for carrying out cycle of the signal in the integrated circuit 10
Transmission；Cycle signal SET is transmitted to control module 101, and then control module 101 and address module by address module 104 simultaneously
It carries out two-way signal between 104 to send and receive, to realize complicated signal processing function.
ROM module 105 is connect with address module 104 and audio-frequency module 103, and address module 104 is to the roads N+2 address signal Q
N road encoded signal D are generated after carrying out coding and decoding operation；Since the generation N+2 of address module 104 road address signal Q can not be direct
It is identified by audio-frequency module 103, being converted the roads N+2 address signal Q to by coding and decoding operation can be direct with audio-frequency module 103
The compatible roads N encoded signal D；Further, when the roads N encoded signal D is transmitted to audio-frequency module 103 by ROM module 105, sound
Frequency module 103 is adjusted the frequency of oscillator signal OSC according to the particular code combining form of the roads N encoded signal D, to logical
The roads the N encoded signal D for crossing the generation of ROM module 105 controls the frequency of the integrated circuit 10 output alarm song.
Output module 106 is connect with address module 104, control module 101, and control module 101 transmits enable signal EN
To output module 106, if enable signal EN is the first level state, inversion signal of the output module 106 to address signal Q
Sound driver signal OUT is generated after carrying out logical operation；Wherein, output module 106 is also connect with audio frequency apparatus 20, output module
Sound driver signal OUT is transmitted to audio frequency apparatus 20 by 106, and audio frequency apparatus 20 is sent out under the driving of sound driver signal OUT
The alarm song of cycle；It should be noted that since the address signal Q that address module 104 generates includes the roads N+2, and output module
106 can both choose the inversion signal of the signal all the way of certain in address signal QLogical operation is carried out, address signal can also be chosen
The inversion signal of multiple signals in QLogical operation is carried out, both selection modes can ensure that output module 106 can be defeated
Go out sound drive signal OUT；Wherein control module 101 controls leading for output module 106 by the level state of enable signal EN
Logical or shutdown situation；I.e. only when enable signal EN is the first level state, output module 106 can generate sound drive
Dynamic signal OUT；If enable signal EN on the contrary is second electrical level state, output module 106 can't generate sound driver signal,
Integrated circuit 10 is in halted state at this time, and audio frequency apparatus 20 can't sound the alarm；Preferably, enable signal EN herein
For the first level state refer to enable signal EN it is high level state, and it refers to enabled letter that enable signal EN, which is second electrical level state,
Number EN is low level state.
Specifically, Fig. 2 shows the modular structure of control module 101 provided in an embodiment of the present invention, as shown in Fig. 2, control
Molding block 101 includes power on reset unit 1011 and control signal generation unit 1012, and wherein power on reset unit 1011 accesses
DC power supply VDD simultaneously generates power-on reset signal POR, and power-on reset signal POR is configured to open control module 101 powering on
Electrification reset protection is carried out during dynamic, and then realizes the normal work for ensureing the integrated circuit 10；Wherein control signal generates
Unit 1012 is connect with power on reset unit 1011, and power-on reset signal POR is transmitted to control letter by power on reset unit 1011
Number generate unit 1012, control signal generation unit 1012 according to power-on reset signal POR, push button signalling TG, oscillator signal OSC
And cycle signal SET generates enable signal EN and reset signal RESET, wherein enable signal EN configures the integrated electricity in order to control
The work on road 10 and halted state, reset signal RESET configure the time of the 10 loop play alarm song of integrated circuit in order to control
And number.
Specifically, Fig. 3 shows the circuit structure of power on reset unit 1011 provided in an embodiment of the present invention, such as Fig. 3 institutes
Show, which includes：Second PMOS tube PMOS2, the second capacitance C2, the 26th reverser INV26, second
17 reverser INV27 and the second eighteen incompatibilities are to device INV28；The source electrode of wherein the second PMOS tube PMOS2 connects DC power supply
VDD, can be to 101 DC power output of control module, the grounded-grid of the second PMOS tube PMOS2 by DC power supply VDD
The drain electrode of GND, the second PMOS tube PMOS2 and the input terminal of the 26th reverser INV26 are connected to the first of the second capacitance C2 altogether
The second end at end, the second capacitance C2 is grounded GND, and the output of the 26th reverser INV26 terminates the 27th reverser INV27
Input terminal, the output of the 27th reverser INV27 terminates input terminal of second eighteen incompatibilities to device INV28, the second eighteen incompatibilities
Control signal generation unit 1012 is terminated to the output of device INV28, and the second eighteen incompatibilities are to power on to the output end of device INV28
The output end of reset unit 1011 is configured to power-on reset signal POR being transmitted to control signal generation unit 1012.
Specifically, Fig. 4 shows the circuit structure of control signal generation unit 1012 provided in an embodiment of the present invention, such as scheme
Shown in 4, control signal generation unit 1012 includes：First PMOS tube PMOS1, the first reverser INV1, the second reverser INV2,
Third reverser INV3, the 4th reverser INV4, the 5th reverser INV5, the 6th reverser INV6, the 7th reverser INV7,
Eight reverser INV8, the 9th reverser INV9, the first nor gate NOR1, the second nor gate NOR1, third nor gate NOR3, D are touched
Send out device ZDR, the first T triggers ZTR1 and the 2nd T triggers ZTR2.
The input terminal of wherein the first reverser INV1 is configured to access oscillator signal OSC, the output of the first reverser INV1
The CKB input terminals of end and the first T triggers ZTR1 are connected to the input terminal of the second reverser INV2 altogether, and the second reverser INV2's is defeated
Go out the CK input terminals of the first T triggers ZTR1 of termination, the source electrode of the first PMOS tube PMOS1 connects DC power supply VDD, the first PMOS tube
The drain electrode of grounded-grid GND, the first PMOS tube PMOS1 of PMOS1 and the input terminal of third reverser INV3 be configured to access by
The QB output ends of the first T triggers ZTR1 of input termination of key signals TG, the 4th reverser INV4, the 5th reverser INV5's is defeated
Enter to terminate the inversion signal TGB of push button signalling TG, the output end of the 4th reverser INV4 and the CK input terminals of d type flip flop ZDR are total
It is connected to the input terminal of the 6th reverser INV6, the CKB input terminals of the output termination d type flip flop ZDR of the 6th reverser INV6, first
The first input end of nor gate NOR1 meets power-on reset signal POR, wherein the first input end of the first nor gate NOR1 connects electricity
The output end of reset unit 1011；The second input terminal of the first nor gate NOR1 of output termination of 5th reverser INV5, first
The input terminal of the 7th reverser INV7 of output termination of nor gate NOR1, the R input of d type flip flop ZDR, the 2nd T triggers
The first input end of the R input of ZTR2 and the second nor gate NOR2 are connected to the output end of the 7th reverser INV7 altogether, and second
The second input termination control module 101 of nor gate NOR2, is configured to access cycle signal SET；Second nor gate NOR2's is defeated
Going out the input terminal of the 8th reverser INV8 of termination, the output end of the 8th reverser INV8 is configured as output to reset signal RESET, the
The Q output that the R input of one T triggers ZTR1 is configured to input reset signal RESET, d type flip flop ZDR connects the 2nd T triggerings
The CK input terminals of device ZTR2, the CKB input terminals of the 2nd T triggers ZTR2 of QB output terminations of d type flip flop ZDR, third nor gate
The first input end of NOR3 and the output end of third reverser INV3 are connected to the D input terminals of d type flip flop ZDR, the 2nd T triggers altogether
The Q output of ZTR2 connects the second input terminal of third nor gate NOR3, and the output of third nor gate BOR3 terminates the 9th reverser
The output end of the input terminal of INV9, the 9th reverser INV9 is configured as output to enable signal EN.
Specifically, in the circuit structure of above-mentioned control signal generation unit 1012, the drain electrode of the first PMOS tube PMOS1 and
The external pull-up resistor of input terminal of third reverser INV3, wherein push button signalling TG is generated by external key, when the external key
When being pressed, push button signalling TG is triggered over the ground, and push button signalling TG becomes low level, the inversion signal of push button signalling TG at this time
TGB becomes high level signal, and the input terminal of the 5th reverser INV5 accesses high level signal, then controls signal generation unit 1012
In normal work, control signal generation unit 1012 starts to export enable signal EN and reset signal RESET.
Specifically, Fig. 5 shows the circuit structure of oscillator module 102 provided in an embodiment of the present invention, as shown in figure 5,
The oscillator module 102 includes：First capacitance C1, first resistor R1, the tenth reverser INV10, the 11st reverser INV11,
12nd reverser INV12, the 13rd reverser INV13, the 14th reverser INV14, the 15th reverser INV15, first
NAND gate NAND1, the second NAND gate NAND2 and third NAND gate NAND3.
The input terminal of the wherein first end of first resistor R1, the first end of the first capacitance C1 and the tenth reverser INV10 is total
It is connected to the input terminal of the 11st reverser INV11, the 12nd reverser INV12's of output termination of the 11st reverser INV11
Input terminal, the first input end of the first NAND gate NAND1 of output termination of the tenth reverser INV10, the first NAND gate NAND1's
The output end of second the second NAND gate NAND2 of input termination, the first input end and the first NAND gate of the second NAND gate NAND2
The output end of NAND1 is connected to the first input end of third NAND gate NAND3 altogether, the output termination of the 12nd reverser INV12 the
Second input terminal of the second input terminal of two NAND gate NAND2, third NAND gate NAND3 is configured to access enable signal EN,
The output termination the 13rd of the second 101 third NAND gate NAND3 of input termination control module of middle third NAND gate NAND3 is reversed
It is reversed that the second end of the input terminal of device INV13, the output end of the 13rd reverser INV13 and the first capacitance C1 are connected to the 14th altogether
It is reversed that the input terminal of device INV14, the output end of the 14th reverser INV14 and the second end of first resistor R1 are connected to the 15th altogether
The output end of the input terminal of device INV15, the 15th reverser INV15 is configured as output to oscillator signal OSC；Therefore by controlling mould
The enable signal EN that block 101 is generated can control work or the halted state of oscillator module 102.
Specifically, Fig. 6 shows the circuit structure of audio-frequency module 103 provided in an embodiment of the present invention, as shown in fig. 6, sound
Frequency module 103 includes：16th reverser INV16, the 17th reverser INV17, eighteen incompatibilities are to device INV18, the 19th anti-
To device INV19, compound flip-flop array, the 3rd T triggers ZTR3, XOR gate XOR and four nor gate NOR4.
Wherein compound flip-flop array is cascaded by N number of compound trigger ZSR1, ZSR2 ... ZSRN-1, ZSRN, and
The positive output end Q of the compound trigger ZSRj-1 of previous stage meets the trigger signal input terminal D of the compound trigger ZSRj of next stage,
Middle j is 2 to the arbitrary positive integer between N；The input terminal of 16th reverser INV16 accesses oscillator signal OSC, then the 16th is anti-
Oscillator module 102 is terminated to the input of device INV16；Reversed clock letter in compound flip-flop array per the compound trigger of level-one
Number input terminal CKB is connected to the output end of the 16th reverser INV16, the input termination the 16th of the 17th reverser INV17 altogether
The output end of reverser INV16, the positive clock signal input terminal CK in compound flip-flop array per the compound trigger of level-one are total
It is connected to the output end of the 17th reverser INV17, the reset signal input in compound flip-flop array per the compound trigger of level-one
Holding J accesses, encoded signal, the trigger signal input terminal D of the compound trigger of the first order connect the output end of XOR gate XOR, exclusive or all the way
The first input end of door XOR meets the positive output end Q of N grades of compound triggers, the second input termination N-1 of XOR gate XOR
The positive output end Q of the compound trigger of grade.
There is wherein four nor gate NOR4 N-1 input terminal, the positive output end Q of the compound trigger ZSRi of i-stage to connect
The (i-1)-th input terminal of four nor gate NOR4, i are 2 to the arbitrary positive integer between N, and the output of four nor gate NOR4 terminates
Eighteen incompatibilities are to the input terminal of device INV18, Reverse Turning Control end PSB in compound flip-flop array per the compound trigger of level-one, the
Eighteen incompatibilities are connected to the 3rd T triggers ZTR3's altogether to the output end of device INV18 and the input terminal of the 19th reverser INV19
CKB input terminals, positive control terminal PS's and the 19th reverser INV19 in compound flip-flop array per the compound trigger of level-one
Output end is connected to the CK input terminals of the 3rd T triggers ZTR3 altogether, and the QB output ends of the 3rd T triggers ZTR3 are configured as output to note
Signal TONE.
It should be noted that the compound trigger in above-mentioned compound flip-flop array includes N number of compound trigger, wherein multiple
The T triggers and d type flip flop for closing trigger and the art have a similar signal processing function, but compound trigger
Difference lies in the compound trigger in the embodiment of the present invention also has positive control with the T triggers and d type flip flop of this field
PS and Reverse Turning Control end PSB is held, then the signal accessed by positive control terminal PS and Reverse Turning Control end PSB is i.e. controllable compound
The signal condition that the positive output end Q and inverse output terminal QB of trigger are exported, i.e., the compound triggering in the embodiment of the present invention
Utensil has more signal control terminals, in order to clearly illustrate the principle of work and power of compound trigger in the embodiment of the present invention,
Figure 16 shows the internal circuit configuration for the compound trigger that the embodiment of the present invention is provided, as shown in figure 16, compound trigger
It is cascaded by reverser, CMOS tube and adder.
Specifically, the R input of the 3rd T triggers ZTR3 connects control module 101, it is configured to access reset signal RESET,
Reset operation is carried out to audio-frequency module 103 by reset signal RESET.
Further, the circuit structure of the audio-frequency module 103 gone out according to Fig.6, passes through the 16th reverser INV16's
Input terminal accesses oscillator signal OSC, and compound flip-flop array is according to the code combination of the roads the N encoded signal of input to oscillator signal
The frequency of OSC is adjusted to obtain the note signal TONE of specific frequency, and then the integrated circuit 10 can export various frequencies
Alarm song.
Specifically, Fig. 7 shows the modular structure of address module 104 provided in an embodiment of the present invention, as shown in fig. 7, ground
Location module 104 includes that address signal generates unit 1041 and cycle signal generation unit 1042；Wherein address signal generates unit
1041 connect with audio-frequency module 103, control module 101, and note signal TONE is transmitted to address module 104 by audio-frequency module 103,
And reset signal RESET is transmitted to address module 104 by control module 101, and address signal generates unit 1041 according to note
Signal TONE and reset signal RESET generate N+2 road address signal Q；Cycle signal generates unit 1042 and is generated with address signal
Unit 1041, control module 101 connect, and address signal generates unit 1041 and the roads N+2 address signal Q is transmitted to cycle signal production
Power-on reset signal POR and clock signal S1 are transmitted to cycle signal and generate unit by raw unit 1042, control module 101
1042；It should be noted that clock signal S1 is generated by control module 101, specifically in conjunction with attached drawing 4, clock signal S1 is by
The QB output ends of one T triggers ZTR1 export；Wherein note signal TONE is arranged for carrying out the work(of carry in address module 104
Can, ensure that the integrated circuit 10 can switch broadcasting alarm song in sequence；Reset signal RESET is configured to address module
104 are resetted, and ensure that the integrated circuit 10 being capable of loop play alarm song.
Specifically, Fig. 8 shows that address signal provided in an embodiment of the present invention generates the circuit structure of unit 1041, such as scheme
Shown in 8, address signal generates unit 1041 and includes：20th reverser INV20, the 21st reverser INV21, the 22nd
Reverser INV22 and T flip-flop array.
Wherein T flip-flop arrays are cascaded by N+2 T trigger ZTR4, ZTR5 ... ZTRN+4, ZTRN+5, previous stage T
The Q output of the Q triggers of trigger ZTRk connects the CKB input terminals of next stage T triggers ZTRk+1, wherein k be 4,5 ... N+3,
Arbitrary positive integer in N+4, the CK input terminals of the QB output termination next stage T triggers ZTRk+1 of previous stage T triggers ZTRk,
The Q output of every level-one T triggers in T flip-flop arrays exports address signal Q1, Q2 ... QN+1, QN+2 all the way, T triggers
The R input of every level-one T triggers in array connects control module 101, is configured to access reset signal RESET, passes through reset
Signal RESET can make address signal generation unit 1041 carry out reset operation.
The input of wherein the 20th reverser INV20 terminates audio-frequency module 103, is configured to access note signal TONE；The
The CKB input terminals of first order T triggers ZTR4 in the output end and T flip-flop arrays of 20 reverser INV20 are connected to altogether
The input terminal of 21 reverser INV21, the output of the 21st reverser INV21 terminate the first order T in T flip-flop arrays
The input of the CK input terminals of trigger ZTR4, the 22nd reverser INV22 terminates the first order T triggerings in T flip-flop arrays
The Q output of device ZTR4, specifically, the first via address signal Q1 of the Q output output of first order T triggers ZTR4 passes through the
The inversion signal Q1B of 22 reverser INV22 output first via address signals Q1.
Specifically, Fig. 9 shows that cycle signal provided in an embodiment of the present invention generates the circuit structure of unit 1042, such as scheme
Shown in 9, cycle signal generates unit 1042 and includes：23rd reverser INV23, the 24th reverser INV24, the 20th
Five reverser INV25, the 4th NAND gate NAND4, the 5th NAND gate NAND5, the 5th nor gate NOR5, the 6th nor gate NOR6 with
And the 7th nor gate NOR7.
Wherein, the 4th NAND gate NAND4 tool is there are four input terminal, and the 5th NAND gate NAND5 tools are there are five input terminal, and the 7th
There are three input terminal, input terminal and the address signals of the 23rd reverser INV23 to generate unit 1041 and connect for nor gate NOR7 tools
It connects, is configured to access first via address signal Q1；The 4th NAND gate NAND4's of output termination of 23rd reverser INV23
First input end, the second input end grounding location signal generation unit 1041 of the 4th NAND gate NAND4 are configured to the second tunnel of access
Address signal Q2；The third input end grounding location signal generation unit 1041 of 4th NAND gate NAND4 is configured to access third road
Address signal Q3；The input end grounding location signal generation unit 1041 of 24th reverser INV24 is configured to the 4th tunnel of access
Address signal Q4；24th reverser INV24 output termination the 4th NAND gate NAND4 the 4th input terminal, the 5th with it is non-
The first input end of door NAND5 is grounded location signal generation unit 1041, is configured to the 5th road address signal Q5 of access；5th with it is non-
The second input end grounding location signal generation unit 1041 of door NAND5 is configured to the 6th road address signal Q6 of access；25th
The input end grounding location signal generation unit 1041 of reverser INV25 is configured to the 7th road address signal Q7 of access；25th
The third input terminal of the 5th NAND gate NAND5 of output termination of reverser INV25, the 4th input terminal of the 5th NAND gate NAND5
It is grounded location signal generation unit 1041, is configured to the 8th road address signal Q8 of access, the 5th input terminal of the 5th NAND gate NAND5
It is grounded location signal generation unit 1041, is configured to the 9th road address signal Q9 of access.
Wherein, the first input end of the 5th nor gate NOR5 of output termination of the 4th NAND gate NAND4, the 5th NAND gate
The second input terminal of the 5th nor gate NOR5 of output termination of NAND5, the output of the 5th nor gate NOR5 terminate the 6th nor gate
The first input end of NOR6, the first input end of the 7th nor gate NOR7 of output termination of the 6th nor gate NOR6, the 6th or non-
The output end of the second the 7th nor gate NOR7 of input termination of door NOR6, the second input terminal of the 7th nor gate NOR7 are configured to connect
Enter the clock signal S1, the third input terminal of the 7th nor gate NOR7 connects power on reset unit 1011, is configured to access and powers on
Reset signal POR, the output end of the 7th nor gate NOR7 are configured as output to cycle signal SET.
Specifically, Figure 10 shows the modular structure of ROM module 105 provided in an embodiment of the present invention, as shown in Figure 10,
ROM module includes translator unit ROWDEC_P and cell encoder ROM_512, wherein translator unit ROWDEC_P and address
Module 104 connects, and translator unit ROWDEC_P generates decoded signal according to address signal Q；Optionally, the address module 104
A part of address signal transmission in the address signal Q of the roads Ke Jiang N+2 is to translator unit ROWDEC_P；The translator unit
Decoded signal is transmitted to cell encoder ROM_512 by ROWDEC_P, and wherein decoded signal includes 32 segment signals.
Cell encoder ROM_512 is connect with translator unit ROWDEC_P, address module 104, translator unit
Decoded signal is transmitted to cell encoder ROM_512 by ROWDEC_P, and address module 104 is by the part in the address signal Q of the roads N+2
Address signal is transmitted to cell encoder ROM_512, and cell encoder ROM_512 generates N according to decoded signal and address signal
Road encoded signal D1, D2 ... DN-1, DN.
As an alternative embodiment, Figure 11 shows translator unit ROWDEC_P provided in an embodiment of the present invention
Circuit structure, Figure 12 shows the circuit structure of cell encoder ROM_512 provided in an embodiment of the present invention, in conjunction with Figure 11 and
Figure 12 it is found that translator unit ROWDEC_P by multiple CMOS tubes and multiple reversers interconnection form, it is similar, coding
Device unit R OM_512 is made of multiple CMOS tubes and the interconnection of multiple reversers；Pass through the multichannel address signal Q controls inputted
The conducting or shutdown of CMOS tube processed can make the roads the N encoded signal that there is the output of ROM module 105 different code to combine.
It should be noted that in the modular structure of above-mentioned ROM module 105, translator unit ROWDEC_P's is anticreep
The leakproof electric signal input end of signal input part and cell encoder ROM_512 are connected to control module 101 altogether, and being configured to access makes
Energy signal EN, with the leaky for preventing ROM module 105 from occurring during being stopped.
As an alternative embodiment, Figure 13 shows the circuit of output module 106 provided in an embodiment of the present invention
Structure, as shown in figure 13, output module 106 includes：29th reverser INV29, the 30th reverser INV30, the 30th
One reverser INV31, the 32nd reverser INV32, the 33rd reverser INV33, the 34th reverser INV34,
35 reverser INV35, the 6th NAND gate NAND6 and the 7th NAND gate NAND7.
Specifically, the first input end of the 6th NAND gate NAN6 and the second input terminal of the 7th NAND gate NAND7 are connected to altogether
Control module 101 is configured to access enable signal EN；The second input terminal and the 29th reverser of 6th NAND gate NAN6
The input terminal of INV29 is connected to address module 104 altogether, is configured to the reverse signal Q of access address signal Q；29th reverser
The first input end of the 7th NAND gate NAND7 of output termination of INV29, the output termination the 30th of the 6th NAND gate NAND6 are anti-
To the input terminal of device INV30, the input terminal of the 31st reverser INV31 of output termination of the 30th reverser INV30, third
The input terminal of the 32nd reverser INV32 of output termination of 11 reverser INV31, the output end of the 7th NAND gate NAND7
The input terminal of the 33rd reverser INV33 is connect, the output of the 33rd reverser INV33 terminates the 34th reverser
The input terminal of INV34, the input terminal of the 35th reverser INV35 of output termination of the 34th reverser INV34, the 30th
The output end of two reverser INV32 and the output end of the 35th reverser INV35 be configured as output to sound driver signal BD and
BDB；It should be noted that the above sound drive signal OUT includes sound driver signal BD and BDB herein.In conjunction with attached drawing 13
The circuit connection structure of shown output module 106, wherein the sound that the output end of the 32nd reverser INV32 is exported
The sound driver signal BDB opposite in phase that the output end of drive signal BD and the 35th reverser INV35 are exported.
Further, in the circuit structure of output module 106 shown by attached drawing 13, output module 106 is accessed by address
Module 104 generates the inversion signal of address signal QIn conjunction with described above, since address module 104 is according to note signal TONE
Generate N+2 road address signal Q, the i.e. inversion signal of address signal QAlso there is the roads N+2, as a preferred embodiment,
104 roads Ke Jiang N+2 inversion signal of address moduleIn reverse signal all the way (such as first via reverse signal Q1B) output to export
In module 106, then output module 106 is to the wherein inversion signal progress logical operation generation sound drive all the way in address signal Q
Dynamic signal OUT, and then drive integrated circult 10 sends out the alarm song with various frequencies.
As a preferred embodiment, the N is 7.
Through the embodiment of the present invention, in the integrated circuit 10 of above-mentioned imitation alarm song, since the generation of control module 101 makes
Energy signal EN and reset signal RESET, the level state by adjusting enable signal EN can control the work of integrated circuit 10
And halted state, cycle signal SET can realize the function of alarm song loop play in integrated circuit 10, greatly simplifie
The structure of circuit；Since the roads N encoded signal D has Multiple Code combining form, by the code-group for changing N road encoded signal D
Conjunction can be obtained the note signal TONE with different frequency, and then recyclable police of the broadcasting with different frequency of integrated circuit 10
Report sound；Efficiently solving the integrated circuit in existing alarm device can not generate with different frequency alarm song and circuit
Complicated problem.
Figure 14 shows that the modular structure of warning device 140 provided in an embodiment of the present invention, warning device 140 include as before
The integrated circuit 10 and audio frequency apparatus 1401；Wherein integrated circuit 10 is connect with audio frequency apparatus 1401, audio frequency apparatus 1401
The sound driver signal OUT signal an alerts generated according to integrated circuit 10；Since integrated circuit 10 can be by adjusting interior
The code combination form of the multiplex coding signal D in portion is to produce the note signal TONE of different frequency, at this time integrated circuit 10
The parameter of the sound driver signal OUT of generation can also occur to change accordingly, frequency, signal such as sound driver signal OUT
Amplitude etc.；Therefore, audio frequency apparatus 1401 under the driving of sound driver signal OUT can loop play there is different frequency
Alarm signal.
Preferably, in warning device 140, audio frequency apparatus 1401 is piezo or loudspeaker etc..
Figure 15 shows that the modular structure of police car 150 provided in an embodiment of the present invention, police car 150 include sound as described above
Frequency equipment 1401, when applying audio frequency apparatus 1401 in police car 150, police car 150 can be according to the different purposes of police car 150
Loop play has the alarm song of different frequency, enhances the practical performance of police car 150, has good application prospect.
Claims (10)
1. a kind of integrated circuit imitating alarm song, which is characterized in that including：
Push button signalling is accessed, be configured to generate enable signal according to the push button signalling, oscillator signal and cycle signal and is answered
The control module of position signal；
It is connect with control module, is configured to generate the oscillation of the oscillator signal when the enable signal is the first level state
Device module；
It is connect with the oscillator module, is configured to that the frequency of the oscillator signal is adjusted according to the roads N encoded signal
To the audio-frequency module of note signal, wherein the N is the positive integer more than or equal to 7；
Connect with the audio-frequency module, the control module, be configured to according to the note signal generate N+2 roads address signal,
And the address module of the cycle signal is generated according to the roads N+2 address signal；
It is connect with described address module and the audio-frequency module, is configured to carry out coding and decoding life to the roads N+2 address signal
At the ROM module of the roads N encoded signal；And
Connect with described address module and the control module, be configured to the enable signal for the first level state when to institute
The inversion signal for stating address signal carries out the output module that logical operation generates sound driver signal.
2. integrated circuit according to claim 1, which is characterized in that the control module includes：
It is configured to access DC power supply and generates the power on reset unit of power-on reset signal；With
It connect, is configured to according to the power-on reset signal, the push button signalling, oscillation letter with the power on reset unit
Number and the cycle signal generate the control signal generation unit of the enable signal and the reset signal.
3. integrated circuit according to claim 2, which is characterized in that the control signal generation unit includes：First
PMOS tube, the first reverser, the second reverser, third reverser, the 4th reverser, the 5th reverser, the 6th reverser, the 7th
Reverser, the 8th reverser, the 9th reverser, the first nor gate, the second nor gate, third nor gate, d type flip flop, the first T are touched
Send out device and the 2nd T triggers；
Wherein, the input terminal of first reverser is configured to access the oscillator signal, the output end of first reverser
It is connected to the input terminal of second reverser, the output of second reverser altogether with the CKB input terminals of the first T triggers
The CK input terminals of the first T triggers are terminated, the source electrode of first PMOS tube connects DC power supply, first PMOS tube
Grounded-grid, the drain electrode of first PMOS tube and the input terminal of the third reverser are configured to access the push button signalling,
The input of 4th reverser terminates the QB output ends of the first T triggers, and the input of the 5th reverser terminates institute
The inversion signal of push button signalling is stated, the output end of the 4th reverser and the CK input terminals of the d type flip flop are connected to described altogether
The input terminal of 6th reverser, the output of the 6th reverser terminate the CKB input terminals of the d type flip flop, described first or
The first input end of NOT gate connects the power-on reset signal, and the output of the 5th reverser terminates the of first nor gate
Two input terminals, the input terminal of output termination the 7th reverser of first nor gate, the R input of the d type flip flop,
The R input of the 2nd T triggers and the first input end of second nor gate are connected to the 7th reverser altogether
Output end, the second input terminal of second nor gate are configured to access the cycle signal, the output of second nor gate
The input terminal of the 8th reverser is terminated, the output end of the 8th reverser is configured as output to the reset signal, described
The R input of first T triggers is configured to input the reset signal, and the Q output of the d type flip flop meets the 2nd T and touches
The CK input terminals of device are sent out, the QB outputs of the d type flip flop terminate the CKB input terminals of the 2nd T triggers, the third or non-
The first input end of door and the output end of the third reverser are connected to the D input terminals of the d type flip flop altogether, and the 2nd T is touched
The Q output of hair device connects the second input terminal of the third nor gate, and the output termination the described 9th of the third nor gate is anti-
To the input terminal of device, the output end of the 9th reverser is configured as output to the enable signal.
4. integrated circuit according to claim 1, which is characterized in that the oscillator module includes：First capacitance, first
Resistance, the tenth reverser, the 11st reverser, the 12nd reverser, the 13rd reverser, the 14th reverser, the 15th are instead
To device, the first NAND gate, the second NAND gate and third NAND gate；
Wherein, the input terminal of the first end of the first resistor, the first end of first capacitance and the tenth reverser is total
It is connected to the input terminal of the 11st reverser, the output of the 11st reverser terminates the input of the 12nd reverser
End, the output of the tenth reverser terminate the first input end of first NAND gate, and the second of first NAND gate is defeated
Enter the output end for terminating second NAND gate, the output of the first input end of second NAND gate and first NAND gate
End is connected to the first input end of the third NAND gate altogether, and the output of the 12nd reverser terminates second NAND gate
Second input terminal, the second input terminal of the third NAND gate are configured to access the enable signal, the third NAND gate
Output terminates the input terminal of the 13rd reverser, the output end of the 13rd reverser and the second of first capacitance
End is connected to the input terminal of the 14th reverser, the output end of the 14th reverser and the second of the first resistor altogether
End is connected to the input terminal of the 15th reverser altogether, and the output end of the 15th reverser is configured as output to the oscillation letter
Number.
5. integrated circuit according to claim 1, which is characterized in that the audio-frequency module includes：16th reverser,
17 reversers, eighteen incompatibilities are to device, the 19th reverser, compound flip-flop array, the 3rd T triggers, XOR gate and
Four nor gate；
Wherein, the compound flip-flop array is cascaded by N number of compound trigger, and the forward direction of the compound trigger of previous stage
The trigger signal input terminal of the output termination compound trigger of next stage, the input terminal of the 16th reverser access the oscillation
Signal is connected to the described 16th in the compound flip-flop array altogether per the reversed clock signal input terminal of the compound trigger of level-one
The output end of reverser, the input of the 17th reverser terminates the output end of the 16th reverser, described compound tactile
It is connected to the output end of the 17th reverser in hair device array altogether per the positive clock signal input terminal of the compound trigger of level-one,
Reset signal input terminal access in the compound flip-flop array per the level-one compound trigger encoded signal all the way, first
The trigger signal input of the grade compound trigger terminates the output end of the XOR gate, and the first input end of the XOR gate connects
The positive output end of the N grades of compound triggers, the second input N-1 grades of compound triggers of termination of the XOR gate
Positive output end；
Wherein, the four nor gate has N-1 input terminal, described in the positive output of compound trigger described in i-stage terminates
(i-1)-th input terminal of four nor gate, the i are 2 to the arbitrary positive integer between N, and the output of the four nor gate terminates
The eighteen incompatibilities are to the input terminal of device, Reverse Turning Control end, institute in the compound flip-flop array per the compound trigger of level-one
State the CKB that eighteen incompatibilities are connected to the 3rd T triggers to the output end of device and the input terminal of the 19th reverser altogether
Input terminal, positive control terminal and the 19th reverser in the compound flip-flop array per the compound trigger of level-one it is defeated
Outlet is connected to the CK input terminals of the 3rd T triggers altogether, and the QB output ends of the 3rd T triggers are configured as output to the sound
Accord with signal.
6. integrated circuit according to claim 2, which is characterized in that described address module includes：
It is connect with the audio-frequency module, the control module, is configured to be generated according to the note signal and the reset signal
The address signal of the roads N+2 address signal generates unit；With
It connect, is configured to according to the roads N+2 address signal, described with the control module and described address signal generation unit
The cycle signal that power-on reset signal and clock signal generate the cycle signal generates unit.
7. integrated circuit according to claim 6, which is characterized in that described address signal generation unit includes：20th
Reverser, the 21st reverser, the 22nd reverser and T flip-flop arrays；
Wherein, the T flip-flop arrays are cascaded by N+2 T trigger, the Q outputs of the Q triggers of previous stage T triggers
Terminate the CKB input terminals of next stage T triggers, the CK inputs of the QB output termination next stage T triggers of previous stage T triggers
It holds, the Q output of every level-one T triggers in the T flip-flop arrays exports described address signal all the way, the T triggers
The R input of every level-one T triggers in array is configured to access the reset signal；
Wherein, the input terminal of the 20th reverser is configured to access the note signal, the 20th reverser it is defeated
The CKB input terminals of first order T triggers in outlet and the T flip-flop arrays are connected to the defeated of the 21st reverser altogether
Entering end, the output of the 21st reverser terminates the CK input terminals of the first order T triggers in the T flip-flop arrays,
The input of 22nd reverser terminates the Q output of the first order T triggers in the T flip-flop arrays.
8. the integrated circuit described according to claim 6 or 7, which is characterized in that the cycle signal generates unit and includes：Second
13 reversers, the 24th reverser, the 25th reverser, the 4th NAND gate, the 5th NAND gate, the 5th nor gate,
Six nor gates and the 7th nor gate；
Wherein, the 4th NAND gate tool is there are four input terminal, the 5th NAND gate tool there are five input terminal, the described 7th or
There are three input terminal, the input terminal of the 23rd reverser is configured to access the first via address signal, institute NOT gate tool
The output for stating the 23rd reverser terminates the first input end of the 4th NAND gate, the second input of the 4th NAND gate
End is configured to access second road address signal, and the third input terminal of the 4th NAND gate is configured to access the third road
Address signal, the input terminal of the 24th reverser are configured to access the 4th road address signal, the 24th reverser
Output terminates the 4th input terminal of the 4th NAND gate, and the first input end of the 5th NAND gate is configured to access described the
Five road address signals, the second input terminal of the 5th NAND gate are configured to access the 6th road address signal, and described second
The input terminal of 15 reversers is configured to access the 7th road address signal, and the output of the 25th reverser terminates institute
The third input terminal of the 5th NAND gate is stated, the 4th input terminal of the 5th NAND gate is configured to access the 8th tunnel address letter
Number, the 5th input terminal of the 5th NAND gate is configured to access the 9th road address signal；
The output of 4th NAND gate terminates the first input end of the 5th nor gate, the output end of the 5th NAND gate
The second input terminal of the 5th nor gate is connect, the output of the 5th nor gate terminates the first input of the 6th nor gate
End, the output of the 6th nor gate terminate the first input end of the 7th nor gate, and the second of the 6th nor gate is defeated
Enter the output end for terminating the 7th nor gate, the second input terminal of the 7th nor gate is configured to access the clock letter
Number, the third input terminal of the 7th nor gate is configured to access the power-on reset signal, the output of the 7th nor gate
End is configured as output to the cycle signal.
9. integrated circuit according to claim 1, which is characterized in that the ROM module includes：
It is connect with described address module, is configured to generate the translator unit of decoded signal according to described address signal；
It is connect with the translator unit and described address module, is configured to be given birth to according to the decoded signal and described address signal
At the cell encoder of the roads N encoded signal.
10. a kind of warning device, which is characterized in that including integrated circuit as described in any one of claim 1 to 9, and：
It is connect with the integrated circuit, is configured to the sound driver signal signal an alert generated according to the integrated circuit
Audio frequency apparatus.
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| JPH08211868A (en) * | 1988-03-03 | 1996-08-20 | Seiko Epson Corp | Sound signal generation device, sound signal generation method, and musical sound generation device including same |
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