CN108777899A - Control circuit and lighting system for generating multichannel means of chaotic signals - Google Patents
Control circuit and lighting system for generating multichannel means of chaotic signals Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
Abstract
The invention belongs to technical field of integrated circuits, provide a kind of control circuit and lighting system for generating multichannel means of chaotic signals；The control circuit includes：First oscillator unit, the second oscillator unit, the first frequency unit, the second frequency unit and the first output unit；First oscillator unit generates the first oscillator signal；Second oscillator unit generates the second oscillator signal；First frequency unit carries out repeatedly frequency dividing according to the first oscillator signal of power-on reset signal pair and obtains multi-channel frequency division signal；Second frequency unit carries out repeatedly frequency dividing according to the second oscillator signal of power-on reset signal pair and obtains trigger signal；First output unit carries out first time logical operation to trigger signal and multi-channel frequency division signal according to power-on reset signal and obtains the very poor drive signal of multichannel regularity；Can effectively solve through the invention integrated circuit in traditional technology can not Conduce Disciplinarian difference drive signal, and its realized circuit function is single, can not blanket problem.
Description
Technical field
The invention belongs to technical field of integrated circuits more particularly to a kind of control electricity for generating multichannel means of chaotic signals
Road and lighting system.
Background technology
Generally use large scale integrated circuit generates drive signal in traditional technology, and then realizes corresponding circuit function；
The functional requirement realized for electronic circuit however as people is more and more, passes through the generated drive signal of integrated circuit
Performance parameter also becomes to become increasingly complex；Traditional some signals of integrated circuit generally use generate chip to generate certain law
Property very strong signal, although these very strong signals of regularity can drive electronic component to realize more complicated function simultaneously,
It is contemplated that the functional requirement that some in electronic circuit are special, if very strong by the regularity that traditional integrated circuit is generated
Signal cannot achieve preferable circuit function；It is with the illumination of LED (Light Emitting Diode, light emitting diode) lamp
Example, people then need to obtain better light appreciation effect by electronic circuit generates irregular drive signal
Realize that multiple LED light carry out random sudden strain of a muscle, to bring good visual effect；However the integrated circuit of traditional technology can only give birth to
At the very strong drive signal of regularity, multiple LED light can not be driven to realize preferable disorderly sudden strain of a muscle effect.
Therefore, integrated circuit generally use signal generates chip and can be only generated the stronger drive of multichannel regularity in traditional technology
Dynamic signal, the circuit structure of itself are fixed, it is difficult to which the very poor drive signal of Conduce Disciplinarian leads to traditional integrated circuit institute
The circuit function of realization is single, and poor compatibility can not be generally applicable in, and the usage experience sense of user is relatively low.
Invention content
The present invention provides a kind of control circuit and lighting system for generating multichannel means of chaotic signals, it is intended to solve tradition
In technology integrated circuit can not Conduce Disciplinarian difference drive signal so that the circuit function list that causes integrated circuit to be realized
One, it can not blanket problem.
First aspect present invention provides a kind of control circuit for generating multichannel means of chaotic signals, including：
It is configured to generate the first oscillator unit of the first oscillator signal；
It is configured to generate the second oscillator unit of the second oscillator signal；
It is connect with first oscillator unit, is configured to carry out first oscillator signal according to power-on reset signal
N times divide to obtain the first frequency unit of the roads L fractional frequency signal；
It connect, is configured to according to the power-on reset signal to second oscillator signal with second oscillator unit
It carries out M frequency dividing and obtains the second frequency unit of trigger signal；And
It connect, is configured to according to the power-on reset signal pair with first frequency unit and second frequency unit
The trigger signal and the roads L fractional frequency signal carry out first time logical operation and obtain the first output unit of the roads L drive signal；
Wherein, the N, the L and the M are greater than or equal to 2 positive integer, and L is less than or equal to
N。
In one of which embodiment, first oscillator unit includes：First NAND gate, the second NAND gate,
One resistance, the first capacitance, the first reverser, the second reverser, third reverser, the 4th reverser, the 5th reverser, the 6th are instead
To device and the 7th reverser；
Wherein, the first end of the first resistor, the first end of first capacitance and first reverser is defeated
Enter the input terminal that end is connected to second reverser altogether, the output of second reverser terminates the first of second NAND gate
Input terminal, the second input of second NAND gate terminate the output end of first NAND gate, and the of first NAND gate
One input terminal and the output end of second NAND gate are connected to the input terminal of the 4th reverser altogether, first reverser
Output terminates the input terminal of the third reverser, and the second of output termination first NAND gate of the third reverser is defeated
Enter end, the output of the 4th reverser terminates the input terminal of the 5th reverser, the output end of the 5th reverser and
The second end of first capacitance is connected to the input terminal of the 6th reverser altogether, the output end of the 6th reverser and described
The second end of first resistor is connected to the input terminal of the 7th reverser, the output termination described first of the 7th reverser altogether
Frequency unit.
In one of which embodiment, second oscillator unit includes：Third NAND gate, the 4th NAND gate,
Two resistance, the second capacitance, the 8th reverser, the 9th reverser, the tenth reverser, the 11st reverser, the 12nd reverser,
13 reversers, the 14th reverser and the 15th reverser；
Wherein, the first end of the second resistance, the first end of second capacitance and the 8th reverser is defeated
Enter the input terminal that end is connected to the 9th reverser altogether, the output of the 9th reverser terminates the first of the 4th NAND gate
Input terminal, the second input of the 4th NAND gate terminate the output end of the third NAND gate, and the of the third NAND gate
One input terminal and the output end of the 4th NAND gate are connected to the input terminal of the 11st reverser, the 8th reverser altogether
Output terminate the input terminal of the tenth reverser, the output of the tenth reverser terminates the second of the third NAND gate
Input terminal, the output of the 11st reverser terminate the input terminal of the 12nd reverser, the 12nd reverser
The second end of output end and second capacitance is connected to the input terminal of the 13rd reverser altogether, the 13rd reverser
The second end of output end and the second resistance is connected to the input terminal of the 14th reverser altogether, the 14th reverser
Output terminates the input terminal of the 15th reverser, and the output of the 15th reverser terminates second frequency unit.
In one of which embodiment, first frequency unit includes：16th reverser and the first T trigger battle arrays
Row；Wherein, the first T flip-flop arrays include N number of cascade T triggers, each in the first T flip-flop arrays
The reset signal input terminal of grade T triggers is used for for accessing the power-on reset signal per the Q output of level-one T triggers
The fractional frequency signal is exported, the Q output of i-stage T triggers connects the CKB input terminals of i+1 grade T triggers, i-stage T triggerings
The CK input terminals of the QB output termination i+1 grade T triggers of device；
The CKB inputs of first order T triggers in the first T flip-flop arrays terminate the defeated of the 16th reverser
Outlet, the input terminal of the CK input terminals and the 16th reverser of the first order T triggers in the first T flip-flop arrays
It is connected to first oscillator unit altogether；The wherein described i is 1 to the arbitrary positive integer between N-1.
In one of which embodiment, second frequency unit includes：17th reverser, eighteen incompatibilities to device and
2nd T flip-flop arrays；Wherein, the 2nd T flip-flop arrays include M cascade T triggers, are triggered in the 2nd T
In device array, the reset signal input terminal per level-one T triggers is used to access the power-on reset signal, j-th stage T triggers
Q output meets the CKB input terminals of+1 grade of T trigger of jth, the CK of QB output termination+1 grade of T trigger of jth of j-th stage T triggers
Input terminal；
The CK inputs of first order T triggers in the input terminal of 17th reverser and the 2nd T flip-flop arrays
It holds and is connected to second oscillator unit altogether, in the 2nd T flip-flop arrays described in the QB output terminations of M grades of T triggers
For eighteen incompatibilities to the input terminal of device, the eighteen incompatibilities terminate first output unit to the output of device；Wherein, the j is 1
To the arbitrary positive integer between M-1.
In one of which embodiment, first output unit includes：19th reverser and d type flip flop array；
Wherein, the d type flip flop array includes L cascade d type flip flops, in the d type flip flop array, per level-one d type flip flop
Reset signal input terminal is for accessing the power-on reset signal, and the D input terminals access per level-one d type flip flop all the way believe by frequency dividing
Number, the Q output per level-one d type flip flop is connected to for exporting drive signal all the way per the CKB input terminals of level-one d type flip flop altogether
The input terminal of the output end of 19th reverser, CK input terminals and the 19th reverser per level-one d type flip flop is total
It is connected to second frequency unit.
In one of which embodiment, further include：With first frequency unit, second frequency unit and institute
The connection of the first output unit is stated, access DC power supply is configured to and generates the power on reset unit of the power-on reset signal.
In one of which embodiment, the power on reset unit includes：First PMOS tube, third capacitance, the 20th
Reverser, the 21st reverser and the 22nd reverser；
The source electrode of first PMOS tube connects the DC power supply, the grounded-grid of first PMOS tube, and described first
The drain electrode of PMOS tube and the first end of the third capacitance are connected to the input terminal of the 20th reverser, the third capacitance altogether
Second end ground connection, the output of the 20th reverser terminates the input terminal of the 21st reverser, the described 20th
The output of one reverser terminates the input terminal of the 22nd reverser, and the output end of the 22nd reverser is for defeated
Go out the power-on reset signal.
In one of which embodiment, further include：It is connect with first output unit, is configured to drive the roads L
Dynamic signal carries out second of logical operation and obtains the second output unit of multichannel Drive Optimization signal；
Wherein, second output unit includes multiple signal optimization modules, and each signal optimization module includes one
Logic gate and a reverser；The logic gate includes at least two input terminals, and the input terminal access of the logic gate is driven all the way
Dynamic signal, the output of the logic gate terminate the input terminal of the reverser, and the output end of the reverser is for exporting all the way
Drive Optimization signal.
Second aspect of the present invention provides a kind of lighting system, including control circuit as described above, and electric with the control
Road connects, the multiple LED light disorderly dodged under the driving of the roads L drive signal.
Above-mentioned in generating the control circuit of multichannel means of chaotic signals, the first oscillation to be generated by the first oscillator unit
Signal generates the second oscillator signal by the second oscillator unit, is carried out by first the first oscillator signal of frequency unit pair multiple
Multi-channel frequency division signal is obtained after frequency dividing, carries out obtaining triggering letter after repeatedly dividing by second the second oscillator signal of frequency unit pair
Number, and then the first output unit carries out first time logical operation according to power-on reset signal to trigger signal and multi-channel frequency division signal
After can be obtained the irregular drive signal of multichannel, due between per drive signal all the way frequency and the parameters such as phase have not
Systematicness and randomness, and then a variety of circuit functions can be realized by the drive signal, each industry neck can be universally applied to
In domain；The drive signal for the arbitrary way that the control circuit can generate simultaneously, compatibility is strong, and scalability is high, the scope of application
Extensively；Efficiently solving integrated circuit in traditional technology can not the drive signal of Conduce Disciplinarian difference, the circuit function realized
It is single, it can not blanket problem.
Description of the drawings
Fig. 1 is a kind of modular structure for generating the control circuit of multichannel means of chaotic signals provided in an embodiment of the present invention
Figure；
Fig. 2 is a kind of circuit structure diagram of first oscillator unit provided in an embodiment of the present invention；
Fig. 3 is a kind of circuit structure diagram of second oscillator unit provided in an embodiment of the present invention；
Fig. 4 is a kind of circuit structure diagram of first frequency unit provided in an embodiment of the present invention；
Fig. 5 is a kind of circuit structure diagram of second frequency unit provided in an embodiment of the present invention；
Fig. 6 is a kind of circuit structure diagram of first output unit provided in an embodiment of the present invention；
Fig. 7 is another module knot for generating the control circuit of multichannel means of chaotic signals provided in an embodiment of the present invention
Composition；
Fig. 8 is a kind of circuit structure diagram of power on reset unit provided in an embodiment of the present invention；
Fig. 9 is a kind of circuit structure diagram of second output unit provided in an embodiment of the present invention；
Figure 10 is a kind of function structure chart of lighting system provided in an embodiment of the present invention.
Specific implementation mode
Fig. 1 shows the module knot provided in an embodiment of the present invention for generating the control circuit 10 of multichannel means of chaotic signals
Structure, for convenience of description, illustrate only with the relevant part of the embodiment of the present invention, details are as follows：
As shown in Figure 1, control circuit 10 includes：First oscillator unit 101, the second oscillator unit 102, first frequency dividing
Unit 103, the second frequency unit 104 and the first output unit 105, wherein the first oscillator unit 101 generates the first oscillation
Signal H0, the second oscillator unit 102 generate the second oscillator signal L0；First generated by the first oscillator unit 101
Oscillator signal H0 has specific frequency and phase, the second oscillator signal L0 generated by the second oscillator unit 102
With specific frequency and phase, optionally, the parameter of the parameter of the first oscillator signal H0 and the second oscillator signal L0 can phases
With can not also be identical, this not be limited herein, wherein the parameter of the oscillator signal includes but not limited to：The week of signal
Phase, frequency, phase, amplitude；In the present embodiment, the parameter of the parameter of the first oscillator signal H0 and the second oscillator signal L0 not phase
Together, wherein the first oscillator signal H0 is high-frequency signal, period of the high-frequency signal is 10 microseconds between 900 microseconds；Second shakes
It is low frequency signal to swing signal L0, between period of the low frequency signal is 10 milliseconds to 900 milliseconds；Preferably, the first oscillator signal
The period of H0 and the period of the second oscillator signal L0, it is necessary to meet following condition：The period of first oscillator signal H0 and the second oscillation
The period of signal L0 is all prime number, and the period of the second oscillator signal L0 divided by the period of the first oscillator signal H0 are not belonging to 64
Within integer；When meeting the condition in the period in the period of the first oscillator signal H0 and the second oscillator signal L0, control electricity
It road 10 will the worse multi-channel drive signal D of Conduce Disciplinarian；All due to the first oscillator signal H0 and the second oscillator signal L0
With specific frequency of oscillation, control circuit 10 is repeatedly divided and is patrolled to the first oscillator signal H0 and the second oscillator signal L0
After volume operation, control circuit 10 can output multi-channel there is the drive signal of different frequency, to realize increasingly complex circuit work(
Energy.
First frequency unit 103 is connect with the first oscillator unit 101, and the first oscillator unit 101 believes the first oscillation
Number H0 is transmitted to the first frequency unit 103, and the first frequency unit 103 is according to POR couples of the first oscillator signal H0 of power-on reset signal
N times are carried out to divide to obtain the roads L fractional frequency signal Q；Wherein power-on reset signal POR has power on reset unit generation, by above replying by cable
Position signal POR can be driven each electric power component in the first frequency unit 103 and carry out reset operation；Specifically, whenever first
Frequency unit 103 carries out after once dividing the first oscillator signal H0, and the frequency of the first oscillator signal H0 will change, that
After carrying out n times frequency dividing to the first oscillator signal H0 by the first frequency unit 103, obtained every fractional frequency signal Q all the way is
There can be specific frequency, then the roads L fractional frequency signal Q there will be multi-frequency.
Second frequency unit 104 is connect with the second oscillator unit 102, and the second frequency unit 104 is believed according to electrification reset
Number POR couples the second oscillator signal L0 carries out M frequency dividing and obtains trigger signal L1；Wherein power-on reset signal POR is in the second frequency dividing
It can play the role of reset in unit 104；After M frequency dividing being carried out by the second frequency unit 104 to the second oscillator signal L0
The frequency of i.e. changeable second oscillator signal L0, and then the trigger signal L1 generated has specific frequency and phase；First is defeated
Go out unit 105 to connect with the first frequency unit 103 and the second frequency unit 104, the first output unit 105 is believed according to electrification reset
Number POR carries out first time logical operation to the roads trigger signal L1 and L fractional frequency signal Q and obtains the roads L drive signal D；Due to first
In output unit 105, the frequency of fractional frequency signal Q can be changed at random by carrying out logical operation to fractional frequency signal Q, therefore when the
After one output unit 105 carries out first time logical operation to the roads trigger signal L1 and L fractional frequency signal Q, per drive signal D's all the way
What frequency and phase were randomly generated, there is arbitrariness；Then pass through the frequency of 105 the generated roads L drive signal D of the first output unit
Rate and phase have the characteristics that irregular；Further, the output of the first output unit 105 terminates external electronic device, when
When the roads L drive signal D is transmitted to external electronic device by the first output unit 105, due to the frequency and phase of the roads L drive signal D
Position has the characteristics that arbitrariness and randomness, therefore it is various by multi-channel drive signal D to can be driven external electronic device realization
Complicated circuit function, to meet actual demand of the people in each industrial circle.
It should be noted that the N, the L and the M are greater than or equal to 2 positive integer, and L is less than
Or it is equal to N.
Through the embodiment of the present invention, the first frequency unit 103 according to POR couples of the first oscillator signal H0 of power-on reset signal into
Repeatedly frequency dividing obtains multi-channel frequency division signal Q to row, and the second frequency unit 104 is according to POR pairs of the second oscillator signal of power-on reset signal
L0 carries out repeatedly frequency dividing and obtains trigger signal L1, time divided to the first oscillator signal H0 due to the first frequency unit 103
Number can be adjusted according to actual needs, and then can obtain the fractional frequency signal Q with different frequency, the second frequency unit
The number that 104 couple of second oscillator signal L0 is divided can also be adjusted according to actual needs, therefore control circuit 10 has
There is high scalability；Simultaneously because being to Q the first logical operations of progress of multi-channel frequency division signal by the first output unit 105
Irregular multi-channel drive signal D can be obtained, since the phase and frequency of multi-channel drive signal D has randomness and arbitrariness,
And then electronic circuit can be driven by multi-channel drive signal D and realize various circuit functions, to meet the various need of technical staff
It asks；And the way of the drive signal D generated by control circuit 10 can be adjusted according to the concrete function of electronic circuit,
Compatibility is extremely strong, can be widely used in each industrial technical field；Efficiently solve in traditional technology integrated circuit without
The drive signal of method Conduce Disciplinarian difference, causes the circuit function that integrated circuit is realized single, can not generally be useful in each
The problems in industrial circle.
As an alternative embodiment, Fig. 2 shows the first oscillator units 101 provided in an embodiment of the present invention
Circuit structure, as shown in Fig. 2, the first oscillator unit 101 includes：First NAND gate NAND1, the second NAND gate NAND2, first
Resistance R1, the first capacitance C1, the first reverser INV1, the second reverser INV2, third reverser INV3, the 4th reverser
INV4, the 5th reverser INV5, the 6th reverser INV6 and the 7th reverser INV7；Wherein the first end of first resistor R1,
The input terminal of the first end of first capacitance C1 and the first reverser INV1 are connected to the input terminal of the second reverser INV2 altogether, and second
The first input end of the second NAND gate NAND2 of output termination of reverser INV2, the second input termination of the second NAND gate NAND2
The output end of first NAND gate NAND1, the output end of the first input end of the first NAND gate NAND1 and the second NAND gate NAND2
It is connected to the input terminal of the 4th reverser INV4 altogether, the output of the first reverser INV1 terminates the input terminal of third reverser INV3,
The second input terminal of the first NAND gate NAND1 of output termination of third reverser INV3, the output termination of the 4th reverser INV4
It is anti-that the second end of the input terminal of 5th reverser INV5, the output end of the 5th reverser INV5 and the first capacitance C2 are connected to the 6th altogether
To the input terminal of device INV6, the output end of the 6th reverser INV6 and the second end of first resistor R1 are connected to the 7th reverser altogether
The output of the input terminal of INV7, the 7th reverser INV7 terminates the first frequency unit 103；The wherein output of the 7th reverser INV7
End is the output end of the first frequency unit 103, for the first oscillator signal H0 to be transmitted to the first frequency unit 103.
As an alternative embodiment, Fig. 3 shows the second oscillator unit 102 provided in an embodiment of the present invention
Circuit structure, as shown in figure 3, the second oscillator unit 102 includes：Third NAND gate NAND3, the 4th NAND gate NAND4, second
Resistance R2, the second capacitance C2, the 8th reverser INV8, the 9th reverser INV9, the tenth reverser INV10, the 11st reverser
INV11, the 12nd reverser INV12, the 13rd reverser INV13, the 14th reverser INV14 and the 15th reverser
INV15；Wherein, the input terminal of the first end of second resistance R2, the first end of the second capacitance C2 and the 8th reverser INV8 is total
It is connected to the input terminal of the 9th reverser INV9, the first input of the 4th NAND gate NAND4 of output termination of the 9th reverser INV9
End, the output end of the second input termination third NAND gate NAND3 of the 4th NAND gate NAND4, the first of third NAND gate NAND3
The output end of input terminal and the 4th NAND gate NAND4 are connected to the input terminal of the 11st reverser INV11, the 8th reverser INV8 altogether
The tenth reverser INV10 of output termination input terminal, the output termination third NAND gate NAND3's of the tenth reverser INV10
Second input terminal, the input terminal of the 12nd reverser INV12 of output termination of the 11st reverser INV11, the 12nd reverser
The second end of the output end of INV12 and the second capacitance C2 are connected to the input terminal of the 13rd reverser INV13, the 13rd reverser altogether
The output end of INV13 and the second end of second resistance R2 are connected to the input terminal of the 14th reverser INV14, the 14th reverser altogether
The input terminal of the 15th reverser INV15 of output termination of INV14, the second frequency dividing of output termination of the 15th reverser INV15
Unit 104；Wherein the output end of the 15th reverser INV15 is the output end of the second oscillator unit 102, for second to shake
It swings signal L0 and is transmitted to the second frequency unit 104.
As an alternative embodiment, Fig. 4 shows the electricity of the first frequency unit 103 provided in an embodiment of the present invention
Line structure, as shown in figure 4, the first frequency unit 103 includes：16th reverser INV16 and the first T flip-flop arrays 1031；
Wherein, the first T flip-flop arrays 1031 include N number of cascade T triggers, in the first T flip-flop arrays 1031, per level-one T
The reset signal input terminal R of trigger accesses power-on reset signal POR, by power-on reset signal POR can be realized for
Each T trigger carries out reset operation in first frequency unit 1031；Q output per level-one T triggers divides for exporting
Frequency signal Q, the Q output of i-stage T triggers ZTRi connect the CKB input terminals of i+1 grade T triggers ZTRi+1, i-stage T triggerings
The CK input terminals of the QB output termination i+1 grade T triggers ZTRi+1 of device ZTRi；First in first T flip-flop arrays 1031
The output end of the 16th reverser INV16 of CKB input terminations of grade T triggers ZTR1, the in the first T flip-flop arrays 1031
The CK input terminals of level-one T triggers ZTR1 and the input terminal of the 16th reverser INV16 are connected to the first oscillator unit 101 altogether,
For accessing the first oscillator signal H0.
It should be noted that the i is 1 to the arbitrary positive integer between N-1.
It is shown in Fig. 4 go out the first frequency unit 103 circuit structure in, since the first T flip-flop arrays 1031 include
Multiple T triggers, and T triggers are used as electronic component common in the art, when the first T flip-flop arrays 1031 connect
When entering the first oscillator signal H0, is overturn using the signal of multiple T triggers and keep function, the first T flip-flop arrays 1031 right
First oscillator signal H0 carries out that the roads L fractional frequency signal Q1, Q2 ... QL-1, QL can be obtained after repeatedly dividing；Specifically, in conjunction in Fig. 4
The circuit structure of first frequency unit 103 is equivalent to each when the first oscillator signal H0 passes sequentially through every level-one T triggers
Grade T triggers carry out a divide operation for the first oscillator signal H0；It is each and then in the first T flip-flop arrays 1031
The fractional frequency signal Q that the Q output of grade T triggers is exported has different frequency and phase；Therefore, optionally from the first T
The roads point signal composition L chosen L T trigger in flip-flop array 1031, and the Q output of this L T trigger is exported
Frequency signal Q, then this road L fractional frequency signal Q has a variety of frequency and phase；It being preferably carried out mode as one kind, in order to
The frequency and phase for enough making the roads L fractional frequency signal Q have randomness and out of order property, preferential to select in the first T flip-flop arrays 1031
Take signal composition L road fractional frequency signal Q1, Q2 ... QL-1 that the Q output of N-L+1 grades to N grades of T triggers exported,
QL, due to have passed through multiple frequency dividing, the regularity of the frequency and phase of fractional frequency signal Q is worse at this time, and then 10 energy of control circuit
Enough driving electronic circuit realizes the circuit function of Various Complex.
It should be noted that in the circuit structure of the first frequency unit 103, due to passing through the first T flip-flop arrays
1031 couple of first oscillator signal H0 carries out having obtained the roads L fractional frequency signal Q1, Q2 ... QL-1, QL after repeatedly dividing, then per all the way
The fractional frequency signal period all can be the integral multiple in the first oscillator signal H0 periods, and also can not phase per the period of fractional frequency signal all the way
Together.
As an alternative embodiment, Fig. 5 shows the electricity of the second frequency unit 104 provided in an embodiment of the present invention
Line structure, as shown in figure 5, the second frequency unit 104 includes：17th reverser INV17, eighteen incompatibilities are to device INV18 and
Two T flip-flop arrays 1041；Wherein the 2nd T flip-flop arrays 1041 include M cascade T triggers ZTR1, ZTR2 ... ZTRM-
1, ZTRM, in the 2nd T flip-flop arrays 1041, the reset signal input terminal R per level-one T triggers accesses power-on reset signal
POR carries out reset operation by the T triggers in POR pairs of the 2nd T flip-flop array 1041 of power-on reset signal；J-th stage T is touched
The Q output of hair device ZTRj connects the CKB input terminals of+1 grade of T triggers ZTRj+1 of jth, the QB output ends of j-th stage T triggers ZTRj
Connect the CK input terminals of+1 grade of T triggers ZTRj+1 of jth；The input terminal and the 2nd T flip-flop arrays of 17th reverser INV17
The CK input terminals of first order T triggers ZTR1 are connected to the second oscillator unit 102 altogether in 1041, for accessing the second oscillator signal
L0；Input of the QB output termination eighteen incompatibilities of M grades of T triggers ZTRM to device INV18 in 2nd T flip-flop arrays 1041
End, eighteen incompatibilities to the output of device INV18 terminate the first output unit 105, eighteen incompatibilities to the output end of device INV18 be second
The output end of frequency unit 104, for trigger signal L1 to be transmitted to the first output unit 105.
It should be noted that the j is 1 to the arbitrary positive integer between M-1.
According to the circuit structure of above-mentioned second frequency unit 104, the 2nd T flip-flop arrays 1041 include that M cascade T are touched
Device is sent out, since T triggers have the function of keeping and overturn to signal, when the second oscillation of the 2nd T flip-flop arrays 1041 access
When signal L0, then multiple the second oscillator signal of T triggers pair L0 have carried out multiple frequency dividing, you can change the second oscillator signal L0's
Frequency and phase, and then the 2nd T flip-flop arrays 1041 produce the trigger signal L1 with different frequency and phase；Specifically
, in practical applications, those skilled in the art can select the T triggers of different number, example in the second frequency unit 104
Property, M can be 10,11 or 12 etc., if the quantity of T triggers is more included in the 2nd T flip-flop arrays 1041, then
2nd T flip-flop arrays 1041 also will be more to the second oscillator signal L0 numbers divided, so as to by changing the
The quantity of T triggers in two T flip-flop arrays 1041, and then the trigger signal L1 of different frequency can be obtained, it can with high
Autgmentability.
As an alternative embodiment, Fig. 6 shows the electricity of the first output unit 105 provided in an embodiment of the present invention
Line structure, as shown in fig. 6, the first output unit 105 includes：19th reverser INV19 and d type flip flop array 1051；Wherein,
D type flip flop array 1051 includes L cascade d type flip flop ZDR1, ZDR2 ... ZDRL-1, ZDRL, in d type flip flop array 1051
In, the reset signal input terminal R per level-one d type flip flop accesses power-on reset signal POR, is touched to D by power-on reset signal POR
Every level-one d type flip flop in hair device array 1051 carries out reset operation, and the D input terminals access per level-one d type flip flop divides all the way
Signal, in conjunction with above-mentioned first frequency unit 103 circuit structure it is found that every level-one d type flip flop herein D input terminals respectively with
The Q output connection of T triggers in first T flip-flop arrays 1031；Q output per level-one d type flip flop is for exporting all the way
Drive signal can drive electronic circuit to realize corresponding function by the drive signal；Per the CKB input terminals of level-one d type flip flop
It is connected to the output end of the 19th reverser INV19 altogether, the CK input terminals and the 19th reverser INV19 per level-one d type flip flop
Input terminal is connected to the second frequency unit 104 altogether, for accessing trigger signal L1.
Specifically, d type flip flop has the processing function of digital signal as common electronic component in traditional technology；
In d type flip flop array 1051, per level-one d type flip flop, to trigger signal L1 and all the way, fractional frequency signal progress logical operation is defeated in turn
Go out drive signal all the way, as noted previously, as the phase and frequency for the roads the L fractional frequency signal Q that the first frequency unit 103 is generated is all
With randomness and arbitrariness, therefore, d type flip flop array 1051 carries out the first logic to the roads trigger signal L1 and L fractional frequency signal Q
After operation, the frequency and phase of the obtained roads L drive signal D also have erratic behavior, and are believed triggering by T triggers
The logical operation that number L1 and fractional frequency signal Q are carried out will enhance the randomness and arbitrariness of multi-channel drive signal D；Due to multichannel
The frequency and phase of drive signal D is extremely irregular, when multi-channel drive signal D is transmitted to the external world by the first output unit 105
Electronic circuit in, electronic circuit can be made to realize more complicated circuit function by multi-channel drive signal D.
The operation principle of control circuit 10 has in conjunction with Fig. 1-6 by one in embodiment in order to better illustrate the present invention
The application scenarios of body are come to illustrate the work step of control circuit 10, this application scene be to apply above-mentioned control circuit 10 multiple
LED light is realized in the technique effect disorderly dodged, specific as follows：
In the conventional technology, the light source with different brightness and frequency is sent out by multiple LED light, as disorderly dodges effect
Fruit can bring good visual sense of beauty due to by LED light disorderly dodge, and by LED light disorderly dodge wide
It is applied to generally in the every field such as Curtain Wall Design, the billboard publicity of skyscraper；In this application scene, if technical staff
4 LED light are needed to realize the effect disorderly dodged, it is in this application scene, the parameter setting of control circuit 10 is as follows：
N=7；L=4；M=14；
It is at this time high-frequency signal, the first oscillator signal by the first oscillator signal H0 that the first oscillator unit 101 generates
The period of H0 is 200 microseconds；It is low frequency signal by the second oscillator signal L0 that the second oscillator unit 102 generates, second shakes
The period for swinging signal L0 is 200 milliseconds；First frequency unit 103 obtains 4 tunnels to first oscillator signal H0 7 frequency dividings of progress and does not advise
Fractional frequency signal Q1, Q2, Q3 and Q4 then, the second frequency unit 104 carry out 14 frequency dividings to the second oscillator signal L0 and are touched
Signalling L1, due to being random, and trigger signal L1 by the phase of trigger signal L1 obtained by the second frequency unit 104
Phase there are rising edges and failing edge；According to the control between the input signal and output signal of d type flip flop in traditional technology
Logic, only when the signal that the CK input terminals of d type flip flop are accessed is rising edge, the signal phase of the Q output of d type flip flop
It can be just consistent with the signal phase of the D input terminals of d type flip flop, then the letter accessed whenever the CK input terminals of d type flip flop
When number there is rising edge, the signal phase of the Q output of d type flip flop will be kept with the signal phase of the D input terminals of d type flip flop
Unanimously, thus, the signal period of the Q output output of d type flip flop can be the CK input terminals institute input signal week of d type flip flop
The integral multiple of phase.
The specific circuit structure in conjunction with the first output unit 105 in the embodiment of the present invention, due in d type flip flop array 1051
In, fractional frequency signal, the CK input terminals per level-one d type flip flop access trigger signal to the D input terminals access per level-one d type flip flop all the way
L1, the reverse signal of the CKB input terminals access trigger signal L1 per level-one d type flip flop, then the Q outputs per level-one d type flip flop
The phase bit timing of end institute output drive signal is determined by the phase bit timing of trigger signal L1 and the phase bit timing of fractional frequency signal；
If the frequency of 4 road fractional frequency signal Q1, Q2, Q3 and Q4 and the frequency of trigger signal L1 have the characteristics that regularity is very poor, then
The frequency and phase for 4 road drive signal D1, D2, D3 and D4 that first output unit 105 is exported also have regularity very poor
The characteristics of；Specifically, when if trigger signal L1 is rising edge, 4 road fractional frequency signal Q1, Q2 that the first frequency unit 103 is generated,
Q3 and Q4 is high level, then in d type flip flop array 1051, the signal accessed per the D input terminals of level-one d type flip flop is
High level, the signal accessed per the CK input terminals of level-one d type flip flop is rising edge, per the CKB input terminals institute of level-one d type flip flop
The signal of access is failing edge, according to the control logic between the input signal and output signal of d type flip flop, at this time per level-one D
The drive signal that the Q output of trigger is exported is high level, and is driven by 4 tunnels that the first output unit 105 is exported
Dynamic signal D1, D2, D3 and D4 can maintain always high level, when there is next rising edge in trigger signal L1, driving letter
Number phase can just be changed according to the phase of fractional frequency signal；Therefore when rising edge occurs in trigger signal L1, d type flip flop
Q output output the phase of drive signal and the phase of fractional frequency signal be consistent, and the phase of drive signal can one
When straight maintenance next rising edge occurs to trigger signal L1, repeatedly, and then the first output unit 105 is to trigger signal L1
4 road drive signal D1, D2, D3 and D4 are obtained after carrying out logical operation with 4 road fractional frequency signal Q1, Q2, Q3 and Q4.
Therefore according to the operation principle of above-mentioned first output unit 105, drive signal is generated by the first output unit 105
The phase cycling of D is determined according to the phase cycling of trigger signal L1 and the phase cycling of fractional frequency signal Q, if trigger signal L1
Phase and fractional frequency signal Q phase all be irregular distribution or the first oscillator signal H0 phase and the second oscillator signal
The phase of L0 is all irregular distribution, then the phase of drive signal D also has erratic behavior；Specifically, working as trigger signal L1
Phase when there is rising edge, the level state of fractional frequency signal Q is uncertain, then the Q output institute by d type flip flop is defeated
The level state for going out drive signal D is also uncertain, i.e., every drive signal D's all the way is to be likely to be at high level state also may be used
It can be in low level state, to which the phase and frequency of drive signal D is all extremely irregular, there is randomness and arbitrariness；
Further, if the period of the first oscillator signal H0 and the period of the second oscillator signal L0 are all prime numbers, trigger signal L1's
Phase and the phase of fractional frequency signal Q have higher randomness, and the matching degree of the two can be lower, to which control circuit 10 can give birth to
At the worse multi-channel drive signal D of regularity, and then drives multiple LED light to realize and more preferably disorderly dodge effect.
As a preferred embodiment, circuit structure in, in the first frequency unit 103 and the first output unit
Increase multiple logic gates, such as XOR gate, same or door and door, that is, NOT gate between 105, the roads L are divided by multiple logic gates and are believed
Number Q carries out logical operation, then the D of d type flip flop in the signal transmission after logical operation to the first output unit 105 is inputted
End, so that the multi-channel drive signal D that d type flip flop array 1051 is exported has the out of order property of higher, regularity worse.
In conjunction with the application scenarios of aforementioned present invention, first oscillator signal H0 is carried out by the first frequency unit 103 multiple
Multi-channel frequency division signal Q is obtained after frequency dividing, and second oscillator signal L0 obtain after repeatedly dividing by the second frequency unit 104
Trigger signal L1, since the phase of fractional frequency signal Q, the phase of frequency and trigger signal L1, period are all uncertain, random
, therefore obtain multichannel when the first output unit 105 carries out first time logical operation to trigger signal L1 and multi-channel frequency division signal Q
The phase of drive signal D, drive signal D are also uncertain, have randomness and arbitrariness, and then give birth to by control circuit 10
At regular very poor multi-channel drive signal D, by multi-channel drive signal D can be driven multiple LED light carry out it is irregular
It disorderly dodges, good user experience is brought to audience；And according to the circuit composed structure of control circuit 10,10 institute of control circuit
Generating the way of drive signal can be adjusted according to the quantity of LED light, for example, control circuit 10 produces 4 tunnels, 5 tunnels or 6
The drive signals such as road, to realize that the LED light of different number carries out random sudden strain of a muscle, therefore the compatibility of the control circuit 10 is extremely strong, can expand
Malleability is high, has the extensive scope of application；To solve the generated multi-way LED lamp drive signal of integrated circuit in traditional technology
The unrest realized of too strong, the multiple LED light of regularity dodge ineffective, and then cause the visual experience sense of user is bad to ask
Topic.
As a preferred embodiment, Fig. 7 show it is provided in an embodiment of the present invention for generate multichannel irregular
Another circuit structure of the control circuit 10 of signal, compared to the modular structure of control circuit 10 shown in figure 1, in Fig. 7
Shown control circuit 10 further comprises power on reset unit 701 and the second output unit 702, specifically：
Power on reset unit 701 and the first frequency unit 103, the second frequency unit 102 and the first output unit 105 connect
It connects, power on reset unit 701 accesses DC power supply VDD and generates power-on reset signal POR, and power on reset unit 701 will
Power-on reset signal POR is transmitted to other circuit units in control circuit 10, and power-on reset signal POR is in control circuit 10
The effect resetted can be achieved；Second output unit 702 is connect with the first output unit 105, and the first output unit 105 drives the roads L
Dynamic signal D is transmitted to the second output unit 702, and the second output unit 702 carries out second of logical operation to the roads L drive signal D
Obtain multichannel Drive Optimization signal DL；As noted previously, as having by the roads the L drive signal that the first output unit 105 generates
Very poor regularity, after the second output unit 702 carries out second of logical operation to the roads L drive signal, obtained multichannel
The phase and frequency of Drive Optimization signal DL has higher randomness and arbitrariness, is equivalent to control circuit 10 to trigger signal
The roads L1 and L fractional frequency signal Q has carried out logical operation twice, the multichannel Drive Optimization signal DL tools that control circuit 10 is exported at this time
There is higher erratic behavior；Therefore, it is shown in Fig. 7 go out control circuit 10 modular structure in, the first output unit 105 passes through
When second output unit 702 connects external electronic device, multichannel Drive Optimization signal DL was transmitted to by the second output unit 702 at that time
When external electronic device, external electronic device can realize better random sudden strain of a muscle effect according to multichannel Drive Optimization signal DL, carry
The high practicability of the control circuit 10.
As an alternative embodiment, Fig. 8 shows the electricity of power on reset unit 701 provided in an embodiment of the present invention
Line structure, as shown in figure 8, power on reset unit 701 includes：First PMOS tube PMOS1, third capacitance C3, the 20th reverser
INV20, the 21st reverser INV21 and the 22nd reverser INV22；Wherein, the source electrode of the first PMOS tube PMOS1 connects directly
The drain electrode of the grounded-grid GND, the first PMOS tube PMOS1 of galvanic electricity source VDD, the first PMOS tube PMOS1 and the of third capacitance C3
One end is connected to the input terminal of the 20th reverser C20 altogether, and the second end of third capacitance C3 is grounded GND, the 20th reverser INV20
The 21st reverser INV21 of output termination input terminal, the output termination the 22nd of the 21st reverser INV21 is anti-
To the input terminal of device INV22, the output end of the 22nd reverser INV22 is the output end of power on reset unit 701, for defeated
Go out power-on reset signal POR.
According to the circuit structure of power on reset unit 701, when power on reset unit 701 is rigid obtains electric, the first PMOS tube
PMOS1 is connected, and DC power supply VDD charges to third capacitance C3 by the first PMOS tube PMOS1, since the C3 chargings of third capacitance exist
It will produce the effect of delay in charging process；In third capacitance C3 charging processes, exported by power on reset unit 701
Power-on reset signal POR can maintain 1 microsecond to the high level state of 10 microseconds；After third capacitance C3 charging completes, power on
Reset signal POR becomes low level state；And then power-on reset signal POR is transmitted to control circuit by power on reset unit 701
Other units (including the first frequency unit 103, the second frequency unit 102 and first output unit 105) in 10, to realize
Other units in control circuit 10 carry out reset operation.
It is understood that in embodiments of the present invention, power-on reset signal POR can play multiple in control circuit 10
The effect of position, T triggers and d type flip flop carry out reset operation according to power-on reset signal in control circuit 10, in practical application
Other function signals can also be used to realize the effect of reset in field, control circuit 10, it is only necessary to used other functions
Signal realizes identical reset function with power-on reset signal POR in the present embodiment, to which control circuit 10 can also be realized
Corresponding signal processing function.
As an alternative embodiment, the second output unit 702 includes multiple signal optimization modules, each signal is excellent
It includes a logic gate and a reverser to change module；Logic gate includes at least two input terminals, the input terminal access one of logic gate
The output end of road drive signal, logic gate connects the input terminal of reverser, and the output end of reverser is for exporting Drive Optimization all the way
Signal；Therefore in the second output unit 702, after carrying out logical operation to multi-channel drive signal D by multiple logic gates, into one
Step enhances the frequency of drive signal D and the randomness of phase and arbitrariness, the second output unit 702 can output rule more
The multichannel Drive Optimization signal of difference, and then electronic circuit is driven to realize more preferably circuit function.
Optionally, in the optimization module of the second output unit 702, logic gate is：With or door, XOR gate, NAND gate or
NOT gate or door or with door.
Illustratively, in order to better illustrate 702 operation principle of the second output unit, Fig. 9 shows the embodiment of the present invention
The circuit structure of the second output unit 702 provided, in conjunction with the circuit structure of the first output unit 105 illustrated in fig. 6；Such as figure
Shown in 9, the second output unit 702 contains 6 signal optimization modules 7021, and in each signal optimization module 7021
Logic gate can be with door AND or door OR and XOR gate XOR etc., an input terminal random access wherein one of each logic gate
Road drive signal D, so by 7021 logical operation of signal optimization module generate Drive Optimization signal DL have greatly with
Machine and contingency, and then the multichannel Drive Optimization signal DL by being exported after 702 second of the logical operation of the second output unit
Phase and frequency be extremely irregular, correspondingly, electronic circuit realizes more according to multichannel Drive Optimization signal DL at this time
Complicated circuit effect.
Through the embodiment of the present invention, control circuit 10 includes the first output unit 105 and the second output unit 702, and one
Aspect carries out first time logical operation to trigger signal L1 and multi-channel frequency division signal Q by the first output unit 105 and obtains multichannel
Drive signal D, since the phase and frequency of multichannel driving has randomness and arbitrariness；On the other hand, single by the second output
702 couples of multi-channel drive signal D of member obtain the worse multichannel Drive Optimization signal DL of regularity after carrying out second of logical operation, this
When be equivalent to control circuit 10 logical operation twice successively carried out to trigger signal L1 and multi-channel frequency division signal Q, avoid the
The multi-channel drive signal of one output unit 105 output still may have the problem of relatively strong regularity；Believed by being driven to multichannel
Number D, which carries out second of logical operation, will be significantly enhanced the randomness and scrambling of multichannel Drive Optimization signal DL, in turn
Can the irregular Drive Optimization signal DL of general warranty multichannel electronic circuit can be driven to realize more preferably circuit effect；And
Since the signal optimization module in the second output unit 702 can be adjusted according to actual needs, then the second output unit 702
The Drive Optimization signal DL of exportable arbitrary way has higher compatibility, can be widely used in different industrial circles；
To efficiently solve the regularity electricity that is stronger, and its being realized for the drive signal that integrated circuit in traditional technology is generated
Road has a single function, can not blanket problem.
As an alternative embodiment, Figure 10 shows the module of lighting system 100 provided in an embodiment of the present invention
Structure, wherein lighting system 100 includes control circuit 10 as described above and multiple LED light 1001；Multiple LED light 1001 are divided
It is not connect with control circuit 10, multi-channel drive signal D is transmitted in multiple LED light by control circuit 10, and then multiple LED light exist
Random sudden strain of a muscle is carried out under the driving of multi-channel drive signal D；According to discussed above, by the drive signal generated by control circuit 10
D have the characteristics that it is extremely irregular, multiple LED light according to multi-channel drive signal D can realize it is splendid it is random dodge effect, to enhance
User experience；Therefore technical staff can apply lighting system 100 in commercial advertising board, the curtain wall of skyscraper and city scape
The fields such as lamp are seen, there is extremely strong actual application value.
It should be noted that herein only apply control circuit 10 in LED light realizes the technical field disorderly dodged,
Since this is only a kind of embodiment, do not constitute for the control circuit 10 for generating multichannel means of chaotic signals in the present invention
Technology limiting；It is understood that in practical applications, related technical personnel can apply the control circuit 10 in robot
Mobile design, unmanned plane flight path control etc. other technical fields, as long as its essence inventive concept and circuit structure
Consistent with control circuit in the present invention 10, this still falls within protection scope of the present invention.Meanwhile herein, such as it is multiple and
The quantity of multichannel etc referred both to more than 1；Such as first and second etc relational terms be used merely to by an entity with it is another
One entity distinguishes, and without necessarily requiring or implying between these entities, there are any this actual relationships or suitable
Sequence.And the terms "include", "comprise" or any other variant are intended to non-exclusive inclusion, so that including one
The intrinsic element of the product or structure of list of elements.In addition, herein, " being more than ", " being less than ", " being more than " etc. are interpreted as
It does not include this number；" more than ", " following ", " within " etc. be interpreted as including this number.
Claims (10)
1. a kind of control circuit for generating multichannel means of chaotic signals, which is characterized in that including：
It is configured to generate the first oscillator unit of the first oscillator signal；
It is configured to generate the second oscillator unit of the second oscillator signal；
It is connect with first oscillator unit, is configured to carry out n times to first oscillator signal according to power-on reset signal
Frequency dividing obtains the first frequency unit of the roads L fractional frequency signal；
It is connect with second oscillator unit, is configured to carry out second oscillator signal according to the power-on reset signal
M times frequency dividing obtains the second frequency unit of trigger signal；And
It connect, is configured to according to the power-on reset signal to described with first frequency unit and second frequency unit
Trigger signal and the roads L fractional frequency signal carry out first time logical operation and obtain the first output unit of the roads L drive signal；
Wherein, the N, the L and the M are greater than or equal to 2 positive integer, and L is less than or equal to N.
2. circuit according to claim 1, which is characterized in that first oscillator unit includes：First NAND gate,
Two NAND gates, first resistor, the first capacitance, the first reverser, the second reverser, third reverser, the 4th reverser, the 5th are instead
To device, the 6th reverser and the 7th reverser；
Wherein, the input terminal of the first end of the first resistor, the first end of first capacitance and first reverser
It is connected to the input terminal of second reverser altogether, the output of second reverser terminates the first input of second NAND gate
End, the second input of second NAND gate terminate the output end of first NAND gate, and the first of first NAND gate is defeated
Enter the input terminal for holding the output end with second NAND gate to be connected to the 4th reverser altogether, the output of first reverser
The input terminal of the third reverser is terminated, the output of the third reverser terminates the second input of first NAND gate
End, the output of the 4th reverser terminate the input terminal of the 5th reverser, the output end of the 5th reverser and institute
The second end for stating the first capacitance is connected to the input terminal of the 6th reverser, the output end of the 6th reverser and described altogether
The second end of one resistance is connected to the input terminal of the 7th reverser, described first point of the output termination of the 7th reverser altogether
Frequency unit.
3. control circuit according to claim 1, which is characterized in that second oscillator unit includes：Third with it is non-
Door, the 4th NAND gate, second resistance, the second capacitance, the 8th reverser, the 9th reverser, the tenth reverser, the 11st are reversely
Device, the 12nd reverser, the 13rd reverser, the 14th reverser and the 15th reverser；
Wherein, the input terminal of the first end of the second resistance, the first end of second capacitance and the 8th reverser
It is connected to the input terminal of the 9th reverser altogether, the output of the 9th reverser terminates the first input of the 4th NAND gate
End, the second input of the 4th NAND gate terminate the output end of the third NAND gate, and the first of the third NAND gate is defeated
The output end for entering end and the 4th NAND gate is connected to the input terminal of the 11st reverser altogether, the 8th reverser it is defeated
Go out the input terminal for terminating the tenth reverser, the output of the tenth reverser terminates the second input of the third NAND gate
End, the output of the 11st reverser terminate the input terminal of the 12nd reverser, the output of the 12nd reverser
The second end of end and second capacitance is connected to the input terminal of the 13rd reverser, the output of the 13rd reverser altogether
The second end of end and the second resistance is connected to the input terminal of the 14th reverser, the output of the 14th reverser altogether
The input terminal of the 15th reverser is terminated, the output of the 15th reverser terminates second frequency unit.
4. control circuit according to claim 1, which is characterized in that first frequency unit includes：16th is reversed
Device and the first T flip-flop arrays；Wherein, the first T flip-flop arrays include N number of cascade T triggers, in the first T
In flip-flop array, the reset signal input terminal per level-one T triggers is touched for accessing the power-on reset signal per level-one T
For the Q output of hair device for exporting the fractional frequency signal, the Q output of i-stage T triggers meets the CKB of i+1 grade T triggers
Input terminal, the CK input terminals of the QB output termination i+1 grade T triggers of i-stage T triggers；
The CKB inputs of first order T triggers in the first T flip-flop arrays terminate the output of the 16th reverser
It holds, the CK input terminals of the first order T triggers in the first T flip-flop arrays and the input terminal of the 16th reverser are total
It is connected to first oscillator unit；The wherein described i is 1 to the arbitrary positive integer between N-1.
5. control circuit according to claim 1, which is characterized in that second frequency unit includes：17th is reversed
Device, eighteen incompatibilities are to device and the 2nd T flip-flop arrays；Wherein, the 2nd T flip-flop arrays include M cascade T triggerings
Device, in the 2nd T flip-flop arrays, the reset signal input terminal per level-one T triggers is for accessing the electrification reset
Signal, the Q output of j-th stage T triggers connect the CKB input terminals of+1 grade of T trigger of jth, the QB output ends of j-th stage T triggers
Connect the CK input terminals of+1 grade of T trigger of jth；
The CK input terminals of first order T triggers are total in the input terminal of 17th reverser and the 2nd T flip-flop arrays
It is connected to second oscillator unit, the QB outputs termination the described tenth of M grades of T triggers in the 2nd T flip-flop arrays
The input terminal of eight reversers, the eighteen incompatibilities terminate first output unit to the output of device；Wherein, the j is 1 to M-
Arbitrary positive integer between 1.
6. control circuit according to claim 1, which is characterized in that first output unit includes：19th is reversed
Device and d type flip flop array；Wherein, the d type flip flop array includes L cascade d type flip flops, in the d type flip flop array,
Reset signal input terminal per level-one d type flip flop is for accessing the power-on reset signal, per the D input terminals of level-one d type flip flop
Fractional frequency signal, the Q output per level-one d type flip flop are used to export drive signal all the way all the way for access, every level-one d type flip flop
CKB input terminals are connected to the output end of the 19th reverser altogether, and the CK input terminals and the described 19th per level-one d type flip flop are instead
It is connected to second frequency unit altogether to the input terminal of device.
7. control circuit according to claim 1, which is characterized in that further include：With first frequency unit, described
Two divided-frequency unit and first output unit connection, are configured to access DC power supply and generate the power-on reset signal
Power on reset unit.
8. control circuit according to claim 7, which is characterized in that the power on reset unit includes：First PMOS tube,
Third capacitance, the 20th reverser, the 21st reverser and the 22nd reverser；
The source electrode of first PMOS tube meets the DC power supply, the grounded-grid of first PMOS tube, the first PMOS
The drain electrode of pipe and the first end of the third capacitance are connected to the input terminal of the 20th reverser altogether, and the of the third capacitance
Two ends are grounded, and the output of the 20th reverser terminates the input terminal of the 21st reverser, and the described 21st is anti-
The input terminal of the 22nd reverser is terminated to the output of device, the output end of the 22nd reverser is for exporting institute
State power-on reset signal.
9. according to claim 1-8 any one of them control circuits, which is characterized in that further include：It is single with first output
Member connection, is configured to carry out second of logical operation to the roads L drive signal to obtain the second defeated of multichannel Drive Optimization signal
Go out unit；
Wherein, second output unit includes multiple signal optimization modules, and each signal optimization module includes a logic
Door and a reverser；The logic gate includes at least two input terminals, and driving is believed all the way for the input terminal access of the logic gate
Number, the output of the logic gate terminates the input terminal of the reverser, and the output end of the reverser drives all the way for exporting
Optimize signal.
10. a kind of lighting system, is characterized in that, including such as claim 1-9 any one of them control circuits, and with the control
Circuit connection processed, the multiple LED light disorderly dodged under the driving of the roads L drive signal.
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| CN201810668433.2A CN108777899B (en) | 2018-06-26 | 2018-06-26 | Control circuit for generating multipath irregular signals and lighting system |
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| CN201810668433.2A CN108777899B (en) | 2018-06-26 | 2018-06-26 | Control circuit for generating multipath irregular signals and lighting system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
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| CN208386968U (en) * | 2018-06-26 | 2019-01-15 | 宗仁科技(平潭)有限公司 | For generating the control circuit and lighting system of multichannel means of chaotic signals |
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| JPH05191833A (en) * | 1992-01-13 | 1993-07-30 | Toshiba Corp | Pulse signal generation circuit |
| CN1204185A (en) * | 1997-06-26 | 1999-01-06 | 深圳市华为技术有限公司 | Equipment for controlling clock signal switching phase transient and method |
| KR20010016497A (en) * | 2000-12-15 | 2001-03-05 | 송동호 | Circuit for controlling pattern display in a lighting wheel |
| US20090189700A1 (en) * | 2008-01-30 | 2009-07-30 | Nec Electronics Corporation | Frequency synthesizer |
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| CN208386968U (en) * | 2018-06-26 | 2019-01-15 | 宗仁科技(平潭)有限公司 | For generating the control circuit and lighting system of multichannel means of chaotic signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
| CN116566370B (en) * | 2023-07-11 | 2024-01-30 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
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| CN108777899B (en) | 2024-01-02 |
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