CN105957470B - Shift register cell, gate driving circuit and its driving method, display device - Google Patents
Shift register cell, gate driving circuit and its driving method, display device Download PDFInfo
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- CN105957470B CN105957470B CN201610534144.4A CN201610534144A CN105957470B CN 105957470 B CN105957470 B CN 105957470B CN 201610534144 A CN201610534144 A CN 201610534144A CN 105957470 B CN105957470 B CN 105957470B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of shift register cell, gate driving circuit and its driving methods, display device；In the shift register cell, there are two output modules for setting, export corresponding scanning pulse by different scanning pulse output ends；Accordingly even when setting one of scanning pulse to the scanning pulse with top rake, it is nonetheless possible to use another scanning pulse drives next stage shift register cell；The driving capability to next stage shift register cell will not be reduced.In addition, two input modules are arranged in the present invention；Enabling to the process of two output module output scanning pulses will not influence each other, and can further avoid the influence to the scanning pulse of one of top rake to another scanning pulse, and then avoid influencing the driving capability to next stage shift register cell.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift register cells, gate driving circuit and its drive
Dynamic method, display device.
Background technique
GOA (Gate Driver On Array, gate driving circuit are integrated into array substrate) is to realize display device
A kind of important means of narrow side.In general, the gate driving circuit being integrated into array substrate is by multistage shift register
Unit composition, every level-one shift register cell is successively under the driving of the scanning pulse of upper level shift register cell output
It exports on scanning pulse to corresponding grid line, so that each thin film transistor (TFT) conducting that each grid line is connected, to realize
To the driving process of corresponding pixel unit；And the scanning pulse that this grade of shift register cell is exported can be also output to down
The driving to next stage shift register cell is realized in level-one shift register cell.
On the other hand, TFT gate is down to Vgl from Vgh at the end of charging process, in the influence of gate-source parasitic capacitance
Under, the voltage of pixel electrode declines therewith, the amplitude of decline and the size of gate-source electrode capacitance and Vgh (gate high-voltage) and Vgl
Pressure difference between (gate high-voltage) is directly proportional.This pressure drop phenomena can impact the display effect of display device, in order to
The display effect for promoting display device is generally required and is formed to the end progress top rake for the scanning pulse being applied on each grid line
Multi-stage gate voltage.As described above, since the driving that scanning pulse itself will also be used as next stage shift register cell is believed
Number, therefore such top rake can reduce the scanning pulse to the driving capability of next stage shift register cell.
Summary of the invention
It can either can not be dropped again to the scanning pulse that grid line exports top rake it is an object of the present invention to provide a kind of
The shift register cell of the low driving capability to next stage shift register cell, and corresponding gate driving circuit and its
Driving method, display device.
In a first aspect, the present invention provides a kind of shift register cells, comprising:
First input module connects first node and scanning pulse input terminal, for being first in scanning pulse input terminal
When level, first node is set to the first level；
Second input module connects second node and scanning pulse input terminal, for being first in scanning pulse input terminal
When level, second node is set to the first level；
First output module, connection first node, the first scanning pulse output end and the first clock signal terminal；For
When one node is the first level, the first scanning pulse output end is connected with the first clock signal terminal；When first node suspends,
The charge for maintaining first node maintains the charge of the first scanning pulse output end when the first scanning pulse output end suspends；
Second output module, connection second node, the second scanning pulse output end and second clock signal end；For
When two nodes are the first level, the second scanning pulse output end is connected with second clock signal end；When second node suspends,
The charge for maintaining second node maintains the charge of the second scanning pulse output end when the second scanning pulse output end suspends；
First reseting module, connection first node, reseting controling end and first voltage end, for being the in reseting controling end
When one level, first node is connected with first voltage end；
Second reseting module connects first node, second node, third node, the first scanning pulse output end and first
Voltage end, for when third node is the first level, by first node, second node and the first scanning pulse output end and the
The conducting of one voltage end；
Third node control module, connection first voltage end, second voltage end, first node and third node, is used for
When first node is the first level, third node is set to the level at first voltage end；It is second electrical level and the in first node
When two voltage ends are the first level, third node is set to the first level.
Further, further includes: third reseting module, connection first node, second node, fourth node, the first scanning
Pulse output end and first voltage end, for when fourth node is the first level, first node, second node and first to be swept
Pulse output end is retouched to be connected with first voltage end；
Fourth node control module, connection first node, third node, fourth node, first voltage end and tertiary voltage
End, for any node in first node and third node be the first level when, fourth node is set to first voltage end
Level；When first node and third node are second electrical level and tertiary voltage end is the first level, fourth node is set
For the first level.
It further, further include the 4th reseting module, the 4th reseting module connection third node, fourth node and the
One voltage end, for when fourth node is the first level, third node to be connected with first voltage end.
Further, first input module includes the first transistor, and the grid of the first transistor connects scanning
Pulse input end, the 4th voltage end of connection in source electrode and drain electrode, another connection first node, conduction level first
Level.
Further, second input module includes second transistor, and the grid of the second transistor connects scanning
Pulse input end, a connection scanning pulse input terminal in source electrode and drain electrode, another connection second node, conduction level are
First level.
Further, first reseting module includes third transistor, and the grid of the third transistor, which connects, to be resetted
Control terminal, a connection first voltage end in source electrode and drain electrode, another connection first node, conduction level are the first electricity
It is flat.
Further, second reseting module includes the 4th transistor, the 5th transistor and the 6th transistor；
The grid of 4th transistor connects third node, a connection first voltage end in source electrode and drain electrode, separately
One connection first node；
The grid of 5th transistor connects third node, a connection first voltage end in source electrode and drain electrode, separately
One connection second node；
The grid of 6th transistor connects third node, a connection first voltage end in source electrode and drain electrode, separately
One the first scanning pulse output end of connection；
The conduction level of 4th transistor, the 5th transistor and the 6th transistor is the first level.
Further, first output module includes the 7th transistor and first capacitor；
The grid of 7th transistor connects first node, first clock signal of connection in source electrode and drain electrode
End, another first scanning pulse output end of connection, conduction level is the first level.
Further, second output module includes the 8th transistor and the second capacitor；
The grid of 8th transistor connects second node, a connection second clock signal in source electrode and drain electrode
End, another second scanning pulse output end of connection, conduction level is the first level.
Further, the third node control module, including the 9th transistor, the tenth transistor, the 11st transistor
With the tenth two-transistor；
The grid of 9th transistor and the tenth transistor connects first node；One in the source electrode and drain electrode of 9th transistor
A connection first voltage end, another connection third node；The first electricity of a connection in the source electrode and drain electrode of tenth transistor
Pressure side, another the 5th node of connection；
The grid of 11st transistor connects the 5th node, and a connection second voltage end in source electrode and drain electrode is another
A connection third node；
The grid of tenth two-transistor connects second voltage end, a connection second voltage end in source electrode and drain electrode, separately
One the 5th node of connection；
9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor conduction level be the first electricity
It is flat.
Further, the third reseting module includes the 13rd transistor, the 14th transistor and the 15th transistor；
The grid of 13rd transistor connects fourth node, first scanning pulse of connection in source electrode and drain electrode
Output end, another connection first voltage end, conduction level is the first level；
The grid of 14th transistor connects fourth node, a connection first node in source electrode and drain electrode, separately
One connection first voltage end, conduction level are the first level；
The grid of 15th transistor connects fourth node, a connection second node in source electrode and drain electrode, separately
One connection first voltage end；
The conduction level of 13rd transistor, the 14th transistor and the 15th transistor is the first level.
Further, the fourth node control module, including the 16th transistor, the 17th transistor, the 18th crystalline substance
Body pipe, the 19th transistor and the 20th transistor；
The grid of 20th transistor and the 16th transistor connects third node；The source electrode of 20th transistor and
A connection first voltage end in drain electrode, another connection fourth node；One in the source electrode and drain electrode of 16th transistor
A connection first voltage end, another the 6th node of connection；
The grid of 17th transistor connects the 6th node, and a connection tertiary voltage end in source electrode and drain electrode is another
A connection fourth node；
The grid of 18th transistor connects tertiary voltage end, a connection tertiary voltage end in source electrode and drain electrode, separately
One connection fourth node；
The grid of 19th transistor connects first node, and a connection first voltage end in source electrode and drain electrode is another
A connection fourth node；
16th transistor, the 17th transistor, the 18th transistor, the 19th transistor and the 20th transistor are led
The first level of energization average out to.
Further, the 4th reseting module includes the 21st transistor, the grid of the 21st transistor
Connect fourth node, a connection third node in source electrode and drain electrode, another connection first voltage end.
Further, first level is high level, and the second electrical level is low level.
Second aspect, the present invention provides a kind of gate driving circuits, comprising:
Multiple cascade shift register cells；The shift register cell is shift LD described in any of the above embodiments
Device unit and a plurality of driving line；
First clock signal terminal of each shift register cell of odd level is all connected with the first driving line, second clock letter
Number end connection second driving line；The first clock signal terminal connection third of each shift register cell of even level drives line,
Second clock signal end connects 4 wheel driven moving-wire；
Second scanning pulse output end of the upper level shift register cell in the shift register cell of adjacent two-stage
Connect the scanning pulse input terminal of next stage shift register cell；Second scanning pulse of next stage shift register cell is defeated
The reseting controling end of outlet connection upper level shift register cell.
The third aspect, the present invention provides a kind of methods for driving gate driving circuit described above, which is characterized in that
It include: to input second electrical level DC voltage at the first voltage end of each shift register cell；
The first clock signal is inputted in the first driving line, inputs second clock signal in the second driving line；It is driven in third
Line inputs third clock signal, inputs the 4th clock signal in 4 wheel driven moving-wire；
Initial sweep pulse is inputted in the scanning pulse input terminal of first order shift register cell；The initial sweep arteries and veins
The level of punching is the first level；
Wherein, the clock cycle phase of the first clock signal, second clock signal, third clock signal and the 4th clock signal
Together；Wherein, the voltage of the first level in the first clock signal and third clock signal is multistage；First clock signal and third
The duty ratio of clock signal is 1/2, and level state is opposite in real time；The duty ratio of second clock signal and the 4th clock signal
It is 1/2, and level state is opposite in real time；In second clock signal in the initial time of the first level and the first clock signal
The initial time of one level is identical, the initial time of the first level and the first level in third clock signal in the 4th clock signal
Initial time it is identical；
The initial time of initial sweep pulse is identical as the initial time of first level in third clock signal, knot
The beam moment is identical as the finish time of first level.
Fourth aspect, the present invention provides a kind of display devices, comprising: substrate and the gate driving being formed in substrate
Circuit and a plurality of grid line；Wherein, gate driving circuit is gate driving circuit described above, every level-one shift register list
First scanning pulse output end of member connects a grid line.
In shift register cell provided by the invention, there are two output modules for setting；Two output modules pass through respectively
Different scanning pulse output ends exports corresponding scanning pulse；It is cut accordingly even when one of scanning pulse is set as having
The scanning pulse at angle, it is nonetheless possible to use another scanning pulse drives next stage shift register cell；It will not reduce
To the driving capability of next stage shift register cell.In addition, two input modules are arranged in the present invention；One input module will
Scanning pulse can be conducted to first node, another input module can pass to scanning pulse to second node；And
One output module can export scanning pulse according to first node, another output module can be exported according to second node and be swept
Retouch pulse；The process of the output scanning pulse of two such output module will not influence each other, and can further avoid to wherein
Influence of the scanning pulse of one top rake to another scanning pulse, and then avoid influencing to next stage shift register cell
Driving capability.
Detailed description of the invention
Can be more clearly understood characteristic information and advantage of the invention by reference to attached drawing, attached drawing be schematically without
It is interpreted as carrying out any restrictions to the present invention, in the accompanying drawings:
Fig. 1 is a kind of structural schematic diagram of shift register cell provided by the invention；
Fig. 2 is a kind of structural schematic diagram of the structural schematic diagram of gate driving circuit provided by the invention；
Fig. 3 is the potential diagram to part signal and node in the driving method of the gate driving circuit in Fig. 2；
Fig. 4 is a kind of structural schematic diagram of shift register cell provided by the invention；
Fig. 5 is the structural schematic diagram of the structural schematic diagram of another gate driving circuit provided by the invention；
Fig. 6 is to comprising part signal and section in the driving method of the gate driving circuit of shift register cell in Fig. 4
The potential diagram of point；
Fig. 7 a, Fig. 7 b and Fig. 7 c are a kind of circuit diagram of shift register cell in Fig. 4.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
A kind of structure of shift register cell of the invention may refer to Fig. 1, and shift register cell SR includes such as
Flowering structure:
First input module 10 connects first node N1 and scanning pulse input terminal INPUT, for inputting in scanning pulse
When end INPUT is the first level, first node N1 is set to the first level；
Second input module 20 connects second node N2 and scanning pulse input terminal INPUT, for inputting in scanning pulse
When end INPUT is the first level, second node N2 is set to the first level；
First output module 30, connection first node N1, the first scanning pulse output end OUTPUT1 and the first clock signal
Hold CLK；For first node N1 be the first level when, by the first scanning pulse output end OUTPUT1 and the first clock signal
Hold CLK conducting；When first node N1 suspends, the charge of first node N1 is maintained, in the first scanning pulse output end OUTPUT1
When suspension (floating), the charge of the first scanning pulse output end OUTPUT1 is maintained；
Second output module 40, connection second node N2, the second scanning pulse output end OUTPUT2 and second clock signal
Hold CLK_L；For when second node N2 is the first level, the second scanning pulse output end OUTPUT2 and second clock to be believed
Number end CLK_L conducting；When second node N2 suspends, the charge of second node N2 is maintained, in the second scanning pulse output end
When OUTPUT2 suspends, the charge of the second scanning pulse output end OUTPUT2 is maintained；
First reseting module 50, connection first node N1, reseting controling end RESET and first voltage end V1, for multiple
When position control terminal RESET is the first level, first node N1 is connected with first voltage end VSS；
Second reseting module 60, connection first node N1, second node N2, third node N4, the output of the first scanning pulse
OUTPUT1 and first voltage end VSS is held, is used for when third node N3 is the first level, by first node N1, second node N2
It is connected with the first scanning pulse output end OUTPUT1 with first voltage end VSS；
Third node control module 70, connection first voltage end VSS, second voltage end GCH_o, first node N1 and third
Node N3, for when first node N1 is the first level, third node N3 to be set to the level of first voltage end VSS；?
When one node N1 is second electrical level and second voltage end GCH_e is the first level, third node N3 is set to the first level.
Gate driving circuit GOA comprising the shift register cell in Fig. 1 can refer to Fig. 2, including N grades (assuming that N is
Even number) shift register cell；For the ease of distinguishing, m grades of shift register cells therein are known as SR (m)；Referring to
Fig. 2 moves the shift register cell of any two-stage neighboring, such as first order shift register cell SR (1) and the second level
Bit register cell S R (2)；Wherein the second scanning pulse output end OUTPUT2 of upper level shift register cell SR (1) connects
Meet the scanning pulse input terminal INPUT of next stage shift register cell SR (2)；Next stage shift register cell SR's (2)
The reseting controling end RESET of second scanning pulse output end OUTPUT2 connection upper level shift register cell SR (1)；In addition,
The shift register cell of each odd level, such as first order shift register cell SR (1) and penultimate stage shift LD
The first clock signal terminal CLK of device cell S R (N-1) is connected, and is all connected with the first clock cable CLK1, second clock signal
It holds CLK_L to be also connected, is all connected with second clock signal wire CLK2；And the shift register cell of each even level, such as the
The first clock signal terminal CLK of level-one shift register cell SR (2) and penultimate stage shift register cell SR (N) is homogeneous
Even, it is all connected with third clock cable CLK3, second clock signal end CLK_L is also connected, and is all connected with the 4th clock cable
CLK4。
Shift register cell and gate driving circuit provided by the invention can export two relatively independent pulses,
So as to use another scanning pulse to drive next stage shift register cell；It will not reduce and next stage is shifted
The driving capability of register cell.In addition, the process of the output scanning pulse of two output modules will not influence each other, Ke Yijin
One step avoids influence of the scanning pulse to one of top rake to another scanning pulse, and then avoids influencing to move next stage
The driving capability of bit register unit.
Below with reference to Fig. 3 to Fig. 2 shows gate driving circuit one of driving method and its realize its function
Principle be illustrated.Referring to Fig. 3, it is assumed that the first level here is high level, then corresponding second electrical level is low level.It should
Method can specifically include:
Second electrical level DC voltage is inputted at the first voltage end of each shift register cell；
The first level direct voltage is inputted in the second voltage end GCH_o of each shift register cell；
First the first clock signal clk 1 of driving line CLK1 input (for ease of description, will on each driving line it is defeated
The clock signal and the driving line entered is indicated using identical symbol), second clock signal is inputted in the second driving line CLK2
CLK2；Third clock signal clk 3 is inputted in third driving line CLK3, inputs the 4th clock signal in 4 wheel driven moving-wire CLK4
CLK4；
Initial sweep pulse STV is inputted in the scanning pulse input terminal INPUT of first order shift register cell SR (1)；
The level of the initial sweep pulse STV is the first level；
Wherein, the first clock signal clk 1, second clock signal CLK2, third clock signal clk 3 and the 4th clock signal
The clock cycle of CLK4 is identical；Wherein, the voltage of the first clock signal clk 1 and the first level in third clock signal clk 3
To be multistage, the voltage of second clock signal CLK2 and the first level in the 4th clock signal clk 4 is steady state value；First clock
The duty ratio of signal CLK1 and third clock signal clk 3 is 1/2, and level state is opposite in real time；Second clock signal CLK2
Duty ratio with the 4th clock signal clk 4 is 1/2, and level state is opposite in real time；First electricity in second clock signal CLK2
Flat initial time is identical as the initial time of the first level in the first clock signal clk 1, first in the 4th clock signal clk 4
The initial time of level is identical as the initial time of the first level in third clock signal clk 3；
The initial time of initial sweep pulse STV and the initial time of first level in third clock signal clk 3
Identical, finish time is identical as the finish time of first level.
Referring to Fig. 3, for first order shift register cell SR (1), S1, initial sweep pulse STV are in the first stage
First level, then first node N1 and second node N2 are set to by the first input module 10 and the second input module 20 respectively at this time
First level, the first clock signal terminal CLK is connected with the first scanning pulse output end OUTPUT1 at this time, second clock signal end
CLK_L is connected with the second scanning pulse output end OUTPUT2；By the driving line that the first clock signal terminal CLK is connected at this time
CLK1 and and the driving line CLK2 that is connected of second clock signal end CLK_L be second electrical level, then the first scanning pulse is defeated
Entering to hold OUTPUT1 and the second scanning pulse output end OUTPUT2 is second electrical level；Additionally, due to first order shift register list
The second scanning pulse output end of the second level shift register cell SR (2) of the reseting controling end RESET connection of first SR (1)
OUTPUT2 is second electrical level, then the reseting controling end RESET of first order shift register cell SR (1) is second electrical level at this time；
In addition, for first order shift register cell SR (1), since first node N1 is the first level, then the second reseting module 60
So that the level of third node N3 and the level of first voltage end VSS are consistent, it is second electrical level；
First order shift register cell SR (1) is continued in second stage S2, node N1 and N2 see also Fig. 3
It is maintained the first level；First clock signal terminal CLK continues to be connected with the first scanning pulse output end OUTPUT1, second clock
Signal end CLK_B continues to be connected with the second scanning pulse output end OUTPUT2；First driving line CLK1 and the second driving line CLK2
It is the first level, corresponding first clock signal terminal CLK and second clock signal end CLK_L are also the first level；So that
First scanning pulse output end OUTPUT1 and the second scanning pulse output end OUTPUT2 starts to export the scanning arteries and veins of the first level
Punching；And at this stage, the waveform and the first clock signal for the scanning pulse that the first scanning pulse output end OUTPUT1 is exported
CLK1 is consistent, and is two rank voltages；The waveform for the scanning pulse that second scanning pulse output end OUTPUT2 is exported and
Two clock signal clks 2 are consistent, and voltage therein is steady state value；In addition, in first order shift register cell SR (1), it is multiple
Position control terminal RESET is maintained second electrical level, and third node N3 is also maintained second electrical level；
In second stage S2, for second level shift register cell SR (2), and each terminal (including two clocks letters
Number end CLK and CLK_B, scanning pulse input terminal INPUT and reseting controling end RESET) with first order shift register cell SR
(1) the case where signal that S1 is entered in the first stage, is consistent, therefore each section in second level shift register cell SR (2)
The current potential feelings of the current potential situation and first order shift register cell SR (1) S1 in the first stage of point and scanning pulse output end
Condition is completely the same, is no longer described in detail herein.
In phase III S3, for second level shift register cell SR (2), and each terminal (including two clocks letters
Number end CLK and CLK_B, scanning pulse input terminal INPUT and reseting controling end RESET) with first order shift register cell SR
(1) consistent the signal that second stage S2 is entered the case where, thus also by the first scanning pulse output end OUTPUT1 and
Second scanning pulse output end OUTPUT2 exports corresponding scanning pulse；
In phase III S3, for first order shift register cell SR (1), reseting controling end RESET is connected
The second scanning pulse output end OUTPUT2 of second level shift register cell SR (2) is the first level, then the first reset at this time
First node N1 is connected module 50 with first voltage end VSS, and first node N is set to second electrical level；It further results in this way
Third node N3 is set to the level of second voltage end GCH_e, i.e. the first level by third node control module 70；And third node
N3 is set to the first level, and can further result in first node N1, second node N2 and be connected with first voltage end VSS, realizes
Reset to first node and second node N2, and it is further ensured that first node N1 is maintained second electrical level；At this stage
Later, until first order shift register cell SR (1) scanning pulse input terminal INPUT be set to again the first level it
Before, the first node N1 in first order shift register cell SR (1) is maintained second electrical level, corresponding second node N1,
Third node N3 is also maintained the first level；
In fourth stage S4, for second level shift register cell SR (2), and each terminal (including two clocks letters
Number end CLK and CLK_B, scanning pulse input terminal INPUT and reseting controling end RESET and the first scanning pulse output end
OUTPUT1 and the second scanning pulse output end OUTPUT2) with first order shift register cell SR (1) phase III S3's
Situation is consistent, no longer illustrates herein.
It is not difficult to find out from above-mentioned driving process, for the shift register cell of adjacent two-stage, rear stage displacement
The state of signal of each terminal of register cell received by the current generation is each with upper level shift register cell
A terminal is completely the same in the potential state of signal received on last stage, in this way according to the description above it is known that
Shift register cells at different levels can be sequentially output multiple scanning pulses.
It should be pointed out that driving method shown in Fig. 3 is only a kind of possibility of the gate driving circuit provided in Fig. 2
Driving method, in practical applications, corresponding driving method is not limited to form shown in Fig. 3.
In the specific implementation, other than the basic structure shown by shift register cell shown in Fig. 1, the present invention
The shift register cell of offer can also include other structures, be another embodiment referring to fig. 4 to further improve performance
The structural schematic diagram of the shift register cell of offer；It further include that third resets mould other than the modules shown in Fig. 1
Block 80, fourth node control module 90；4th reseting module 100；
Wherein, third reseting module 80 connects first node N1, fourth node N4, the first scanning pulse output end
OUTPUT1 and first voltage end VSS, for when fourth node N4 is the first level, first node N1 and first to be scanned arteries and veins
Output end is rushed to be connected with first voltage end VSS；
Fourth node control module 90 connects first node N1, third node N3, fourth node N4, first voltage end VSS
With tertiary voltage end GCH_O, for any node in first node N1 and third node N3 be the first level when, by the 4th
Node N4 is set to the level of first voltage end VSS；It is second electrical level and tertiary voltage in first node N1 and third node N3
When end is the first level, fourth node N4 is set to the first level.
The benefit that third reseting module 80 and fourth node control module 90 is arranged is can to pass through third reseting module 80
With the second reseting module 60 alternately to first node N1, second node N2 and the first scanning pulse output end OUTPUT1 into
The lasting reset of row, avoid for a long time to third reseting module 80 apply for make third reseting module 80 to first node N1,
The signal that second node N2 and the first scanning pulse output end OUTPUT1 are resetted, avoids the property of third reseting module 80
It can reduce.
The structural schematic diagram of gate driving circuit comprising the shift register cell in Fig. 4 may refer to Fig. 5, with Fig. 2
Unlike, each shift register cell SR also has tertiary voltage end GCH_e；The third of each shift register cell SR
Voltage end GCH_e is connected with each other.
With reference to the accompanying drawing 6 pairs comprising Fig. 5 gate driving circuit a kind of driving method and its working principle carry out
Explanation.In Fig. 6, it is also assumed that the first level is high level, and second electrical level is low level；It is different from shown in Fig. 3 referring to Fig. 6
, in this method, alternately apply the first level in second voltage end GCH_e and tertiary voltage end GCH_o；In this way first
Node N1 is set to after low level, and when second voltage end GCH_e is the first level, third node N3 is the first level, is made
It obtains the second reseting module 60 and opens reset function, to first node N1, second node N2 and the first scanning pulse output end
OUTPUT1 is resetted；When second voltage end GCH_e be second electrical level when, third node N3 be second electrical level, Section four at this time
Fourth node N4 is set to the level of tertiary voltage end GCH_o, as the first level by point control module 90；So that third is multiple
Position module 80 opens reset function, carries out to first node N1, second node N2 and the first scanning pulse output end OUTPUT1
It resets.It thereby realizes alternately by third reseting module 80 and the second reseting module 60 to first node N1, the second section
The function that point N2 and the first scanning pulse output end OUTPUT1 are resetted.
From the description above it is known that just alternately passing through third reseting module 80 and the second reseting module to realize
For 60 realize the function of resetting, the 4th reseting module 100 here is it is not necessary to the structure being arranged.
4th reseting module 100, connection third node N3, fourth node N4 and first voltage end VSS, at Section four
When point N4 is the first level, third node N3 is connected with first voltage end VSS.
Be arranged the 4th reseting module 100 benefit be can fourth node N4 be the first level when, by third node N3 quilt
It is set to second electrical level, to preferably close the reset function of the second reseting module 60.
From the description above it is known that under the premise of can be realized corresponding function, each functional module is specifically such as
What design will not influence protection scope of the present invention.Some optional modes of each functional module are carried out further below
Explanation.
In the specific implementation, referring to Fig. 7 a, the first input module 10 can be specifically included: the first transistor T1, first is brilliant
The grid of body pipe T1 connects scanning pulse input terminal INPUT, connection a 4th voltage end VDD in source electrode and drain electrode, another
A connection first node N1, conduction level are the first level.
It in this way can be by lasting the first level direct voltage on the 4th voltage end VDD, so that when scanning pulse is defeated
When entering that INPUT is held to be applied the first level, the first transistor T1 conducting will lead to, the level of first node N1 is set to the 4th electricity
The level of pressure side VDD, i.e. the first level, to realize the function of the first above-mentioned input module 10.
In the specific implementation, referring to Fig. 7 a, the second input module 20 can specifically include second transistor T2, the second crystal
The grid of pipe T2 connects scanning pulse input terminal INPUT, a connection scanning pulse input terminal INPUT in source electrode and drain electrode,
Another connection second node N2, conduction level are the first level.
In this way, will lead to second transistor T2 conducting when scanning pulse input terminal INPUT is applied the first level, it will
The level of second node N2 is set to the level of scanning pulse input terminal INPUT, i.e. the first level, to realize above-mentioned second
The function of input module 20.
In the specific implementation, referring to Fig. 7 a, the first reseting module 50 may include third transistor T3, third transistor T3
Grid connect reseting controling end RESET, a connection first voltage end VSS in source electrode and drain electrode, another connects first
Node N1, conduction level are the first level.
In this way when reseting controling end RESET is applied the first level, third transistor T3 conducting will lead to, by first segment
The level of point N1 is set to the level of first voltage end VSS (can be in the DC voltage of second voltage end VSS application second electrical level),
That is second electrical level, to realize the function of the first above-mentioned reseting module 30.
In the specific implementation, referring to Fig. 7 b, the second reseting module 60 can specifically include the 4th transistor T4, the 5th crystal
Pipe T5 and the 6th transistor T6；
The grid of 4th transistor T4 connects third node N3, a connection first voltage end VSS in source electrode and drain electrode,
Another connection first node N1；
The grid of 5th transistor T5 connects third node N3, a connection first voltage end VSS in source electrode and drain electrode,
Another connection second node N2；
The grid of 6th transistor T6 connects third node N3, a connection first voltage end VSS in source electrode and drain electrode,
The first scanning pulse output end OUTPUT1 of another connection；
The conduction level of 4th transistor T4, the 5th transistor T5 and the 6th transistor T6 are the first level.
In this way, when third node N3 is the first level, the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6
It is both turned on, first node N1, second node N2 and the first scanning pulse output end OUTPUT1 is set to second electrical level respectively；It is complete
The reset of pairs of three nodes realizes the function of the second above-mentioned reseting module 60.
In the specific implementation, referring to Fig. 7 a, the first output module 30 can specifically include the electricity of the 7th transistor T7 and first
Hold C1；
The grid of 7th transistor T7 connects first node N1, first clock signal terminal of connection in source electrode and drain electrode
CLK, the first scanning pulse output end OUTPUT1 of another connection, conduction level is the first level.
In this way when first node N1 is the first level, the 7th transistor T7 conducting will lead to, the first scanning pulse is defeated
Outlet OUTPUT1 is connected with the first clock signal terminal CLK, realizes the function of the first above-mentioned output module 30.
In the specific implementation, referring to Fig. 7 a, the second output module 40 can specifically include the electricity of the 8th transistor T8 and second
Hold C2；
The grid of 8th transistor T8 connects second node N2, a connection second clock signal end in source electrode and drain electrode
CLK_L, the second scanning pulse output end OUTPUT2 of another connection, conduction level is the first level.
In this way when second node N2 is the first level, the 8th transistor T8 conducting will lead to, the second scanning pulse is defeated
Outlet OUTPUT2 is connected with second clock signal end CLK_L, realizes the function of the second above-mentioned output module 40.
In the specific implementation, referring to Fig. 7 a, third node control module 70 can specifically include the 9th transistor T9, the tenth
Transistor T10, the 11st transistor T11 and the tenth two-transistor T12；
The grid of 9th transistor T9 and the tenth transistor T10 connects first node N1；The source electrode of 9th transistor T9 and
A connection first voltage end VSS in drain electrode, another connection third node N3；The source electrode and drain electrode of tenth transistor T10
In a connection first voltage end VSS, another connection the 5th node N5；
The grid of 11st transistor T11 connects the 5th node N5, a connection second voltage end in source electrode and drain electrode
GCH_e, another connection third node N3；
The grid of tenth two-transistor connects second voltage end GCH_e, a connection second voltage in source electrode and drain electrode
GCH_e is held, the 5th node N5 of another connection；
9th transistor T9, the tenth transistor T10, the 11st transistor T11 and the tenth two-transistor T12.
In this way when first node N1 is the first level, the 9th transistor T9 and the tenth transistor T10 are both turned on, by the 5th
Node N5 and third node N3 are connected with first voltage end VSS, so that third node N3 is set to second electrical level；Work as first segment
When point N1 is second electrical level, the 9th transistor T9 and the tenth transistor T10 are turned off, at this time since the tenth two-transistor T12 is led
Logical, the level that the 5th node N5 can be set to second voltage end GCH_e (can apply the on the GCH_e of second voltage end at this time
One level) so that the 5th node N5 is set to the first level, so that the 11st transistor T11 is connected, by third node N3
It is set to the first level.Thereby realize the function of above-mentioned third node control module 70
Referring to Fig. 7 c, in the specific implementation, third reseting module 80 can specifically include the 13rd transistor T13, the tenth
Four transistor T14 and the 15th transistor T15；
The grid of 13rd transistor T13 connects fourth node N4, a connection the first scanning arteries and veins in source electrode and drain electrode
Output end OUTPUT1 is rushed, another connection first voltage end VSS, conduction level is the first level；
The grid of 14th transistor connects fourth node N4, a connection first node N1 in source electrode and drain electrode, separately
One connection first voltage end VSS, conduction level are the first level；
The grid of 15th transistor connects fourth node, a connection second node N2 in source electrode and drain electrode, another
A connection first voltage end VSS.
When fourth node N4 is the first level, the 13rd transistor T13, the 14th transistor T14 and the 15th crystal
Pipe T15 is both turned on, by first node N1, second node N2 and the first scanning pulse output end OUTPUT1 and first voltage end VSS
Conducting, so that three nodes are set to second electrical level, thereby realizes the function of above-mentioned third reseting module 80.
Referring to Fig. 7 a, in the specific implementation, fourth node control module 90, can specifically include the 16th transistor T16,
17th transistor T17, the 18th transistor T18, the 19th transistor T19 and the 20th transistor T20；
The grid of 20th transistor T20 and the 16th transistor T16 connects third node N3；20th transistor T20
Source electrode and drain electrode in a connection first voltage end VSS, another connection fourth node N4；16th transistor T16's
A connection first voltage end VSS in source electrode and drain electrode, the 6th node N6 of another connection；
The grid of 17th transistor connects the 6th node N6, a connection tertiary voltage end GCH_ in source electrode and drain electrode
O, another connection fourth node N4；
The grid of 18th transistor T18 connects tertiary voltage end GCH_o, a connection third electricity in source electrode and drain electrode
Pressure side GCH_o, another connection fourth node N4；
The grid of 19th transistor T19 connects first node N1, a connection first voltage end in source electrode and drain electrode
VSS, another connection fourth node N4；
16th transistor T16, the 17th transistor T17, the 18th transistor T18, the 19th transistor T19 and second
The conduction level of ten transistor T20 is the first level.
In this way when first node N1 is the first level, the 19th transistor T19 conducting, by the electricity of fourth node N4 and first
Pressure side VSS conducting, so that fourth node N4 is set to second electrical level；And when third node N3 is the first level, the 20th is brilliant
Body pipe T20 and the 16th transistor T16 are both turned on, so that the 6th node N6 and fourth node N4 are set to the first level；When
When first node N1 and third node N3 are second electrical level, the 20th transistor T20 and the 16th transistor T16 and the tenth
Nine transistor T19 are turned off；17th transistor T17 conducting at this time (in the specific implementation, can apply on GCH_o at this time
First level) so that the 6th node N6 is set to the first level, and then causes the 18th transistor T18 to be connected, by fourth node
N4 is set to the first level.Thereby realize the function of above-mentioned fourth node control module 90.
In the specific implementation, referring to Fig. 7, the 4th reseting module 100 can specifically include the 21st transistor T21, the
The grid of 21 transistor T21 connects fourth node N4, a connection third node N3 in source electrode and drain electrode, another company
Meet first voltage end VSS.
In this way, can make when fourth node N4 is the first level, the 21st transistor T21 is connected, by third section
Point N3 is connected with first voltage end VSS, is set to second electrical level.Has the function of realizing the 4th reseting module 100 in this way.
In the specific embodiment of above-mentioned cited modules, the transistor that modules are included is conducting
Electricity is the transistor of the first level, can be made by identical technique in this way, can reduce manufacture difficulty.
In another aspect, being driven the present invention also provides a kind of display device including substrate and the grid being formed in substrate
Dynamic circuit and a plurality of grid line；Wherein, gate driving circuit is gate driving circuit described in any of the above embodiments, every level-one displacement
First scanning pulse output end of register cell connects a grid line.
Here display device can be with are as follows: Electronic Paper, mobile phone, tablet computer, television set, display, laptop, number
Any products or components having a display function such as code photo frame, navigator.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that implementation of the invention
Example can be practiced without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this specification.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (17)
1. a kind of shift register cell characterized by comprising
First input module connects first node and scanning pulse input terminal, for being the first level in scanning pulse input terminal
When, first node is set to the first level；
Second input module connects second node and scanning pulse input terminal, for being the first level in scanning pulse input terminal
When, second node is set to the first level；
First output module, connection first node, the first scanning pulse output end and the first clock signal terminal；For in first segment
When point is the first level, the first scanning pulse output end is connected with the first clock signal terminal；When first node suspends, maintain
The charge of first node maintains the charge of the first scanning pulse output end when the first scanning pulse output end suspends；
Second output module, connection second node, the second scanning pulse output end and second clock signal end；For in the second section
When point is the first level, the second scanning pulse output end is connected with second clock signal end；When second node suspends, maintain
The charge of second node maintains the charge of the second scanning pulse output end when the second scanning pulse output end suspends；
First reseting module, connection first node, reseting controling end and first voltage end, for being the first electricity in reseting controling end
Usually, first node is connected with first voltage end；
Second reseting module, connection first node, second node, third node, the first scanning pulse output end and first voltage
End is used for when third node is the first level, by first node, second node and the first scanning pulse output end and the first electricity
Pressure side conducting；
Third node control module, connection first voltage end, second voltage end, first node and third node, for first
When node is the first level, third node is set to the level at first voltage end；It is second electrical level and the second electricity in first node
When pressure side is the first level, third node is set to the first level.
2. shift register cell according to claim 1, which is characterized in that further include: third reseting module, connection the
One node, second node, fourth node, the first scanning pulse output end and first voltage end, for being first in fourth node
When level, first node, second node and the first scanning pulse output end are connected with first voltage end；
Fourth node control module, connection first node, third node, fourth node, first voltage end and tertiary voltage end, is used
When any node in first node and third node is the first level, fourth node is set to the electricity at first voltage end
It is flat；When it is the first level that first node and third node, which are second electrical level and tertiary voltage end, fourth node is set to the
One level.
3. shift register cell according to claim 2, which is characterized in that it further include the 4th reseting module, described
Four reseting modules connect third node, fourth node and first voltage end, are used for when fourth node is the first level, by third
Node is connected with first voltage end.
4. shift register cell according to claim 1, which is characterized in that first input module includes first brilliant
Body pipe, the grid of the first transistor connect scanning pulse input terminal, the 4th voltage end of connection in source electrode and drain electrode,
Another connection first node, conduction level are the first level.
5. shift register cell according to claim 1, which is characterized in that second input module includes second brilliant
Body pipe, the grid of the second transistor connect scanning pulse input terminal, and a connection scanning pulse in source electrode and drain electrode is defeated
Enter end, another connection second node, conduction level is the first level.
6. shift register cell according to claim 1, which is characterized in that first reseting module includes third crystalline substance
Body pipe, the grid of the third transistor connect reseting controling end, and a connection first voltage end in source electrode and drain electrode is another
A connection first node, conduction level are the first level.
7. shift register cell according to claim 1, which is characterized in that second reseting module includes the 4th brilliant
Body pipe, the 5th transistor and the 6th transistor；
The grid of 4th transistor connects third node, a connection first voltage end in source electrode and drain electrode, another
Connect first node；
The grid of 5th transistor connects third node, a connection first voltage end in source electrode and drain electrode, another
Connect second node；
The grid of 6th transistor connects third node, a connection first voltage end in source electrode and drain electrode, another
Connect the first scanning pulse output end；
The conduction level of 4th transistor, the 5th transistor and the 6th transistor is the first level.
8. shift register cell according to claim 1, which is characterized in that first output module includes the 7th brilliant
Body pipe and first capacitor；
The grid of 7th transistor connects first node, first clock signal terminal of connection in source electrode and drain electrode, separately
One the first scanning pulse output end of connection, conduction level are the first level.
9. shift register cell according to claim 1, which is characterized in that second output module includes the 8th brilliant
Body pipe and the second capacitor；
The grid of 8th transistor connects second node, a connection second clock signal end in source electrode and drain electrode, separately
One the second scanning pulse output end of connection, conduction level are the first level.
10. shift register cell according to claim 1, which is characterized in that the third node control module, including
9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；
The grid of 9th transistor and the tenth transistor connects first node；A company in the source electrode and drain electrode of 9th transistor
First voltage end is connect, another connection third node；A connection first voltage end in the source electrode and drain electrode of tenth transistor,
Another the 5th node of connection；
The grid of 11st transistor connects the 5th node, a connection second voltage end in source electrode and drain electrode, another company
Connect third node；
The grid of tenth two-transistor connects second voltage end, a connection second voltage end in source electrode and drain electrode, another
Connect the 5th node；
9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor conduction level be the first level.
11. shift register cell as claimed in claim 2, which is characterized in that the third reseting module includes the 13rd
Transistor, the 14th transistor and the 15th transistor；
The grid of 13rd transistor connects fourth node, first scanning pulse of the connection output in source electrode and drain electrode
End, another connection first voltage end, conduction level is the first level；
The grid of 14th transistor connects fourth node, a connection first node in source electrode and drain electrode, another
First voltage end is connected, conduction level is the first level；
The grid of 15th transistor connects fourth node, a connection second node in source electrode and drain electrode, another
Connect first voltage end；
The conduction level of 13rd transistor, the 14th transistor and the 15th transistor is the first level.
12. shift register cell as claimed in claim 2, which is characterized in that the fourth node control module, including the
16 transistors, the 17th transistor, the 18th transistor, the 19th transistor and the 20th transistor；
The grid of 20th transistor and the 16th transistor connects third node；The source electrode and drain electrode of 20th transistor
In a connection first voltage end, another connection fourth node；A company in the source electrode and drain electrode of 16th transistor
First voltage end is connect, another the 6th node of connection；
The grid of 17th transistor connects the 6th node, a connection tertiary voltage end in source electrode and drain electrode, another company
Connect fourth node；
The grid of 18th transistor connects tertiary voltage end, a connection tertiary voltage end in source electrode and drain electrode, another
Connect fourth node；
The grid of 19th transistor connects first node, a connection first voltage end in source electrode and drain electrode, another company
Connect fourth node；
16th transistor, the 17th transistor, the 18th transistor, the 19th transistor and the 20th transistor electric conduction
The first level of average out to.
13. shift register cell as claimed in claim 3, which is characterized in that the 4th reseting module includes the 20th
One transistor, the grid of the 21st transistor connect fourth node, a connection third node in source electrode and drain electrode,
Another connection first voltage end.
14. such as the described in any item shift register cells of claim 1-13, which is characterized in that first level is high electricity
Flat, the second electrical level is low level.
15. a kind of gate driving circuit characterized by comprising
Multiple cascade shift register cells；The shift register cell is such as the described in any item shiftings of claim 1-14
Bit register unit and a plurality of driving line；
First clock signal terminal of each shift register cell of odd level is all connected with the first driving line, second clock signal end
Connection the second driving line；The first clock signal terminal connection third driving line of each shift register cell of even level, second
Clock signal terminal connects 4 wheel driven moving-wire；
Second scanning pulse output end of the upper level shift register cell in the shift register cell of adjacent two-stage connects
The scanning pulse input terminal of next stage shift register cell；Second scanning pulse output end of next stage shift register cell
Connect the reseting controling end of upper level shift register cell.
16. a kind of method for driving gate driving circuit as claimed in claim 15 characterized by comprising in each shifting
The first voltage end of bit register unit inputs second electrical level DC voltage；
The first clock signal is inputted in the first driving line, inputs second clock signal in the second driving line；It is defeated in third driving line
Enter third clock signal, inputs the 4th clock signal in 4 wheel driven moving-wire；
Initial sweep pulse is inputted in the scanning pulse input terminal of first order shift register cell；The initial sweep pulse
Level is the first level；
Wherein, the first clock signal, second clock signal, third clock signal are identical with the clock cycle of the 4th clock signal；
Wherein, the voltage of the first level in the first clock signal and third clock signal is multistage；When the first clock signal and third
The duty ratio of clock signal is 1/2, and level state is opposite in real time；The duty ratio of second clock signal and the 4th clock signal is equal
It is 1/2, and level state is opposite in real time；In second clock signal first in the initial time of the first level and the first clock signal
The initial time of level is identical, the initial time of the first level and the first level in third clock signal in the 4th clock signal
Initial time is identical；
The initial time of initial sweep pulse is identical as the initial time of first level in third clock signal, at the end of
It carves identical as the finish time of first level.
17. a kind of display device characterized by comprising substrate and the gate driving circuit being formed in substrate and more
Grid line；Wherein, gate driving circuit is gate driving circuit as claimed in claim 15, every level-one shift register cell
The first scanning pulse output end connect a grid line.
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| CN107749276B (en) * | 2017-11-28 | 2020-06-23 | 上海天马有机发光显示技术有限公司 | Organic light-emitting display panel and organic light-emitting display device |
| CN108257578A (en) | 2018-04-16 | 2018-07-06 | 京东方科技集团股份有限公司 | Shift register cell and its control method, gate drive apparatus, display device |
| CN108735162B (en) | 2018-05-25 | 2020-04-03 | 京东方科技集团股份有限公司 | Display device, grid drive circuit, shift register and control method thereof |
| US11640795B2 (en) | 2018-08-29 | 2023-05-02 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit and drive method |
| CN109935201B (en) | 2018-08-29 | 2020-10-09 | 合肥鑫晟光电科技有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN109166542B (en) * | 2018-09-26 | 2024-05-07 | 合肥鑫晟光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN110390903B (en) * | 2019-06-20 | 2022-12-30 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN111415624B (en) | 2020-04-29 | 2021-05-14 | 京东方科技集团股份有限公司 | Shift register circuit and driving method thereof, gate drive circuit and display device |
| CN115035863A (en) * | 2022-06-30 | 2022-09-09 | 厦门天马微电子有限公司 | Gate drive circuit of light-emitting panel and light-emitting panel |
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