CN105957470A - Shift register unit, gate drive circuit and drive method thereof and display device - Google Patents
Shift register unit, gate drive circuit and drive method thereof and display device Download PDFInfo
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- CN105957470A CN105957470A CN201610534144.4A CN201610534144A CN105957470A CN 105957470 A CN105957470 A CN 105957470A CN 201610534144 A CN201610534144 A CN 201610534144A CN 105957470 A CN105957470 A CN 105957470A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a shift register unit, a gate drive circuit and a drive method thereof and a display device. The shift register unit is provided with two output modules which output corresponding scanning pulses through different scanning pulse output ends so that the other scanning pulse can still be used to drive the next shift register unit even one of the scanning pulses is set as the scanning pulse with a cutting angle, and thus the driving capacity for the next shift register unit is not reduced. Besides, two input modules are arranged so that the process of scanning pulse outputting of the two output modules is not mutually influenced, the influence of one of the scanning pulses with the cutting angle on the other scanning pulse can be further avoided, and thus the influence on the driving capacity for the next shift register unit can be avoided.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of shift register cell, gate driver circuit and drive
Dynamic method, display device.
Background technology
GOA (Gate Driver On Array, gate driver circuit is integrated on array base palte) is to realize display device
A kind of important means on narrow limit.General, the gate driver circuit being integrated on array base palte is by multistage shift register
Unit forms, and every one-level shift register cell is successively under the driving of the scanning impulse of upper level shift register cell output
Export scanning impulse to corresponding grid line so that each thin film transistor (TFT) conducting that each grid line is connected, thus realize
Driving process to corresponding pixel cell；And the scanning impulse that this grade of shift register cell is exported also can export down
One-level shift register cell realizes the driving to next stage shift register cell.
On the other hand, TFT gate is down to Vgl from Vgh at the end of charging process, in the impact of gate-source parasitic capacitance
Under, the voltage of pixel electrode declines therewith, the amplitude of decline and the size of gate-source electric capacity and Vgh (gate high-voltage) and Vgl
Pressure reduction between (gate high-voltage) is directly proportional.The display effect of display device can be impacted by this pressure drop phenomena, in order to
Promote the display effect of display device, it is generally required to the end of the scanning impulse being applied on each bar grid line is carried out top rake formation
Multistage gate voltage.As described above, owing to the driving of scanning impulse next stage to be used as shift register cell itself is believed
Number, the most such top rake can reduce this scanning impulse driving force to next stage shift register cell.
Summary of the invention
It is an object of the present invention to provide a kind of can either to grid line output top rake scanning impulse can not drop again
The shift register cell of the low driving force to next stage shift register cell, and corresponding gate driver circuit and
Driving method, display device.
First aspect, the invention provides a kind of shift register cell, including:
First input module, connects primary nodal point and scanning impulse input, and being used at scanning impulse input is first
During level, primary nodal point is set to the first level；
Second input module, connects secondary nodal point and scanning impulse input, and being used at scanning impulse input is first
During level, secondary nodal point is set to the first level；
First output module, connects primary nodal point, the first scanning impulse outfan and the first clock signal terminal；For
When one node is the first level, the first scanning impulse outfan and the first clock signal terminal are turned on；When primary nodal point suspends,
Maintain the electric charge of primary nodal point, when the first scanning impulse outfan suspends, maintain the electric charge of the first scanning impulse outfan；
Second output module, connects secondary nodal point, the second scanning impulse outfan and second clock signal end；For
When two nodes are the first level, the second scanning impulse outfan is turned on second clock signal end；When secondary nodal point suspends,
Maintain the electric charge of secondary nodal point, when the second scanning impulse outfan suspends, maintain the electric charge of the second scanning impulse outfan；
First reseting module, connects primary nodal point, reseting controling end and the first voltage end, for being the at reseting controling end
During one level, primary nodal point and the first voltage end are turned on；
Second reseting module, connects primary nodal point, secondary nodal point, the 3rd node, the first scanning impulse outfan and first
Voltage end, for when the 3rd node is the first level, by primary nodal point, secondary nodal point and the first scanning impulse outfan and the
One voltage end conducting；
3rd node control module, connects the first voltage end, the second voltage end, primary nodal point and the 3rd node, is used for
When primary nodal point is the first level, the 3rd node is set to the level of the first voltage end；It is second electrical level and at primary nodal point
When two voltage ends are the first level, the 3rd node is set to the first level.
Further, also include: the 3rd reseting module, connect primary nodal point, secondary nodal point, fourth node, the first scanning
Pulse output end and the first voltage end, for when fourth node is the first level, sweep primary nodal point, secondary nodal point and first
Retouch pulse output end and the conducting of the first voltage end；
Fourth node control module, connects primary nodal point, the 3rd node, fourth node, the first voltage end and tertiary voltage
End, when any node being used in primary nodal point and the 3rd node is the first level, is set to the first voltage end by fourth node
Level；When primary nodal point and the 3rd node are second electrical level and tertiary voltage end is the first level, fourth node is put
It it is the first level.
Further, also including the 4th reseting module, described 4th reseting module connects the 3rd node, fourth node and the
One voltage end, for when fourth node is the first level, turns on the 3rd node and the first voltage end.
Further, described first input module includes the first transistor, and the grid of described the first transistor connects scanning
One in pulse input end, source electrode and drain electrode connects the 4th voltage end, and another connects primary nodal point, and conduction level is first
Level.
Further, described second input module includes transistor seconds, and the grid of described transistor seconds connects scanning
One in pulse input end, source electrode and drain electrode connects scanning impulse input, and another connects secondary nodal point, and conduction level is
First level.
Further, described first reseting module includes third transistor, and the grid of described third transistor connects reset
Controlling connection first voltage end in end, source electrode and drain electrode, another connects primary nodal point, and conduction level is the first electricity
Flat.
Further, described second reseting module includes the 4th transistor, the 5th transistor and the 6th transistor；
The grid of described 4th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, separately
One connects primary nodal point；
The grid of described 5th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, separately
One connects secondary nodal point；
The grid of described 6th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, separately
One connects the first scanning impulse outfan；
The conduction level of the 4th transistor, the 5th transistor and the 6th transistor is the first level.
Further, described first output module includes the 7th transistor and the first electric capacity；
The grid of described 7th transistor connects connection first clock signal in primary nodal point, source electrode and drain electrode
Holding, another connects the first scanning impulse outfan, and conduction level is the first level.
Further, described second output module includes the 8th transistor and the second electric capacity；
The grid of described 8th transistor connects a connection second clock signal in secondary nodal point, source electrode and drain electrode
Holding, another connects the second scanning impulse outfan, and conduction level is the first level.
Further, described 3rd node control module, including the 9th transistor, the tenth transistor, the 11st transistor
With the tenth two-transistor；
The grid of the 9th transistor and the tenth transistor connects primary nodal point；In the source electrode of the 9th transistor and drain electrode one
Individual connection the first voltage end, another connects the 3rd node；A connection the first electricity in the source electrode of the tenth transistor and drain electrode
Pressure side, another connects the 5th node；
The grid of the 11st transistor connects connection second voltage end in the 5th node, source electrode and drain electrode, another
Individual connection the 3rd node；
The grid of the tenth two-transistor connects connection second voltage end in the second voltage end, source electrode and drain electrode, separately
One connects the 5th node；
The conduction level of the 9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor is the first electricity
Flat.
Further, described 3rd reseting module includes the 13rd transistor, the 14th transistor and the 15th transistor；
The grid of described 13rd transistor connects connection first scanning impulse in fourth node, source electrode and drain electrode
Outfan, another connects the first voltage end, and conduction level is the first level；
The grid of described 14th transistor connects a connection primary nodal point in fourth node, source electrode and drain electrode, separately
One connects the first voltage end, and conduction level is the first level；
The grid of described 15th transistor connects a connection secondary nodal point in fourth node, source electrode and drain electrode, separately
One connects the first voltage end；
The conduction level of the 13rd transistor, the 14th transistor and the 15th transistor is the first level.
Further, described fourth node control module, including the 16th transistor, the 17th transistor, the 18th crystalline substance
Body pipe, the 19th transistor and the 20th transistor；
The grid of described 20th transistor and the 16th transistor connects the 3rd node；The source electrode of the 20th transistor and
Connection first voltage end in drain electrode, another connects fourth node；In the source electrode of the 16th transistor and drain electrode one
Individual connection the first voltage end, another connects the 6th node；
The grid of the 17th transistor connects a connection tertiary voltage end in the 6th node, source electrode and drain electrode, another
Individual connection fourth node；
The grid of the 18th transistor connects a connection tertiary voltage end in tertiary voltage end, source electrode and drain electrode, separately
One connects fourth node；
The grid of the 19th transistor connects connection first voltage end in primary nodal point, source electrode and drain electrode, another
Individual connection fourth node；
Leading of 16th transistor, the 17th transistor, the 18th transistor, the 19th transistor and the 20th transistor
Energising average out to the first level.
Further, described 4th reseting module includes the 21st transistor, the grid of described 21st transistor
Connecting connection the 3rd node in fourth node, source electrode and drain electrode, another connects the first voltage end.
Further, described first level is high level, and described second electrical level is low level.
Second aspect, the invention provides a kind of gate driver circuit, including:
The shift register cell of multiple cascades；Described shift register cell is the shift LD described in any of the above-described item
Device unit and a plurality of driving line；
First clock signal terminal of each shift register cell of odd level is all connected with the first driving line, and second clock is believed
Number end connect second driving line；First clock signal terminal of each shift register cell of even level connects the 3rd driving line,
Second clock signal end connects 4 wheel driven moving-wire；
Second scanning impulse outfan of the upper level shift register cell in the shift register cell of adjacent two-stage
Connect the scanning impulse input of next stage shift register cell；Second scanning impulse of next stage shift register cell is defeated
Go out end and connect the reseting controling end of upper level shift register cell.
The third aspect, the invention provides a kind of method driving gate driver circuit described above, it is characterised in that
Including: at the first voltage end input second electrical level DC voltage of each shift register cell；
Drive line to input the first clock signal first, drive line input second clock signal second；Drive the 3rd
Line input the 3rd clock signal, inputs the 4th clock signal at 4 wheel driven moving-wire；
Scanning impulse input at first order shift register cell inputs initial sweep pulse；Described initial sweep arteries and veins
The level of punching is the first level；
Wherein, the first clock signal, second clock signal, the 3rd clock signal and the clock cycle phase of the 4th clock signal
With；Wherein, the voltage of the first level in the first clock signal and the 3rd clock signal is multistage；First clock signal and the 3rd
The dutycycle of clock signal is 1/2, and level state is the most contrary；Second clock signal and the dutycycle of the 4th clock signal
It is 1/2, and level state is the most contrary；In second clock signal in the initial time of the first level and the first clock signal
The initial time of one level is identical, the first level in the initial time of the first level and the 3rd clock signal in the 4th clock signal
Initial time identical；
The initial time of first level in the initial time of initial sweep pulse and the 3rd clock signal is identical, knot
The bundle moment is identical with the finish time of this first level.
Fourth aspect, the invention provides a kind of display device, including: substrate and be formed at suprabasil raster data model
Circuit and a plurality of grid line；Wherein, gate driver circuit is gate driver circuit described above, every one-level shift register list
First scanning impulse outfan of unit connects a grid line.
In the shift register cell that the present invention provides, it is provided with two output modules；Two output modules pass through respectively
The scanning impulse that different scanning impulse outfan output is corresponding；Cut accordingly even when be set to have by one of them scanning impulse
The scanning impulse at angle, it is nonetheless possible to use next stage shift register cell is driven by another scanning impulse；Will not reduce
Driving force to next stage shift register cell.It addition, the present invention arranges two input modules；One input module will
Can conduct scanning impulse to primary nodal point, scanning impulse can be passed to secondary nodal point by another input module；And
One output module can export scanning impulse according to primary nodal point, and another output module can be swept according to secondary nodal point output
Retouch pulse；The process of the output scanning impulse of two such output module will not influence each other, and can avoid further wherein
The impact on another scanning impulse of the scanning impulse of one top rake, and then avoid impact to next stage shift register cell
Driving force.
Accompanying drawing explanation
By inventive feature information and advantage can be more clearly understood from reference to accompanying drawing, accompanying drawing be schematic and not
It is interpreted as the present invention is carried out any restriction, in the accompanying drawings:
The structural representation of a kind of shift register cell that Fig. 1 provides for the present invention；
The structural representation of the structural representation of a kind of gate driver circuit that Fig. 2 provides for the present invention；
Fig. 3 is to part signal in the driving method of the gate driver circuit in Fig. 2 and the potential diagram of node；
The structural representation of a kind of shift register cell that Fig. 4 provides for the present invention；
The structural representation of the structural representation of another gate driver circuit that Fig. 5 provides for the present invention；
Fig. 6 is to comprising in Fig. 4 part signal and joint in the driving method of the gate driver circuit of shift register cell
The potential diagram of point；
Fig. 7 a, Fig. 7 b and Fig. 7 c are the circuit diagram of a kind of shift register cell in Fig. 4.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, real with concrete below in conjunction with the accompanying drawings
The present invention is further described in detail by mode of executing.It should be noted that in the case of not conflicting, the enforcement of the application
Feature in example and embodiment can be mutually combined.
A kind of structure of the shift register cell of the present invention may refer to Fig. 1, this shift register cell SR include as
Lower structure:
First input module 10, connects primary nodal point N1 and scanning impulse input INPUT, for inputting at scanning impulse
When end INPUT is the first level, primary nodal point N1 is set to the first level；
Second input module 20, connects secondary nodal point N2 and scanning impulse input INPUT, for inputting at scanning impulse
When end INPUT is the first level, secondary nodal point N2 is set to the first level；
First output module 30, connects primary nodal point N1, the first scanning impulse outfan OUTPUT1 and the first clock signal
End CLK；For when primary nodal point N1 is the first level, by the first scanning impulse outfan OUTPUT1 and the first clock signal
End CLK conducting；When primary nodal point N1 suspends, maintain the electric charge of primary nodal point N1, at the first scanning impulse outfan OUTPUT1
During suspension (floating), maintain the electric charge of the first scanning impulse outfan OUTPUT1；
Second output module 40, connects secondary nodal point N2, the second scanning impulse outfan OUTPUT2 and second clock signal
End CLK_L；For when secondary nodal point N2 is the first level, the second scanning impulse outfan OUTPUT2 is believed with second clock
Number end CLK_L conducting；When secondary nodal point N2 suspends, maintain the electric charge of secondary nodal point N2, at the second scanning impulse outfan
When OUTPUT2 suspends, maintain the electric charge of the second scanning impulse outfan OUTPUT2；
First reseting module 50, connects primary nodal point N1, reseting controling end RESET and the first voltage end V1, for multiple
When position control end RESET is the first level, primary nodal point N1 and the first voltage end VSS is turned on；
Second reseting module 60, connects primary nodal point N1, secondary nodal point N2, the 3rd node N4, the first scanning impulse output
End OUTPUT1 and the first voltage end VSS, for when the 3rd node N3 is the first level, by primary nodal point N1, secondary nodal point N2
Turn on the first scanning impulse outfan OUTPUT1 and the first voltage end VSS；
3rd node control module 70, connects the first voltage end VSS, the second voltage end GCH_o, primary nodal point N1 and the 3rd
Node N3, for when primary nodal point N1 is the first level, is set to the level of the first voltage end VSS by the 3rd node N3；?
One node N1 is second electrical level and time the second voltage end GCH_e is the first level, and the 3rd node N3 is set to the first level.
The gate driver circuit GOA comprising the shift register cell in Fig. 1 is referred to Fig. 2, (assumes that N is including N level
Even number) shift register cell；For the ease of distinguishing, m level shift register cell therein is referred to as SR (m)；See
Fig. 2, for the shift register cell of any two-stage neighboring, such as first order shift register cell SR (1) and the second level are moved
Bit register cell S R (2)；Wherein the second scanning impulse outfan OUTPUT2 of upper level shift register cell SR (1) is even
Meet the scanning impulse input INPUT of next stage shift register cell SR (2)；Next stage shift register cell SR (2)
Second scanning impulse outfan OUTPUT2 connects the reseting controling end RESET of upper level shift register cell SR (1)；It addition,
The shift register cell of each odd level, such as first order shift register cell SR (1) and penultimate stage shift LD
First clock signal terminal CLK of device cell S R (N-1) is the most connected, is all connected with the first clock cable CLK1, second clock signal
CLK_L is the most connected for end, is all connected with second clock holding wire CLK2；And the shift register cell of each even level, such as
First clock signal terminal CLK of one-level shift register cell SR (2) and penultimate stage shift register cell SR (N) is homogeneous
Even, being all connected with the 3rd clock cable CLK3, signal end CLK_L is the most connected for second clock, is all connected with the 4th clock cable
CLK4。
The shift register cell of present invention offer and gate driver circuit, can export two relatively independent pulses,
Such that it is able to use another scanning impulse that next stage shift register cell is driven；Will not reduce and next stage is shifted
The driving force of register cell.It addition, the process of the output scanning impulse of two output modules will not influence each other, Ke Yijin
One step avoids the impact on another scanning impulse of the scanning impulse on one of them top rake, and then avoids affecting next stage shifting
The driving force of bit register unit.
Below in conjunction with Fig. 3 to the one of which driving method of the gate driver circuit shown in Fig. 2 and its realize its function
Principle illustrate.See Fig. 3, it is assumed that the first level here is high level, then corresponding second electrical level is low level.Should
Method can specifically include:
The first voltage end input second electrical level DC voltage at each shift register cell；
The first level direct voltage is inputted at the second voltage end GCH_o of each shift register cell；
First drive line CLK1 input the first clock signal clk 1 (for the ease of describing, will be defeated on each driving line
The symbol that the clock signal entered is identical with this driving line employing represents), drive line CLK2 to input second clock signal second
CLK2；Drive line CLK3 to input the 3rd clock signal clk 3 the 3rd, input the 4th clock signal at 4 wheel driven moving-wire CLK4
CLK4；
Initial sweep pulse STV is inputted at the scanning impulse input INPUT of first order shift register cell SR (1)；
The level of described initial sweep pulse STV is the first level；
Wherein, the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 and the 4th clock signal
The clock cycle of CLK4 is identical；Wherein, the voltage of the first level in the first clock signal clk 1 and the 3rd clock signal clk 3
For multistage, the voltage of the first level in second clock signal CLK2 and the 4th clock signal clk 4 is steady state value；First clock
The dutycycle of signal CLK1 and the 3rd clock signal clk 3 is 1/2, and level state is the most contrary；Second clock signal CLK2
It is 1/2 with the dutycycle of the 4th clock signal clk 4, and level state is the most contrary；First electricity in second clock signal CLK2
In flat initial time and the first clock signal clk 1, the initial time of the first level is identical, in the 4th clock signal clk 4 first
In the initial time of level and the 3rd clock signal clk 3, the initial time of the first level is identical；
The initial time of first level in the initial time of initial sweep pulse STV and the 3rd clock signal clk 3
Identical, finish time is identical with the finish time of this first level.
See Fig. 3, for first order shift register cell SR (1), at first stage S1, initial sweep pulse STV be
First level, the most now primary nodal point N1 and secondary nodal point N2 is set to by the first input module 10 and the second input module 20 respectively
First level, now the first clock signal terminal CLK and the first scanning impulse outfan OUTPUT1 conducting, second clock signal end
CLK_L and the second scanning impulse outfan OUTPUT2 conducting；Due to the driving line that now the first clock signal terminal CLK is connected
CLK1 and and the driving line CLK2 that connected of second clock signal end CLK_L be second electrical level, then the first scanning impulse is defeated
Enter to hold OUTPUT1 and the second scanning impulse outfan OUTPUT2 to be second electrical level；Additionally, due to first order shift register list
Second scanning impulse outfan of second level shift register cell SR (2) that the reseting controling end RESET of unit SR (1) connects
OUTPUT2 is second electrical level, and the most now the reseting controling end RESET of first order shift register cell SR (1) is second electrical level；
It addition, for first order shift register cell SR (1), owing to primary nodal point N1 is the first level, then the second reseting module 60
The level of the 3rd node N3 and the level of the first voltage end VSS is made to keep consistent, for second electrical level；
See also Fig. 3, for first order shift register cell SR (1), in second stage S2, node N1 and N2 continues
It is maintained the first level；First clock signal terminal CLK and the first scanning impulse outfan OUTPUT1 continues conducting, second clock
Signal end CLK_B and the second scanning impulse outfan OUTPUT2 continues conducting；First drives line CLK1 and second to drive line CLK2
Being the first level, corresponding first clock signal terminal CLK and second clock signal end CLK_L is also the first level；Make
First scanning impulse outfan OUTPUT1 and the second scanning impulse outfan OUTPUT2 starts to export the scanning arteries and veins of the first level
Punching；And in this stage, the waveform of the scanning impulse that the first scanning impulse outfan OUTPUT1 is exported and the first clock signal
CLK1 keeps consistent, is two rank voltages；The waveform of the scanning impulse that the second scanning impulse outfan OUTPUT2 is exported and
Two clock signal clks 2 keep consistent, and voltage therein is steady state value；It addition, in first order shift register cell SR (1), multiple
Position controls end RESET and is maintained second electrical level, and the 3rd node N3 is also maintained second electrical level；
In second stage S2, for second level shift register cell SR (2), and each terminal (includes two clock letters
Number end CLK and CLK_B, scanning impulse input INPUT and reseting controling end RESET) with first order shift register cell SR
(1) situation of the signal being transfused at first stage S1 is consistent, therefore each joint in second level shift register cell SR (2)
Current potential situation and first order shift register cell SR (1) of point and scanning impulse outfan is in the current potential feelings of first stage S1
Condition is completely the same, no longer describes in detail at this.
At phase III S3, for second level shift register cell SR (2), and each terminal (includes two clock letters
Number end CLK and CLK_B, scanning impulse input INPUT and reseting controling end RESET) with first order shift register cell SR
(1) situation of the signal being transfused in second stage S2 is consistent, therefore also by the first scanning impulse outfan OUTPUT1 and
The scanning impulse that second scanning impulse outfan OUTPUT2 output is corresponding；
At phase III S3, for first order shift register cell SR (1), its reseting controling end RESET is connected
Second scanning impulse outfan OUTPUT2 of second level shift register cell SR (2) is the first level, and the most now first resets
Primary nodal point N1 and the first voltage end VSS is turned on by module 50, and primary nodal point N is set to second electrical level；So further result in
3rd node N3 is set to the level of the second voltage end GCH_e, the i.e. first level by the 3rd node control module 70；And the 3rd node
N3 is set to the first level, can further result in again primary nodal point N1, secondary nodal point N2 and the first voltage end VSS conducting, it is achieved
To primary nodal point and the reset of secondary nodal point N2, and it is further ensured that primary nodal point N1 is maintained second electrical level；In this stage
Afterwards, until the scanning impulse input INPUT of first order shift register cell SR (1) be again set to the first level it
Before, the primary nodal point N1 in first order shift register cell SR (1) is all maintained second electrical level, corresponding secondary nodal point N1,
3rd node N3 is the most all maintained the first level；
In fourth stage S4, for second level shift register cell SR (2), and each terminal (includes two clock letters
Number end CLK and CLK_B, scanning impulse input INPUT and reseting controling end RESET and the first scanning impulse outfan
OUTPUT1 and the second scanning impulse outfan OUTPUT2) with first order shift register cell SR (1) phase III S3's
Situation is consistent, no longer illustrates at this.
Being not difficult to find out from above-mentioned driving process, for the shift register cell of adjacent two-stage, rear stage shifts
Each terminal of register cell is state and upper level shift register cell each of the signal received by the current generation
Individual terminal is completely the same at the potential state of signal received on last stage, so according to the description above it is known that
Shift register cells at different levels can be sequentially output multiple scanning impulse.
It is pointed out that the driving method shown in Fig. 3 is only that in Fig. 2, the one of the gate driver circuit of offer may
Driving method, in actual applications, corresponding driving method is not limited to the form shown in Fig. 3.
In the specific implementation, in addition to the basic structure shown by the shift register cell shown in Fig. 1, the present invention
The shift register cell provided can also comprise other structures, with further improving performance, sees Fig. 4, for another embodiment
The structural representation of the shift register cell provided；In addition to the modules shown in Fig. 1, also include the 3rd reset mould
Block 80, fourth node control module 90；4th reseting module 100；
Wherein, the 3rd reseting module 80, connect primary nodal point N1, fourth node N4, the first scanning impulse outfan
OUTPUT1 and the first voltage end VSS, for when fourth node N4 is the first level, by primary nodal point N1 and first scanning arteries and veins
Rush outfan and the first voltage end VSS conducting；
Fourth node control module 90, connects primary nodal point N1, the 3rd node N3, fourth node N4, the first voltage end VSS
With tertiary voltage end GCH_O, for any node in primary nodal point N1 and the 3rd node N3 be the first level time, by the 4th
Node N4 is set to the level of the first voltage end VSS；It is second electrical level and tertiary voltage at primary nodal point N1 and the 3rd node N3
When end is the first level, fourth node N4 is set to the first level.
The benefit arranging the 3rd reseting module 80 and fourth node control module 90 it is possible to by the 3rd reseting module 80
With what the second reseting module 60 replaced, primary nodal point N1, secondary nodal point N2 and the first scanning impulse outfan OUTPUT1 are entered
The lasting reset of row, it is to avoid apply the 3rd reseting module 80 for a long time to be used for make the 3rd reseting module 80 to primary nodal point N1,
Secondary nodal point N2 and the first scanning impulse outfan OUTPUT1 carries out the signal resetted, it is to avoid the property of the 3rd reseting module 80
Can reduce.
The structural representation of the gate driver circuit comprising the shift register cell in Fig. 4 may refer to Fig. 5, with Fig. 2
Except for the difference that, each shift register cell SR also has tertiary voltage end GCH_e；The 3rd of each shift register cell SR
Voltage end GCH_e is connected with each other.
A kind of driving method and its operation principle of 6 gate driver circuits to comprising Fig. 5 is carried out below in conjunction with the accompanying drawings
Explanation.In Fig. 6, it is also assumed that the first level is high level, second electrical level is low level；See shown in Fig. 6 from Fig. 3 is different
, in the method, at the second voltage end GCH_e and tertiary voltage end GCH_o applying the first level alternately；So first
After node N1 is set to low level, when the second voltage end GCH_e is the first level, the 3rd node N3 is the first level, makes
Obtain the second reseting module 60 and open reset function, to primary nodal point N1, secondary nodal point N2 and the first scanning impulse outfan
OUTPUT1 resets；When the second voltage end GCH_e is second electrical level, the 3rd node N3 is second electrical level, now Section four
Fourth node N4 is set to the level of tertiary voltage end GCH_o by point control module 90, is the first level；So that the 3rd is multiple
Position module 80 opens reset function, carries out primary nodal point N1, secondary nodal point N2 and the first scanning impulse outfan OUTPUT1
Reset.Thus achieve alternately by the 3rd reseting module 80 and the second reseting module 60 to primary nodal point N1, second section
Point N2 and the first scanning impulse outfan OUTPUT1 carries out the function resetted.
From the description above it is known that just in order to realize alternately by the 3rd reseting module 80 and the second reseting module
For 60 realize the functions resetted, the 4th reseting module 100 here is it is not necessary to the structure that arranges.
4th reseting module 100, connects the 3rd node N3, fourth node N4 and the first voltage end VSS, at Section four
When point N4 is the first level, the 3rd node N3 and the first voltage end VSS is turned on.
Arrange the benefit of the 4th reseting module 100 be can fourth node N4 when being the first level, by the 3rd node N3 quilt
It is set to second electrical level, thus preferably closes the reset function of the second reseting module 60.
From the description above it is known that on the premise of the function being capable of correspondence, each functional module is concrete such as
What design does not interferes with protection scope of the present invention.Below some optional modes of each functional module are carried out further
Explanation.
In the specific implementation, seeing Fig. 7 a, the first input module 10 can specifically include: the first transistor T1, and first is brilliant
The grid of body pipe T1 connects connection a 4th voltage end VDD in scanning impulse input INPUT, source electrode and drain electrode, another
Individual connection primary nodal point N1, conduction level is the first level.
So can be by the first level direct voltage lasting on the 4th voltage end VDD so that when scanning impulse is defeated
When entering to hold INPUT to be applied in the first level, the first transistor T1 can be caused to turn on, the level of primary nodal point N1 is set to the 4th electricity
The level of pressure side VDD, the i.e. first level, it is achieved thereby that the function of the first above-mentioned input module 10.
In the specific implementation, seeing Fig. 7 a, the second input module 20 can specifically include transistor seconds T2, the second crystal
The grid of pipe T2 connects a connection scanning impulse input INPUT in scanning impulse input INPUT, source electrode and drain electrode,
Another connects secondary nodal point N2, and conduction level is the first level.
So, when scanning impulse input INPUT is applied in the first level, transistor seconds T2 can be caused to turn on, will
The level of secondary nodal point N2 is set to the level of scanning impulse input INPUT, the i.e. first level, it is achieved thereby that above-mentioned second
The function of input module 20.
In the specific implementation, seeing Fig. 7 a, the first reseting module 50 can include third transistor T3, third transistor T3
Grid connect reseting controling end RESET, source electrode and drain electrode in one connection the first voltage end VSS, another connect first
Node N1, conduction level is the first level.
So when reseting controling end RESET is applied in the first level, third transistor T3 can be caused to turn on, by first segment
The level of some N1 is set to the level of the first voltage end VSS (can apply the DC voltage of second electrical level at the second voltage end VSS),
I.e. second electrical level, it is achieved thereby that the function of the first above-mentioned reseting module 30.
In the specific implementation, seeing Fig. 7 b, the second reseting module 60 can specifically include the 4th transistor T4, the 5th crystal
Pipe T5 and the 6th transistor T6；
The grid of the 4th transistor T4 connects a connection first voltage end VSS in the 3rd node N3, source electrode and drain electrode,
Another connects primary nodal point N1；
The grid of the 5th transistor T5 connects a connection first voltage end VSS in the 3rd node N3, source electrode and drain electrode,
Another connects secondary nodal point N2；
The grid of the 6th transistor T6 connects a connection first voltage end VSS in the 3rd node N3, source electrode and drain electrode,
Another connects the first scanning impulse outfan OUTPUT1；
4th transistor T4, the conduction level of the 5th transistor T5 and the 6th transistor T6 are the first level.
So, when the 3rd node N3 is the first level, the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6
It is both turned on, respectively primary nodal point N1, secondary nodal point N2 and the first scanning impulse outfan OUTPUT1 is set to second electrical level；Complete
The reset of paired three nodes, it is achieved that the function of the second above-mentioned reseting module 60.
In the specific implementation, seeing Fig. 7 a, the first output module 30 can specifically include the 7th transistor T7 and first electricity
Hold C1；
The grid of the 7th transistor T7 connects connection first clock signal terminal in primary nodal point N1, source electrode and drain electrode
CLK, another connects the first scanning impulse outfan OUTPUT1, and conduction level is the first level.
So when primary nodal point N1 is the first level, the 7th transistor T7 conducting can be caused, by defeated for the first scanning impulse
Go out to hold OUTPUT1 and the first clock signal terminal CLK conducting, it is achieved that the function of the first above-mentioned output module 30.
In the specific implementation, seeing Fig. 7 a, the second output module 40 can specifically include the 8th transistor T8 and second electricity
Hold C2；
The grid of the 8th transistor T8 connects a connection second clock signal end in secondary nodal point N2, source electrode and drain electrode
CLK_L, another connects the second scanning impulse outfan OUTPUT2, and conduction level is the first level.
So when secondary nodal point N2 is the first level, the 8th transistor T8 conducting can be caused, by defeated for the second scanning impulse
Go out to hold OUTPUT2 and second clock signal end CLK_L to turn on, it is achieved that the function of the second above-mentioned output module 40.
In the specific implementation, see Fig. 7 a, the 3rd node control module 70 can specifically include the 9th transistor T9, the tenth
Transistor T10, the 11st transistor T11 and the tenth two-transistor T12；
The grid of the 9th transistor T9 and the tenth transistor T10 connects primary nodal point N1；The source electrode of the 9th transistor T9 and
A connection first voltage end VSS in drain electrode, another connects the 3rd node N3；The source electrode of the tenth transistor T10 and drain electrode
In one connection the first voltage end VSS, another connects the 5th node N5；
The grid of the 11st transistor T11 connects connection second voltage end in the 5th node N5, source electrode and drain electrode
GCH_e, another connects the 3rd node N3；
The grid of the tenth two-transistor connects connection second voltage in the second voltage end GCH_e, source electrode and drain electrode
End GCH_e, another connects the 5th node N5；
9th transistor T9, the tenth transistor T10, the 11st transistor T11 and the tenth two-transistor T12.
So when primary nodal point N1 is the first level, the 9th transistor T9 and the tenth transistor T10 is both turned on, by the 5th
Node N5 and the 3rd node N3 turns on the first voltage end VSS so that the 3rd node N3 is set to second electrical level；Work as first segment
When point N1 is second electrical level, the 9th transistor T9 and the tenth transistor T10 is turned off, and now leads due to the tenth two-transistor T12
Logical, the level that the 5th node N5 can be set to the second voltage end GCH_e (now can apply the on the second voltage end GCH_e
One level) so that the 5th node N5 is set to the first level, and then makes the 11st transistor T11 conducting, by the 3rd node N3
It is set to the first level.Thus achieve the function of the 3rd above-mentioned node control module 70
See Fig. 7 c, in the specific implementation, the 3rd reseting module 80 can specifically include the 13rd transistor T13, the tenth
Four transistor T14 and the 15th transistor T15；
The grid of the 13rd transistor T13 connects a connection the first scanning arteries and veins in fourth node N4, source electrode and drain electrode
Rushing outfan OUTPUT1, another connects the first voltage end VSS, and conduction level is the first level；
The grid of the 14th transistor connects a connection primary nodal point N1 in fourth node N4, source electrode and drain electrode, separately
One connects the first voltage end VSS, and conduction level is the first level；
The grid of the 15th transistor connects a connection secondary nodal point N2 in fourth node, source electrode and drain electrode, another
Individual connection the first voltage end VSS.
When fourth node N4 is the first level, the 13rd transistor T13, the 14th transistor T14 and the 15th crystal
Pipe T15 is both turned on, by primary nodal point N1, secondary nodal point N2 and the first scanning impulse outfan OUTPUT1 and the first voltage end VSS
Conducting so that three nodes are set to second electrical level, thus achieve the function of the 3rd above-mentioned reseting module 80.
See Fig. 7 a, in the specific implementation, fourth node control module 90, can specifically include the 16th transistor T16,
17th transistor T17, the 18th transistor T18, the 19th transistor T19 and the 20th transistor T20；
The grid of the 20th transistor T20 and the 16th transistor T16 connects the 3rd node N3；20th transistor T20
Source electrode and drain electrode in one connection the first voltage end VSS, another connects fourth node N4；16th transistor T16's
A connection first voltage end VSS in source electrode and drain electrode, another connects the 6th node N6；
The grid of the 17th transistor connects a connection tertiary voltage end GCH_ in the 6th node N6, source electrode and drain electrode
O, another connects fourth node N4；
The grid of the 18th transistor T18 connects a connection the 3rd electricity in tertiary voltage end GCH_o, source electrode and drain electrode
Pressure side GCH_o, another connects fourth node N4；
The grid of the 19th transistor T19 connects connection first voltage end in primary nodal point N1, source electrode and drain electrode
VSS, another connects fourth node N4；
16th transistor T16, the 17th transistor T17, the 18th transistor T18, the 19th transistor T19 and second
The conduction level of ten transistor T20 is the first level.
So when primary nodal point N1 is the first level, the 19th transistor T19 conducting, by fourth node N4 and the first electricity
Pressure side VSS turns on so that fourth node N4 is set to second electrical level；And when the 3rd node N3 is the first level, the 20th is brilliant
Body pipe T20 and the 16th transistor T16 is both turned on so that the 6th node N6 and fourth node N4 are all set to the first level；When
When primary nodal point N1 and the 3rd node N3 is second electrical level, the 20th transistor T20 and the 16th transistor T16 and the tenth
Nine transistor T19 are turned off；Now the 17th transistor T17 conducting (in the specific implementation, now can apply on GCH_o
First level) so that the 6th node N6 is set to the first level, and then causes the 18th transistor T18 conducting, by fourth node
N4 is set to the first level.Thus achieve the function of above-mentioned fourth node control module 90.
In the specific implementation, seeing Fig. 7, the 4th reseting module 100 can specifically include the 21st transistor T21, the
The grid of 21 transistor T21 connects connection a 3rd node N3 in fourth node N4, source electrode and drain electrode, and another is even
Meet the first voltage end VSS.
So, when fourth node N4 is the first level, can make, by the 21st transistor T21 conducting, by Section three
Point N3 and the first voltage end VSS conducting, is set to second electrical level.So tool achieves the function of the 4th reseting module 100.
In the detailed description of the invention of above-mentioned cited modules, the transistor that modules is comprised is conducting
Electricity is the transistor of the first level, so can be made by identical technique, it is possible to reduce manufacture difficulty.
Another further aspect, present invention also offers a kind of display device, including substrate and be formed at suprabasil grid and drive
Galvanic electricity road and a plurality of grid line；Wherein, gate driver circuit is the gate driver circuit described in any of the above-described item, and every one-level shifts
First scanning impulse outfan of register cell connects a grid line.
Here display device can be: Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, number
Any product with display function or the parts such as code-phase frame, navigator.
In description mentioned herein, illustrate a large amount of detail.It is to be appreciated, however, that the enforcement of the present invention
Example can be put into practice in the case of not having these details.In some instances, it is not shown specifically known method, structure
And technology, in order to do not obscure the understanding of this description.
Last it is noted that above example is only in order to illustrate technical scheme, it is not intended to limit；Although
With reference to previous embodiment, the present invention is described in detail, it will be understood by those within the art that: it still may be used
So that the technical scheme described in foregoing embodiments to be modified, or wherein portion of techniques feature is carried out equivalent；
And these amendment or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (17)
1. a shift register cell, it is characterised in that including:
First input module, connects primary nodal point and scanning impulse input, and being used at scanning impulse input is the first level
Time, primary nodal point is set to the first level；
Second input module, connects secondary nodal point and scanning impulse input, and being used at scanning impulse input is the first level
Time, secondary nodal point is set to the first level；
First output module, connects primary nodal point, the first scanning impulse outfan and the first clock signal terminal；For at first segment
When point is the first level, the first scanning impulse outfan and the first clock signal terminal are turned on；When primary nodal point suspends, maintain
The electric charge of primary nodal point, when the first scanning impulse outfan suspends, maintains the electric charge of the first scanning impulse outfan；
Second output module, connects secondary nodal point, the second scanning impulse outfan and second clock signal end；For at second section
When point is the first level, the second scanning impulse outfan is turned on second clock signal end；When secondary nodal point suspends, maintain
The electric charge of secondary nodal point, when the second scanning impulse outfan suspends, maintains the electric charge of the second scanning impulse outfan；
First reseting module, connects primary nodal point, reseting controling end and the first voltage end, and being used at reseting controling end is the first electricity
At ordinary times, primary nodal point and the first voltage end are turned on；
Second reseting module, connects primary nodal point, secondary nodal point, the 3rd node, the first scanning impulse outfan and the first voltage
End, for when the 3rd node is the first level, by primary nodal point, secondary nodal point and the first scanning impulse outfan and the first electricity
Pressure side turns on；
3rd node control module, connects the first voltage end, the second voltage end, primary nodal point and the 3rd node, for first
When node is the first level, the 3rd node is set to the level of the first voltage end；It is second electrical level and the second electricity at primary nodal point
When pressure side is the first level, the 3rd node is set to the first level.
Shift register cell the most according to claim 1, it is characterised in that also include: the 3rd reseting module, connects the
One node, secondary nodal point, fourth node, the first scanning impulse outfan and the first voltage end, being used in fourth node is first
During level, primary nodal point, secondary nodal point and the first scanning impulse outfan and the first voltage end are turned on；
Fourth node control module, connects primary nodal point, the 3rd node, fourth node, the first voltage end and tertiary voltage end, uses
When any node in primary nodal point and the 3rd node is the first level, fourth node is set to the electricity of the first voltage end
Flat；When primary nodal point and the 3rd node are second electrical level and tertiary voltage end is the first level, fourth node is set to
One level.
Shift register cell the most according to claim 2, it is characterised in that also include the 4th reseting module, described
Four reseting modules connect the 3rd node, fourth node and the first voltage end, for when fourth node is the first level, by the 3rd
Node and the conducting of the first voltage end.
Shift register cell the most according to claim 1, it is characterised in that described first input module includes that first is brilliant
Body pipe, the grid of described the first transistor connects connection the 4th voltage end in scanning impulse input, source electrode and drain electrode,
Another connects primary nodal point, and conduction level is the first level.
Shift register cell the most according to claim 1, it is characterised in that described second input module includes that second is brilliant
Body pipe, the connection scanning impulse that the grid of described transistor seconds connects in scanning impulse input, source electrode and drain electrode is defeated
Entering end, another connects secondary nodal point, and conduction level is the first level.
Shift register cell the most according to claim 1, it is characterised in that described first reseting module includes that is trimorphism
Body pipe, the grid of described third transistor connects connection first voltage end in reseting controling end, source electrode and drain electrode, another
Individual connection primary nodal point, conduction level is the first level.
Shift register cell the most according to claim 1, it is characterised in that described second reseting module includes that the 4th is brilliant
Body pipe, the 5th transistor and the 6th transistor；
The grid of described 4th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, another
Connect primary nodal point；
The grid of described 5th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, another
Connect secondary nodal point；
The grid of described 6th transistor connects connection first voltage end in the 3rd node, source electrode and drain electrode, another
Connect the first scanning impulse outfan；
The conduction level of the 4th transistor, the 5th transistor and the 6th transistor is the first level.
Shift register cell the most according to claim 1, it is characterised in that described first output module includes that the 7th is brilliant
Body pipe and the first electric capacity；
The grid of described 7th transistor connects connection first clock signal terminal in primary nodal point, source electrode and drain electrode, separately
One connects the first scanning impulse outfan, and conduction level is the first level.
Shift register cell the most according to claim 1, it is characterised in that described second output module includes that the 8th is brilliant
Body pipe and the second electric capacity；
The grid of described 8th transistor connects a connection second clock signal end in secondary nodal point, source electrode and drain electrode, separately
One connects the second scanning impulse outfan, and conduction level is the first level.
Shift register cell the most according to claim 1, it is characterised in that described 3rd node control module, including
9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；
The grid of the 9th transistor and the tenth transistor connects primary nodal point；A company in the source electrode of the 9th transistor and drain electrode
Connecing the first voltage end, another connects the 3rd node；Connection first voltage end in the source electrode of the tenth transistor and drain electrode,
Another connects the 5th node；
The grid of the 11st transistor connects connection second voltage end in the 5th node, source electrode and drain electrode, and another is even
Connect the 3rd node；
The grid of the tenth two-transistor connects connection second voltage end in the second voltage end, source electrode and drain electrode, another
Connect the 5th node；
The conduction level of the 9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor is the first level.
11. shift register cells as claimed in claim 2, it is characterised in that described 3rd reseting module includes the 13rd
Transistor, the 14th transistor and the 15th transistor；
The grid of described 13rd transistor connects connection the first scanning impulse output in fourth node, source electrode and drain electrode
Holding, another connects the first voltage end, and conduction level is the first level；
The grid of described 14th transistor connects a connection primary nodal point in fourth node, source electrode and drain electrode, another
Connecting the first voltage end, conduction level is the first level；
The grid of described 15th transistor connects a connection secondary nodal point in fourth node, source electrode and drain electrode, another
Connect the first voltage end；
The conduction level of the 13rd transistor, the 14th transistor and the 15th transistor is the first level.
12. shift register cells as claimed in claim 2, it is characterised in that described fourth node control module, including
16 transistors, the 17th transistor, the 18th transistor, the 19th transistor and the 20th transistor；
The grid of described 20th transistor and the 16th transistor connects the 3rd node；The source electrode of the 20th transistor and drain electrode
In one connection the first voltage end, another connects fourth node；A company in the source electrode of the 16th transistor and drain electrode
Connecing the first voltage end, another connects the 6th node；
The grid of the 17th transistor connects a connection tertiary voltage end in the 6th node, source electrode and drain electrode, and another is even
Connect fourth node；
The grid of the 18th transistor connects a connection tertiary voltage end in tertiary voltage end, source electrode and drain electrode, another
Connect fourth node；
The grid of the 19th transistor connects connection first voltage end in primary nodal point, source electrode and drain electrode, and another is even
Connect fourth node；
16th transistor, the 17th transistor, the 18th transistor, the 19th transistor and the electric conduction of the 20th transistor
Average out to the first level.
13. shift register cells as claimed in claim 3, it is characterised in that described 4th reseting module includes the 20th
One transistor, the grid of described 21st transistor connects connection the 3rd node in fourth node, source electrode and drain electrode,
Another connects the first voltage end.
14. shift register cells as described in any one of claim 1-13, it is characterised in that described first level is high electricity
Flat, described second electrical level is low level.
15. 1 kinds of gate driver circuits, it is characterised in that including:
The shift register cell of multiple cascades；Described shift register cell is the shifting as described in any one of claim 1-14
Bit register unit and a plurality of driving line；
First clock signal terminal of each shift register cell of odd level is all connected with the first driving line, second clock signal end
Connect the second driving line；First clock signal terminal connection the 3rd driving line of each shift register cell of even level, second
Clock signal terminal connects 4 wheel driven moving-wire；
Second scanning impulse outfan of the upper level shift register cell in the shift register cell of adjacent two-stage connects
The scanning impulse input of next stage shift register cell；Second scanning impulse outfan of next stage shift register cell
Connect the reseting controling end of upper level shift register cell.
16. 1 kinds of methods driving gate driver circuit as claimed in claim 15, it is characterised in that including: move at each
First voltage end input second electrical level DC voltage of bit register unit；
Drive line to input the first clock signal first, drive line input second clock signal second；Drive line defeated the 3rd
Enter the 3rd clock signal, input the 4th clock signal at 4 wheel driven moving-wire；
Scanning impulse input at first order shift register cell inputs initial sweep pulse；Described initial sweep pulse
Level is the first level；
Wherein, the first clock signal, second clock signal, the 3rd clock signal are identical with the clock cycle of the 4th clock signal；
Wherein, the voltage of the first level in the first clock signal and the 3rd clock signal is multistage；First clock signal and when the 3rd
The dutycycle of clock signal is 1/2, and level state is the most contrary；The dutycycle of second clock signal and the 4th clock signal is equal
It is 1/2, and level state is the most contrary；In second clock signal in the initial time of the first level and the first clock signal first
The initial time of level is identical, the initial time of the first level and the first level in the 3rd clock signal in the 4th clock signal
Initial time is identical；
The initial time of first level in the initial time of initial sweep pulse and the 3rd clock signal is identical, at the end of
Carve identical with the finish time of this first level.
17. 1 kinds of display devices, it is characterised in that including: substrate and be formed at suprabasil gate driver circuit and many
Bar grid line；Wherein, gate driver circuit is gate driver circuit as claimed in claim 15, every one-level shift register cell
First scanning impulse outfan connect a grid line.
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