CN104392687A - Drive unit as well as drive method thereof, drive circuit, array substrate and display panel - Google Patents
Drive unit as well as drive method thereof, drive circuit, array substrate and display panel Download PDFInfo
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- CN104392687A CN104392687A CN201410733496.3A CN201410733496A CN104392687A CN 104392687 A CN104392687 A CN 104392687A CN 201410733496 A CN201410733496 A CN 201410733496A CN 104392687 A CN104392687 A CN 104392687A
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Abstract
The invention discloses a drive unit as well as a drive method thereof, a drive circuit, an array substrate and a display panel, wherein the drive unit comprises a latch sub unit and N scanning signal generating sub units corresponding to the latch sub unit, N is a positive integer bigger than 1; the latch sub unit is used for generating a secondary trigger signal and a first control signal in sequence according to the trigger signal and a first clock signal; the N scanning signal generating sub units are used for generating N scanning signals in sequence according to the received first control signal, the second to the (N+1)-th clock signals, wherein the (N+1)-th clock signal is used for controlling the i-th scanning signal generating sub unit to generate a scanning signal, and i is a positive integer not bigger than N. The drive unit provided by the invention not only can be used for lowering the power consumption of the drive circuit and enabling the array substrate and the display panel to easily realize narrow side frames, but also can be used for lowering the electromagnetic interferences of the clock signals for driving the drive circuit on the array substrate and the display panel.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of driver element and driving method, driving circuit, array base palte and display panel.
Background technology
Recently, along with the development of display technique, the application of display panel is also more and more extensive.When display panel works, the driving circuit being arranged in display panel will produce sweep signal, to drive each sweep trace in array base palte seriatim, makes data-signal can be transferred to each pixel cell in array base palte.Above-mentioned sweep signal is produced by the driver element in driving circuit.
Fig. 1 is the structural representation of the driver element of prior art.As shown in Figure 1, driver element comprises: latch 10, Sheffer stroke gate A8, three phase inverter be electrically connected in series (the 3rd phase inverter A3, 4th phase inverter A4 and the 5th phase inverter A5) three grades of impact dampers forming, trigger pip input end IN, first clock signal input terminal CKV1, scan clock signal input end CKV2 and output terminal GOUT, wherein, latch 10 comprises two phase inverters (the first phase inverter A1 and the second phase inverter A2) and two clocked inverters (the first clocked inverter A6 and second clock phase inverter A7), the input end of latch 10 is trigger pip input end IN and the first clock signal input terminal CKV1, the output terminal of latch 10 is as secondary trigger pip output terminal NEXT, and be electrically connected with the first input end of Sheffer stroke gate A8, its second input end is electrically connected with scan clock signal input end CKV2, the output terminal of Sheffer stroke gate A8 is electrically connected with the input end of the 3rd phase inverter A3, the output terminal of the 5th phase inverter A5 is electrically connected with the output terminal GOUT of driver element.
By above-mentioned driver element is electrically connected in series step by step and can obtains driving circuit, wherein, in arbitrary neighborhood two-stage drive unit, the display packing output terminal of a kind of novel RGBW collocation RGB backlight of the secondary trigger pip of upper level driver element is electrically connected with the trigger pip input end of next stage driver element.Above-mentioned driving circuit is applied to display panel, because each driver element only has an output terminal GOUT, the sweep signal that this output terminal GOUT exports is for scanning a horizontal scanning line, therefore, if display panel has N horizontal scanning line, the driver element just needing driving circuit at least to comprise N level to be electrically connected in series.
In prior art, for display panel, the power consumption of driving circuit occupies greatly.And driving circuit adopts the driver element shown in Fig. 1, because the quantity of the driver element needed is more, therefore make the power dissipation ratio of driving circuit larger; In addition, driving circuit is arranged on the frame region of display panel, and because the quantity of the driver element forming driving circuit is more, therefore, it is more difficult that display panel realizes narrow frameization; In addition, driving circuit operationally, because driver element at different levels provides clock signal by two clock cables to the first clock signal input terminal CKV1 and scan clock signal input end CKV2, therefore, in order to meet drive circuit works, the frequency of two clock signals is higher, and particularly along with the resolution of display panel improves, electromagnetic interference (EMI) can be larger.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of driver element and driving method, driving circuit, array base palte and display panel, to solve the technical matters existed in above-mentioned prior art.
First aspect, the embodiment of the present invention provides a kind of driver element, comprising: latch subelement, and the N number of sweep signal generating subunit corresponding with described latch subelement, N be greater than 1 positive integer, wherein,
Described latch subelement is used for producing secondary trigger pip and the first control signal according to trigger pip and the first clock signal, and described latch subelement comprises trigger pip input end, the first clock signal input terminal, secondary trigger pip output terminal and the first control signal output terminal;
Described first control signal and second that described N number of sweep signal generating subunit is used for according to receiving produces N number of sweep signal successively to N+1 clock signal, wherein, described i-th+1 clock signal produces sweep signal for controlling i-th sweep signal generating subunit, i is the positive integer being not more than N, and each described sweep signal generating subunit comprises the first control signal input end, scan clock signal input end and sweep signal output terminal;
First control signal input end of described N number of sweep signal generating subunit of the first control signal output terminal electrical connection correspondence of described latch subelement.
Second aspect, the embodiment of the present invention also provides a kind of driving method of driver element, and described driving method is performed by the driver element described in above-mentioned first aspect, and described driving method comprises:
Latch subelement and produce secondary trigger pip and the first control signal according to trigger pip and the first clock signal;
I-th sweep signal generating subunit produces sweep signal corresponding to described i-th sweep signal generating subunit successively according to described first control signal received and the i-th+1 clock signal, until all sweep signal generating subunit drive complete.
The third aspect, the embodiment of the present invention also provides a kind of driving circuit, comprise the driver element described in above-mentioned first aspect of plural serial stage electrical connection, wherein, in arbitrary neighborhood two-stage drive unit, the secondary trigger pip output terminal of upper level driver element is electrically connected with the trigger pip input end of next stage driver element.
Fourth aspect, the embodiment of the present invention also provides a kind of array base palte, comprise a plurality of data lines, multi-strip scanning line and intersect by described a plurality of data lines and multi-strip scanning line the multiple pixel cells limited, the pixel electrode that wherein said pixel cell comprises thin film transistor (TFT) and is connected electrically, also comprise the driving circuit described in the above-mentioned third aspect, wherein, each sweep signal output terminal of the sweep signal generating subunit in described driving circuit is electrically connected a sweep trace.
5th aspect, the embodiment of the present invention also provides a kind of display panel, comprises the array base palte described in above-mentioned fourth aspect.
The driver element that the embodiment of the present invention provides and driving method thereof, driving circuit, array base palte and display panel, subelement is latched and the N number of sweep signal generating subunit corresponding with latching subelement by arranging in the driving unit, N be greater than 1 positive integer, wherein each sweep signal generating subunit can produce a sweep signal, due to one latch subelement can a driving N sweep signal generating subunit produce N number of sweep signal, therefore, so not only can reduce the power consumption of the driving circuit of this driver element of application, the space that driving circuit takies can also be reduced, thus the array base palte of this driving circuit of application and display panel can be made easily to realize narrow frame, in addition, driving circuit is driven to N+1 clock signal by the first clock signal and second, namely driven by N+1 clock signal, therefore, when grid circuit works, the frequency of clock signal can be reduced, thus the electromagnetic interference (EMI) of clock signal array substrate and display panel generation can be reduced.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the structural representation of the driver element of prior art;
Fig. 2 is the structural representation of a kind of driver element that the embodiment of the present invention provides;
Fig. 3 a is a kind of electrical block diagram latching subelement that the embodiment of the present invention provides;
Fig. 3 b is the sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal;
Fig. 4 a is the electrical block diagram of a kind of sweep signal generating subunit that the embodiment of the present invention provides;
Fig. 4 b is the sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 4 a;
Fig. 4 c is the electrical block diagram of the another kind of sweep signal generating subunit that the embodiment of the present invention provides;
Fig. 4 d is the electrical block diagram of another sweep signal generating subunit that the embodiment of the present invention provides;
Fig. 5 a is the electrical block diagram of a kind of driver element that the embodiment of the present invention provides;
Fig. 5 b is the sequential chart of the input signal of each input end in Fig. 5 a and the output signal of each output terminal;
Fig. 6 is the schematic flow sheet of the driving method of a kind of driver element that the embodiment of the present invention provides;
Fig. 7 a is the structural representation of a kind of driving circuit that the embodiment of the present invention provides;
Fig. 7 b is the structural representation of a kind of embodiment of driving circuit in Fig. 7 a;
Fig. 7 c is the sequential chart of the input signal of each input end of driving circuit in Fig. 7 b and the output signal of each output terminal;
Fig. 8 is the structural representation of a kind of array base palte that the embodiment of the present invention provides;
Fig. 9 is the structural representation of a kind of display panel that the embodiment of the present invention provides.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
The embodiment of the present invention provides a kind of driver element.Fig. 2 is the structural representation of a kind of driver element that the embodiment of the present invention provides.As shown in Figure 2, described driver element comprises: latch subelement 21, and the N number of sweep signal generating subunit corresponding with described latch subelement 21 (corresponding to the first sweep signal generating subunit 221 to the N sweep signal generating subunit 22N in the drawings), N be greater than 1 positive integer, wherein, described latch subelement 21 is for producing secondary trigger pip and the first control signal according to trigger pip and the first clock signal, described latch subelement 21 comprises trigger pip input end STV, first clock signal input terminal CKV1, secondary trigger pip output terminal NEXT and the first control signal output terminal GTV, described first control signal and second that described N number of sweep signal generating subunit is used for according to receiving produces N number of sweep signal successively to N+1 clock signal, wherein, described i-th+1 clock signal produces sweep signal for controlling i-th sweep signal generating subunit, i is the positive integer being not more than N, and each described sweep signal generating subunit 22i comprises the first control signal input end GTV2_i, scan clock signal input end CKV2_i and sweep signal output terminal GOUTi, first control signal output terminal GTV of described latch subelement 21 is electrically connected the first control signal input end (GTV2_1 ~ GTV2_N) of corresponding described N number of sweep signal generating subunit.
It should be noted that, driver element can be arranged on the array base palte of display panel, corresponding sweep signal output terminal GOUTi is electrically connected with the sweep trace be arranged on array base palte, and sweep trace is electrically connected with the thin film transistor (TFT) be arranged on array base palte again, the sweep signal produced by sweep signal output terminal GOUTi can control the unlatching of thin film transistor (TFT) through sweep trace, therefore, the N number of sweep signal produced by sweep signal generating subunit is in embodiments of the present invention the signal of instigating respective films transistor to be opened, and is effective sweep signal.
Known by the driver element shown in Fig. 2, the first control signal produced by latch subelement 21 exports to N number of sweep signal generating subunit, and control this N number of sweep signal generating subunit to N+1 clock signal produce N number of sweep signal successively with second, wherein N be greater than 1 positive integer, namely a driver element of technical solution of the present invention can produce at least two sweep signals, compared with being merely able to generation sweep signal with a driver element, improve the efficiency that single driver element produces sweep signal.
Next preferred embodiment to provide latch subelement, sweep signal generating subunit and the driver element in driver element.As shown in Figure 3 a, the latch subelement in driver element also comprises the first Sheffer stroke gate NAND1, the second Sheffer stroke gate NAND2, the 3rd Sheffer stroke gate NAND3, the 4th Sheffer stroke gate NAND4, clamp diode 23, first phase inverter B1 and constant low level signal input part VGL; The first input end of described first Sheffer stroke gate NAND1 is electrically connected with described first control signal output terminal GTV, its second input end is electrically connected with described first clock signal input terminal CKV1, and its output terminal is electrically connected with second input end of described second Sheffer stroke gate NAND2; The first input end of described second Sheffer stroke gate NAND2 is electrically connected with described trigger pip input end STV, and its output terminal is electrically connected with the first input end of described 4th Sheffer stroke gate NAND4; The first input end of described 3rd Sheffer stroke gate NAND3 is electrically connected with described first clock signal input terminal CKV1, its second input end is electrically connected with described secondary trigger pip output terminal NEXT, and its output terminal is electrically connected with second input end of described 4th Sheffer stroke gate NAND4; The output terminal of described 4th Sheffer stroke gate NAND4 is electrically connected with described secondary trigger pip output terminal NEXT; The anode P1 of described clamp diode 23 is electrically connected with described constant low level signal input part VGL, and its negative electrode P2 is electrically connected with described secondary trigger pip output terminal NEXT; The input end of described first phase inverter B1 is electrically connected with described secondary trigger pip output terminal NEXT, and its output terminal is electrically connected with described first control signal output terminal GTV.
It should be noted that, the anode P1 of clamp diode 23 is electrically connected with constant low level signal input part VGL, and now clamp diode 23 does not have conducting, by its clamping action, its negative electrode P2 can be made to keep low level.Because secondary trigger pip output terminal NEXT is electrically connected with the negative electrode P2 of clamp diode 23, therefore, clamp diode 23 keeps low level for secondary trigger pip output terminal NEXT when making latch subelement original state, and the first control signal output terminal GTV keeps high level.
In fig. 3 a, clamp diode 23 is formed by NMOS tube NM1, the grid of described NMOS tube NM1 and its drain electrode are electrically connected as the anode P1 of clamp diode 23, the source electrode of described NMOS tube NM1 is as the negative electrode of clamp diode 23, but this is only the concrete example realizing clamp diode 23, in another specific example, clamp diode also can be formed by PMOS, the source electrode of described PMOS is as the anode of clamp diode, and grid and its drain electrode of described PMOS are electrically connected as the negative electrode of clamp diode.
Fig. 3 b is the sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal.In fig 3b, SSTV represents the trigger pip that trigger pip input end STV inputs; SCKV1 represents the first clock signal that the first clock signal input terminal CKV1 inputs; SNEXT represents the secondary trigger pip that secondary trigger pip output terminal exports; And SGTV represents the first control signal of the first control signal output terminal GTV output.And shown in Fig. 3 b time program process in, constant low level signal input part VGL continues to keep input constant low level signal.Next with regard to composition graphs 3b, the principle of work latching subelement in Fig. 3 a is described further.
Before further illustrating, input signal and output signal are simply set for low level signal and high level signal do one, namely represents that input signal and output signal are low level signal with 0, represent that input signal and output signal are high level signal with 1.Above-mentioned setting is applicable equally to each embodiment ensuing.
Sequential chart as shown in Figure 3 b, five moment of t1 to t5 increase successively gradually.Before time tl, because trigger pip SSTV is 0, therefore, no matter the first clock signal SCKV1 becomes 0 by 1, or becomes 1 by 0, and secondary trigger pip SNEXT still keeps during original state 0, and the first control signal SGTV still keeps during original state 1.
In the t1 moment, trigger pip SSTV becomes 1 by 0, and now the first clock signal SCKV1 is 1, is that the first control signal SGTV of 1 is sent to the first input end of the first Sheffer stroke gate NAND1 before the t1 moment, then the first Sheffer stroke gate NAND1 exports the 0, second Sheffer stroke gate NAND2 and exports 1; Before the t1 moment be 0 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports the 1, four Sheffer stroke gate NAND4 and exports 0, therefore in the t1 moment, secondary trigger pip SNEXT is the 0, first control signal SGTV is 1.
Between the t1 moment to t2 moment, secondary trigger pip SNEXT remains 0, and the first control signal SGTV remains 1.
In the t2 moment, the first clock signal SCKV1 becomes 0 by 1, and be that the first control signal SGTV of 1 is sent to the first input end of the first Sheffer stroke gate NAND1 before the t2 moment, then the first Sheffer stroke gate NAND1 exports the 1, second Sheffer stroke gate NAND2 and exports 0; Before the t2 moment be 0 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports the 1, four Sheffer stroke gate NAND4 and exports 1, therefore in the t2 moment, secondary trigger pip SNEXT becomes 1 by 0, and the first control signal SGTV becomes 0 by 1.
Between the t2 moment to t3 moment, be that the first control signal SGTV of 0 is sent to the first input end of the first Sheffer stroke gate NAND1 by the t2 moment, then the first Sheffer stroke gate NAND1 exports the 1, second Sheffer stroke gate NAND2 and exports 0; By the t2 moment be 1 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports 1,4th Sheffer stroke gate NAND4 exports 1, therefore between the t2 moment to t3 moment, secondary trigger pip SNEXT remains 1, and the first control signal SGTV remains 0.
In the t3 moment, the first clock signal SCKV1 becomes 1 by 0, and be that the first control signal SGTV of 0 is sent to the first input end of the first Sheffer stroke gate NAND1 before the t3 moment, then the first Sheffer stroke gate NAND1 exports the 1, second Sheffer stroke gate NAND2 and exports 0; Before the t3 moment be 1 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports the 0, four Sheffer stroke gate NAND4 and exports 1, therefore in the t3 moment, secondary trigger pip SNEXT remains 1, and the first control signal SGTV remains 0.
Between the t3 moment to t4 moment, secondary trigger pip SNEXT remains 1, and the first control signal SGTV remains 0.
In the t4 moment, trigger pip SSTV becomes 0 by 1, and be that the first control signal SGTV of 0 is sent to the first input end of the first Sheffer stroke gate NAND1 before the t4 moment, then the first Sheffer stroke gate NAND1 exports the 1, second Sheffer stroke gate NAND2 and exports 1; Before the t4 moment be 1 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports the 0, four Sheffer stroke gate NAND4 and exports 1, therefore in the t4 moment, secondary trigger pip SNEXT remains 1, and the first control signal SGTV remains 0.
In the t4 moment to the t5 moment, secondary trigger pip SNEXT still remains 1, and the first control signal SGTV still remains 0.
In the t5 moment, the first clock signal becomes 0 by 1, and be that the first control signal SGTV of 0 is sent to the first input end of the first Sheffer stroke gate NAND1 before the t5 moment, then the first Sheffer stroke gate NAND1 exports the 1, second Sheffer stroke gate NAND2 and exports 1; Before the t5 moment be 1 secondary trigger pip SNEXT be sent to second input end of the 3rd Sheffer stroke gate NAND3, then the 3rd Sheffer stroke gate NAND3 exports the 1, four Sheffer stroke gate NAND4 and exports 0, therefore in the t5 moment, secondary trigger pip SNEXT becomes 0 by 1, and the first control signal SGTV becomes 1 by 0.
After the t5 moment, secondary trigger pip SNEXT remains 0, and the first control signal SGTV remains 1.
By drawing latching the sequential chart shown in the description of principle of work of subelement and Fig. 3 b in Fig. 3 a: in the t1 moment, although trigger pip SSTV becomes 1 by 0, now latching the secondary trigger pip SNEXT that subelement produces still is 0; In the t2 moment, the first clock signal SCKV1 becomes 0 by 1 and trigger pip SSTV is still 1, now latches subelement and be triggered, and its secondary trigger pip SNEXT produced becomes 1 by 0; In the t3 moment, the first clock signal SCKV1 becomes 1 by 0 and trigger pip SSTV remains 1 and remain 1 and trigger pip SSTV becomes 0 by 1 at t4 moment first clock signal SCKV1, and corresponding secondary trigger pip SNEXT remains 1; In the t5 moment, the first clock signal SCKV1 becomes 0 by 1 and trigger pip SSTV remains 0, and now secondary trigger pip SNEXT becomes 0 by 1.Therefore, after trigger pip SSTV becomes 1 by 0, and within the cycle of the first clock signal SCKV1 of the first clock signal SCKV1 by 1 moment becoming 0, even if 0 can be become by 1 at this cycle internal trigger signal SSTV, secondary trigger pip SNEXT can keep output 1 always, and this shows to latch the function that subelement has latch.
In fig 3b from the t2 moment to the t5 moment, the secondary trigger pip SNEXT latching subelement generation is 1, first control signal SGTV is 0, and by the setting to sweep signal generating subunit, within the time period that the first control signal SGTV is 0, can make and latch the sweep signal generating subunit that subelement is electrically connected and produce sweep signal.
In order to match the function merging and realize driver element with the latch subelement in Fig. 3 a, as shown in fig. 4 a, each sweep signal generating subunit in driver element at least also comprises a rejection gate NORi, the first input end of described rejection gate NORi is electrically connected to receive described second to the clock signal of in N clock signal with described scan clock signal input end CKV2_i, its second input end is electrically connected with described first control signal input end GTV2_i, its output terminal is electrically connected the sweep signal exported in described N number of sweep signal with described sweep signal output terminal GOUTi.
Fig. 4 b is the sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 4 a.In fig. 4b, SCKV2i represents the i-th+1 clock signal that scan clock signal input end CKV2_i inputs; SGTV2i represents the first control signal that the first control signal input end GTV2_i inputs; SGOUTi represents the sweep signal that sweep signal output terminal GOUTi exports.As shown in Figure 4 b, when the first control signal SGTV2i inputting sweep signal generating subunit is 0 and the i-th+1 clock signal SGTV2i is 0, the sweep signal SGOUTi that sweep signal generating subunit exports is 1.That is, when the first control signal that latch subelement in fig. 3 a produces is 0, along with the change of the i-th+1 clock signal SGTV2i being applied to sweep signal generating subunit, the sweep signal SGOUTi that sweep signal generating subunit exports is 1, and therefore the sweep signal generating subunit in Fig. 4 a and the latch subelement in Fig. 3 a match and can realize the function of driver element.
The sweep signal produced due to the sweep signal generating subunit in Fig. 4 a is more weak, therefore, in order to the sweep signal that the sweep signal generating subunit strengthened in Fig. 4 a produces, as illustrated in fig. 4 c, on the basis of Fig. 4 a, each sweep signal generating subunit also comprises 2M the second phase inverter (Bi_1 ~ Bi_2M) be electrically connected in series, M be greater than 0 positive integer, wherein, the input end of first the second phase inverter Bi_1 is electrically connected with the output terminal of described rejection gate NORi, the output terminal of 2M the second phase inverter Bi_2M is electrically connected with described sweep signal output terminal GOUTi.It should be noted that, number due to the second phase inverter in Fig. 4 c is even number, therefore, the signal that the output terminal of the sweep signal AND OR NOT gate that sweep signal output terminal GOUTi exports exports has identical level, and 2M the second phase inverter only plays the effect strengthening rejection gate output signal, that is, in such cases, the in-phase signal each other of the sweep signal needed for unlatching of the thin film transistor (TFT) on the sweep signal that sweep signal generating subunit in Fig. 4 a produces and array base palte.In actual design, can select the number of the second phase inverter as required.Preferably two the second phase inverters be electrically connected in series are set in each sweep signal generating subunit, so not only can play the effect of enhancing to the output signal of rejection gate, production cost and the space reducing to arrange the second phase inverter can be reduced simultaneously.
But, the sweep signal inversion signal each other that sweep signal needed for the unlatching of the thin film transistor (TFT) on array base palte also can produce with the sweep signal generating subunit in Fig. 4 a, in such cases, in order to the sweep signal that the sweep signal generating subunit strengthened in Fig. 4 a produces, as shown in figure 4d, on the basis of Fig. 4 a, each sweep signal generating subunit also comprises 2L-1 the second phase inverter (Bi_1 ~ Bi_2L-1), wherein L be greater than 0 positive integer; For L=1, each sweep signal generating subunit comprises second phase inverter (being such as Bi_1), the input end of described second phase inverter is electrically connected with the output terminal of described rejection gate NORi, and the output terminal of described second phase inverter is electrically connected with described sweep signal output terminal GOUTi; 1 is greater than for L, each sweep signal generating subunit comprises 2L-1 the second phase inverter be electrically connected in series, wherein, the input end of first the second phase inverter Bi_1 is electrically connected with the output terminal of described rejection gate NORi, and the output terminal of 2L-1 the second phase inverter Bi_2L-1 is electrically connected with described sweep signal output terminal GOUTi.The sweep signal inversion signal each other that in the sweep signal produced due to sweep signal generating subunit in Fig. 4 d and Fig. 4 a, sweep signal generating subunit produces, therefore, about the waveform of the sweep signal that Fig. 4 d produces, specifically can reference diagram 4b, do not repeat them here.Based on foregoing description, in each embodiment ensuing, be illustrated for the sweep signal generating subunit shown in Fig. 4 c.
In embodiments of the present invention, preferably, the waveform of described first clock signal is identical with the cycle to the waveform of N+1 clock signal with described second with the cycle, and the time delay between described first clock signal and described second clock signal and the time delay between described N+1 clock signal and described first clock signal equal the time delay in described second to N+1 clock signal between arbitrary neighborhood two clocks; Described first clock signal and described second is equal to the ratio of in one-period duration of pulse and (N+1) × (described duration of pulse+described time delay) to the dutycycle of N+1 clock signal.
Next in conjunction with the circuit structure of above-mentioned latch subelement and sweep signal generating subunit, exemplarily provide the circuit structure of a driver element, and be described further about the first clock signal and second to cycle of N+1 clock signal, duration of pulse, time delay and dutycycle etc. above-mentioned.As shown in Figure 5 a, identical with Fig. 3 a of the latch subelement in driver element, does not repeat them here, driver element comprises three sweep signal generating subunit (corresponding N=3), each sweep signal generating subunit (is respectively NOR1 by a rejection gate for three sweep signal generating subunit, NOR2 and NOR3) and two be electrically connected in series second phase inverters composition (for three sweep signal generating subunit, be respectively B11 and B12, B21 and B22 and B31 and B32), three sweep signal generating subunit corresponding three for receiving the scan clock signal input end CKV2_1 of the second to the 4th clock signal successively, CKV2_2 and CKV2_3, and correspondence three is for exporting the sweep signal output terminal GOUT1 of sweep signal successively, GOUT2 and GOUT3.
Fig. 5 b is the sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 5 a.In figure 5b, the trigger pip that the trigger pip input end STV that subelement is latched in SSTV representative inputs; The first clock signal that the first clock signal input terminal CKV1 that subelement is latched in SCKV1 representative inputs; The first control signal that the first control signal output terminal GTV that subelement is latched in SGTV representative exports; SCKV21, SCKV22 and SCKV23 represent the second to the 4th clock signal of scan clock signal input end CKV2_1, CKV2_2 and CKV2_3 input of three sweep signal generating subunit respectively; The sweep signal that sweep signal output terminal GOUT1, GOUT2 and GOUT3 that SGOUT1, SGOUT2 and SGOUT3 represent three sweep signal generating subunit respectively export.
As shown in Figure 5 b, the cycle of the cycle of the first clock signal SCKV1 and the second to the 4th clock signal is T, and in one-period T the corresponding duration of pulse be T1, wherein, described pulse is 0 pulse, and first time delay between clock signal SCKV1 and second clock signal SCKV21, time delay between second clock signal SCKV21 and the 3rd clock signal SCKV22, time delay between 3rd clock signal SCKV22 and the 4th clock signal SCKV23 and the time delay between the 4th clock signal SCKV23 and the first clock signal SCKV1 are T2, therefore, first clock signal SCKV1 and second can be expressed as to the cycle T of the 4th clock signal: T=4T1+4T2, correspondingly, first clock signal SCKV1 and second can be expressed as T1/T=T1/ (4T1+4T2) to the dutycycle of the 4th clock signal, namely this dutycycle equals the ratio of duration of pulse T1 and 4 × (duration of pulse T1+ T2 time delay) in one-period.
By the above-mentioned setting to being applied to the first clock signal SCKV1 latching subelement, and to the second clock signal SCKV21 that three sweep signal generating subunit apply, the setting of the 3rd clock signal SCKV22 and the 4th clock signal SCKV23, the sweep signal SGOUT1 that three sweep signal generating subunit export can be made successively, SGOUT2 and SGOUT3 is 1, therefore, based on to Fig. 3 a, the analysis of Fig. 4 a and Fig. 4 c and associated description, driver element shown in Fig. 5 a can realize its function, namely sweep signal is produced, and the driver element in Fig. 5 a can produce three sweep signals successively, compared with only producing a sweep signal with a driver element, driver element provided by the invention can improve the efficiency producing sweep signal.
It should be noted that, Fig. 5 a is only a concrete example about driver element, about the number of the second phase inverter in the number of the sweep signal generating subunit included by it and sweep signal generating subunit, in this no limit.
The embodiment of the present invention also provides a kind of driving method of driver element, and described driving method is performed by the driver element described in above-described embodiment.Fig. 6 is the schematic flow sheet of the driving method of a kind of driver element that the embodiment of the present invention provides.As shown in Figure 6, described driving method comprises:
Step 31, latch subelement produce secondary trigger pip and the first control signal according to trigger pip and the first clock signal;
Step 32, i-th sweep signal generating subunit produce sweep signal corresponding to described i-th sweep signal generating subunit successively according to described first control signal received and the i-th+1 clock signal, until all sweep signal generating subunit drive complete, wherein i is the positive integer being not more than N.
About the detailed description of above-mentioned steps 31 to step 32, please refer to the associated description of above-described embodiment about driver element, do not repeat them here.
The embodiment of the present invention also provides a kind of driving circuit.Fig. 7 a is the structural representation of a kind of driving circuit that the embodiment of the present invention provides.As shown in Figure 7a, comprise the driver element described in above-described embodiment of plural serial stage electrical connection, wherein, trigger pip end STV1 in first order driver element with for providing the line trigger signal stv of trigger pip to be electrically connected, in arbitrary neighborhood two-stage drive unit, the secondary trigger pip output terminal NEXTn of upper level driver element is electrically connected with the trigger pip input end STVn+1 of next stage driver element, wherein n is the positive integer being more than or equal to 1 and being less than driver element series connection progression, and the secondary trigger pip output terminal of afterbody driver element is unsettled.In figure 7 a, CLK_1 ~ N+1 represents N+1 bar for applying the clock cable of clock signal, be electrically connected with the first clock signal input terminal CKV1 in every grade of driver element and N number of scan clock signal input end CKV2_1 ~ CKV2_N respectively, for providing the first clock signal and second to N+1 clock signal; GTVr represents the first control signal output terminal of the latch subelement in every grade of driver element, and wherein r is the positive integer being more than or equal to 1 and being less than or equal to series connection progression.
Particularly, in the driving circuit shown in Fig. 7 a, for first order driver element, CLK_1 is electrically connected with the first clock signal input terminal CKV1 in this grade of driver element, and CLK_2 ~ CLK_N+1 is electrically connected with the N number of scan clock signal input end CKV2_1 ~ CKV2_N in this grade of driver element respectively; For second level driver element, CLK_N+1 is electrically connected with the first clock signal input terminal CKV1 in this grade of driver element, and CLK_1 ~ CLK_N is electrically connected with the N number of scan clock signal input end CKV2_1 ~ CKV2_N in this grade of driver element respectively; When the series connection progression of driver element equals 3, for third level driver element, CLK_N is electrically connected with the first clock signal input terminal CKV1 in this grade of driver element, CLK_N+1 is electrically connected with first scan clock signal input end CKV2_1 of this grade of driver element, and CLK_1 ~ CLK_N-1 is electrically connected with the residue N-1 in this grade of driver element scan clock signal input end CKV2_2 ~ CKV2_N respectively; When the series connection progression of driver element is greater than 3, for jth level driver element, CLK_N-j+3 is electrically connected with the first clock signal input terminal CKV1 in this grade of driver element, CLK_N-j+4 to CLK_N+1 is electrically connected with scan clock signal input end CKV2_1 to the CKV2_n-2 of this grade of driver element, CLK_1 to CLK_N-j+2 is electrically connected with scan clock signal input end CKV2_j-1 to the CKV2_N of this grade of driver element, wherein, j be greater than 3 positive integer.
By applying second to N+1 clock signal to every grade of driver element, can ensure that every grade of driver element exports with second successively to the corresponding sweep signal of N+1 clock signal, by above-mentioned known to arranging of the first clock signal input terminal in driver element at different levels and scan clock signal input end and clock cable, the first clock signal input terminal in next stage driver element is always electrically connected with the clock cable applying N+1 clock signal to its upper level driver element, that is, when upper level driver element produces last sweep signal, the latch subelement in its next stage driver element can be driven to start working, can ensure that driver element at different levels exports sweep signal successively like this, thus whole driving circuit can be enable to export sweep signal successively.
It should be noted that, Fig. 7 a schematically shows by the driver element in above-described embodiment to form driving circuit, in actual design, the number of the sweep signal generating subunit that each driver element forming driving circuit comprises can be all equal, also can the number of sweep signal generating subunit in part driver element equal, also can the number of sweep signal generating subunit all in driver element all unequal, specifically can select according to actual conditions, as long as the driving circuit needed for can being formed by the driver element in above-described embodiment, in this no limit.
Driving circuit adopts the driver element described in above-described embodiment, because each driver element can produce at least two sweep signals, that is, the latch subelement arranged in the driving unit can drive at least two sweep signal generating subunit and produce the sweep signal of respective numbers.The driver element adopted with driving circuit is that each grid unit can only produce a sweep signal and namely often produces a sweep signal and just need one to latch compared with subelement, less latch subelement can be set in the driving circuit of technical solution of the present invention, not only can reduce the power consumption of driving circuit, the space that driving circuit takies can also be reduced.In addition, compared with the driving circuit only needing two clock signals to drive, driving circuit in technical solution of the present invention at least needs three clock signals to drive, therefore, when drive circuit works, the frequency of clock signal can be reduced, thus the electromagnetic interference (EMI) that clock signal produces can be reduced.
Next an example is provided so that the principle of work of the driving circuit in Fig. 7 a to be described.Suppose that the driving circuit in Fig. 7 a has the driver element of thtee-stage shiplock electrical connection, and every grade of driver element comprises three sweep signal generating subunit.As shown in Figure 7b, driving circuit has the driver element of thtee-stage shiplock electrical connection, and every grade of driver element comprises three sweep signal generating subunit, wherein, the latch subelement in every grade of driver element and sweep signal generating subunit all adopt latch subelement in the driver element shown in Fig. 5 a and sweep signal generating subunit, three sweep signal generating subunit are comprised known based on every grade of driver element, whole driving circuit needs the first clock signal and the second to the 4th clock signal, thered is provided for clock cable CLK_1 ~ 4 applying clock signal by 4 in figure, wherein, first clock signal input terminal CKV1 of first order driver element is electrically connected with Article 1 clock cable CLK_1, three scan clock signal input end CKV2_1 of first order driver element, CKV2_2 and CKV2_3 respectively with Article 2 clock cable CLK_2, Article 3 clock cable CLK_3 and Article 4 clock cable CLK_4 is electrically connected, first clock signal input terminal CKV1 of second level driver element is electrically connected with Article 4 clock cable CLK_4, and three scan clock signal input ends CKV2_1, CKV2_2 and CKV2_3 of second level driver element are electrically connected with Article 1 clock cable CLK_1, Article 2 clock cable CLK_2 and Article 3 clock cable CLK_3 respectively, first clock signal input terminal CKV1 of third level driver element is electrically connected with Article 3 clock cable CLK_3, and three scan clock signal input ends CKV2_1, CKV2_2 and CKV2_3 of third level driver element are electrically connected with Article 4 clock cable CLK_4, Article 1 clock cable CLK_1 and Article 2 clock cable CLK_2 respectively.By above-mentioned known to arranging of the first clock signal input terminal in driver element at different levels and scan clock signal input end and clock cable, the first clock signal input terminal in next stage driver element is always electrically connected with the clock cable applying the 4th clock signal to its upper level driver element, that is, when upper level driver element produces last sweep signal, the latch subelement in its next stage driver element can be driven to start working, can ensure that driver element at different levels exports sweep signal successively like this, thus whole driving circuit can be enable to export sweep signal successively.
Fig. 7 c is the sequential chart of the input signal of each input end of driving circuit in Fig. 7 b and the output signal of each output terminal.In figure 7 c, sstv represents the trigger pip that line trigger signal stv provides; SCLK1 ~ SCLK4 represents the clock signal that 4 clock cable CLK_1 ~ CLK_4 provide successively; The first control signal that the first control signal output terminal GTV3 in the first control signal that SGTV1, SGTV2 and SGTV3 represent the first control signal that the first control signal output terminal GTV1 in first order driver element produces respectively, the first control signal output terminal GTV2 in the driver element of the second level produces and third level driver element produces; SNEXT1, SNEXT2 and SNEXT3 represent the secondary trigger pip that the secondary trigger pip output terminal NEXT3 in the secondary trigger pip and third level driver element that the secondary trigger pip output terminal NEXT2 in secondary trigger pip that the secondary trigger pip output terminal NEXT1 in first order driver element produces, second level driver element produces produces respectively; SGOUT1 ~ SGOUT9 represents nine sweep signals that driving circuit exports.Based on to analysis and the associated description of Fig. 5 a and Fig. 5 b and illustrate the explanation of Fig. 7 b, can realize from the driving circuit shown in Fig. 7 c, Fig. 7 b the function exporting required sweep signal successively.
The embodiment of the present invention also provides a kind of array base palte.Fig. 8 is the structural representation of a kind of array base palte that the embodiment of the present invention provides.As shown in Figure 8, array base palte comprise gate driver circuit 41, data drive circuit 42, a plurality of data lines (D1 shown in Fig. 8, D2 ..., Dk), multi-strip scanning line (S1 shown in Fig. 8, S2 ..., Sm) and intersect by a plurality of data lines and multi-strip scanning line the multiple pixel cells 43 limited, wherein pixel cell 43 comprises thin film transistor (TFT) 431 and the pixel electrode 432 be connected electrically, and wherein gate driver circuit 41 is the driving circuit described in above-described embodiment.
Particularly, gate driver circuit 41, for each bar sweep trace (S1, S2 ..., Sm) sweep signal is provided, wherein, each sweep signal output terminal of the sweep signal generating subunit in gate driver circuit 41 is electrically connected a sweep trace; Data drive circuit 42, for pieces of data line (D1, D2 ..., Dk) data-signal is provided; The grid of the thin film transistor (TFT) 431 in pixel cell 43 is electrically connected with a sweep trace, the source electrode of thin film transistor (TFT) 431 is electrically connected with a data line, the drain electrode of thin film transistor (TFT) 431 and being electrically connected with its pixel electrode 432 being arranged in same pixel cell 43, the sweep signal that sweep trace provides can control unlatching or the closedown of thin film transistor (TFT) 431, the data-signal that data line provides can be sent to pixel electrode 432 by the thin film transistor (TFT) 431 opened, thus can realize showing corresponding display frame.
Because the gate driver circuit in array base palte adopts the driving circuit described in above-described embodiment, and the space that this driving circuit takies is less, therefore, the frame region arranging the array base palte of this driving circuit can be less, thus can be conducive to making array base palte easily realize narrow frame.In addition, because above-mentioned driving circuit can reduce the electromagnetic interference (EMI) that clock signal produces, therefore, the array base palte in the present embodiment also has same effect.
The embodiment of the present invention also provides a kind of display panel.Fig. 9 is the structural representation of a kind of display panel that the embodiment of the present invention provides.See Fig. 9, display panel comprises array base palte 52 that counter substrate 51 and counter substrate 51 be oppositely arranged, middle layer 53 between counter substrate 51 and array base palte 52.Wherein, array base palte 52 is the array base palte described in above-described embodiment.
Particularly, middle layer 53 is relevant with the display type of display panel.When adopting liquid crystal display, middle layer 53 is liquid crystal layer, counter substrate 51 can be color membrane substrates, by the electric field (corresponding twisted nematic) that formed between the public electrode that is arranged in counter substrate 31 and the pixel electrode being arranged in array base palte 52 or the rotation controlling the liquid crystal molecule in liquid crystal layer by being arranged on the electric field (corresponding edge field switch type or plane conversion type) formed between public electrode in array base palte 52 and pixel electrode, thus realize display effect.
As employing Organic Light Emitting Diode (Organic Light-Emitting Diode, be called for short OLED) when showing, middle layer 53 is for arranging organic luminous layer, counter substrate 51 can be color membrane substrates, packaged glass (Cover Glass) or cover-plate glass (Cover Lens) etc., controls organic luminous layer luminescence realize display effect by array base palte 52.
Because display panel have employed the array base palte described in above-described embodiment, therefore, display panel not only can easily realize narrow frame, also can reduce the electromagnetic interference (EMI) driving the clock signal of driving circuit to produce.
The driver element that the embodiment of the present invention provides and driving method thereof, driving circuit, array base palte and display panel, subelement is latched and the N number of sweep signal generating subunit corresponding with latching subelement by arranging in the driving unit, N be greater than 1 positive integer, wherein each sweep signal generating subunit can produce a sweep signal, due to one latch subelement can a driving N sweep signal generating subunit produce N number of sweep signal, therefore, so not only can reduce the power consumption of the driving circuit of this driver element of application, the space that driving circuit takies can also be reduced, thus the array base palte of this driving circuit of application and display panel can be made easily to realize narrow frame, in addition, driving circuit is driven to N+1 clock signal by the first clock signal and second, namely drives therefore by N+1 clock signal, when grid circuit works, the frequency of clock signal can be reduced, thus the electromagnetic interference (EMI) of clock signal array substrate and display panel generation can be reduced.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (11)
1. a driver element, is characterized in that, comprising: latch subelement, and the N number of sweep signal generating subunit corresponding with described latch subelement, N be greater than 1 positive integer, wherein,
Described latch subelement is used for producing secondary trigger pip and the first control signal according to trigger pip and the first clock signal, and described latch subelement comprises trigger pip input end, the first clock signal input terminal, secondary trigger pip output terminal and the first control signal output terminal;
Described first control signal and second that described N number of sweep signal generating subunit is used for according to receiving produces N number of sweep signal successively to N+1 clock signal, wherein, described i-th+1 clock signal produces sweep signal for controlling i-th sweep signal generating subunit, i is the positive integer being not more than N, and each described sweep signal generating subunit comprises the first control signal input end, scan clock signal input end and sweep signal output terminal;
First control signal input end of described N number of sweep signal generating subunit of the first control signal output terminal electrical connection correspondence of described latch subelement.
2. driver element according to claim 1, is characterized in that, described latch subelement also comprises the first Sheffer stroke gate, the second Sheffer stroke gate, the 3rd Sheffer stroke gate, the 4th Sheffer stroke gate, clamp diode, the first phase inverter and constant low level signal input part;
The first input end of described first Sheffer stroke gate is electrically connected with described first control signal output terminal, and its second input end is electrically connected with described first clock signal input terminal, and its output terminal is electrically connected with the second input end of described second Sheffer stroke gate;
The first input end of described second Sheffer stroke gate is electrically connected with described trigger pip input end, and its output terminal is electrically connected with the first input end of described 4th Sheffer stroke gate;
The first input end of described 3rd Sheffer stroke gate is electrically connected with described first clock signal input terminal, and its second input end is electrically connected with described secondary trigger pip output terminal, and its output terminal is electrically connected with the second input end of described 4th Sheffer stroke gate;
The output terminal of described 4th Sheffer stroke gate is electrically connected with described secondary trigger pip output terminal;
The anode of described clamp diode is electrically connected with described constant low level signal input part, and its negative electrode is electrically connected with described secondary trigger pip output terminal;
The input end of described first phase inverter is electrically connected with described secondary trigger pip output terminal, and its output terminal is electrically connected with described first control signal output terminal.
3. driver element according to claim 2, it is characterized in that, described clamp diode is formed by NMOS tube, and the grid of described NMOS tube and its drain electrode are electrically connected as the anode of described clamp diode, and the source electrode of described NMOS tube is as the negative electrode of described clamp diode; Or
Described clamp diode is formed by PMOS, and the source electrode of described PMOS is as the anode of described clamp diode, and grid and its drain electrode of described PMOS are electrically connected as the negative electrode of described clamp diode.
4. driver element according to claim 1 and 2, is characterized in that, each sweep signal generating subunit at least also comprises a rejection gate;
The first input end of described rejection gate is electrically connected to receive described second to the clock signal of in N+1 clock signal with described scan clock signal input end, its second input end is electrically connected with described first control signal input end, and its output terminal is electrically connected the sweep signal exported in described N number of sweep signal with described sweep signal output terminal.
5. driver element according to claim 4, is characterized in that, each sweep signal generating subunit also comprises 2L-1 the second phase inverter, wherein L be greater than 0 positive integer;
For L=1, each sweep signal generating subunit comprises second phase inverter, and the input end of described second phase inverter is electrically connected with the output terminal of described rejection gate, and the output terminal of described second phase inverter is electrically connected with described sweep signal output terminal;
1 is greater than for L, each sweep signal generating subunit comprises 2L-1 the second phase inverter be electrically connected in series, wherein, the input end of first the second phase inverter is electrically connected with the output terminal of described rejection gate, and the output terminal of 2L-1 the second phase inverter is electrically connected with described sweep signal output terminal.
6. driver element according to claim 4, it is characterized in that, each sweep signal generating subunit also comprises 2M the second phase inverter be electrically connected in series, M be greater than 0 positive integer, wherein, the input end of first the second phase inverter is electrically connected with the output terminal of described rejection gate, and the output terminal of 2M the second phase inverter is electrically connected with described sweep signal output terminal.
7. driver element according to claim 1, it is characterized in that, the waveform of described first clock signal is identical with the cycle to the waveform of N+1 clock signal with described second with the cycle, and the time delay between described first clock signal and described second clock signal and the time delay between described N+1 clock signal and described first clock signal equal the time delay in described second to N+1 clock signal between arbitrary neighborhood two clock signals;
Described first clock signal and described second is equal to the ratio of in one-period duration of pulse and (N+1) × (described duration of pulse+described time delay) to the dutycycle of N+1 clock signal.
8. a driving method for driver element, the driver element of described driving method according to any one of claim 1-7 performs, and it is characterized in that, described driving method comprises:
Latch subelement and produce secondary trigger pip and the first control signal according to trigger pip and the first clock signal;
I-th sweep signal generating subunit produces sweep signal corresponding to described i-th sweep signal generating subunit successively according to described first control signal received and the i-th+1 clock signal, until all sweep signal generating subunit drive complete.
9. a driving circuit, it is characterized in that, comprise the driver element according to any one of claim 1-7 of plural serial stage electrical connection, wherein, in arbitrary neighborhood two-stage drive unit, the secondary trigger pip output terminal of upper level driver element is electrically connected with the trigger pip input end of next stage driver element.
10. an array base palte, comprise a plurality of data lines, multi-strip scanning line and intersect by described a plurality of data lines and multi-strip scanning line the multiple pixel cells limited, the pixel electrode that wherein said pixel cell comprises thin film transistor (TFT) and is connected electrically, it is characterized in that, also comprise driving circuit as claimed in claim 9, wherein, each sweep signal output terminal of the sweep signal generating subunit in described driving circuit is electrically connected a sweep trace.
11. 1 kinds of display panels, is characterized in that, comprise array base palte as claimed in claim 10.
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