CN104392687B - Drive unit as well as drive method thereof, drive circuit, array substrate and display panel - Google Patents
Drive unit as well as drive method thereof, drive circuit, array substrate and display panel Download PDFInfo
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- CN104392687B CN104392687B CN201410733496.3A CN201410733496A CN104392687B CN 104392687 B CN104392687 B CN 104392687B CN 201410733496 A CN201410733496 A CN 201410733496A CN 104392687 B CN104392687 B CN 104392687B
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Abstract
The invention discloses a drive unit as well as a drive method thereof, a drive circuit, an array substrate and a display panel, wherein the drive unit comprises a latch sub unit and N scanning signal generating sub units corresponding to the latch sub unit, N is a positive integer bigger than 1; the latch sub unit is used for generating a secondary trigger signal and a first control signal in sequence according to the trigger signal and a first clock signal; the N scanning signal generating sub units are used for generating N scanning signals in sequence according to the received first control signal, the second to the (N+1)-th clock signals, wherein the (N+1)-th clock signal is used for controlling the i-th scanning signal generating sub unit to generate a scanning signal, and i is a positive integer not bigger than N. The drive unit provided by the invention not only can be used for lowering the power consumption of the drive circuit and enabling the array substrate and the display panel to easily realize narrow side frames, but also can be used for lowering the electromagnetic interferences of the clock signals for driving the drive circuit on the array substrate and the display panel.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of driver element and its driving method, drive circuit, array
Substrate and display floater.
Background technology
Recently, with the development of Display Technique, the application of display floater is also more and more extensive.When display floater works,
Drive circuit in display floater will produce scanning signal, seriatim to drive each scan line in array base palte,
Data signal is enable to be transferred to each pixel cell in array base palte.Above-mentioned scanning signal is by drive circuit
Driver element producing.
Fig. 1 is the structural representation of the driver element of prior art.As shown in figure 1, driver element includes: latch 10,
NAND gate a8, three phase inverters being electrically connected in series (the 3rd phase inverter a3, the 4th phase inverter a4 and the 5th phase inverter a5) are constituted
Three-level buffer, trigger input in, the first clock signal input terminal ckv1, scan clock signal input ckv2 and
Outfan gout, wherein, latch 10 includes two phase inverters (the first phase inverter a1 and the second phase inverter a2) and two clocks
Phase inverter (the first clocked inverter a6 and second clock phase inverter a7), the input of latch 10 is trigger input in
With the first clock signal input terminal ckv1, the outfan of latch 10 as secondary trigger outfan next, and and with non-
The first input end electrical connection of door a8, its second input is electrically connected with scan clock signal input ckv2, NAND gate a8
Outfan is electrically connected with the input of the 3rd phase inverter a3, the outfan of the 5th phase inverter a5 and the outfan gout of driver element
Electrical connection.
Drive circuit can be obtained by being electrically connected in series above-mentioned driver element step by step, wherein, arbitrary neighborhood two-stage is driven
In moving cell a kind of new rgbw of the secondary trigger of upper level driver element arrange in pairs or groups rgb backlight display packing outfan with
The trigger input electrical connection of next stage driver element.Above-mentioned drive circuit is applied to display floater, due to each drive
The scanning signal of moving cell only one of which outfan gout, this outfan gout output is used for scanning one horizontal scanning line, therefore, such as
Fruit display floater has n horizontal scanning line it is necessary to drive circuit at least includes the driver element that n level is electrically connected in series.
In prior art, for display floater, the power consumption of drive circuit occupies greatly.And drive circuit
Using the driver element shown in Fig. 1, the quantity of the driver element due to needing is more, hence in so that the power dissipation ratio of drive circuit is relatively
Greatly；Additionally, drive circuit is arranged on the frame region of display floater, due to constitute drive circuit driver element quantity relatively
Many, therefore, it is relatively difficult that display floater realizes narrow frameization；In addition, drive circuit is operationally, because driver elements at different levels are equal
To provide clock to the first clock signal input terminal ckv1 and scan clock signal input ckv2 by two clock cables
Signal, therefore, in order to meet drive circuit works, the frequency of two clock signals is higher, dividing in particular with display floater
Resolution improves, and electromagnetic interference can be than larger.
Content of the invention
In view of this, the embodiment of the present invention provide a kind of driver element and its driving method, drive circuit, array base palte and
Display floater, to solve technical problem present in above-mentioned prior art.
In a first aspect, the embodiment of the present invention provide a kind of driver element, comprising: latch subelement, and with described latch
The corresponding n scanning signal generating subunit of subelement, n is the positive integer more than 1, wherein,
Described latch subelement is used for producing secondary trigger and the first control according to trigger and the first clock signal
Signal processed, described latch subelement includes trigger input, the first clock signal input terminal, secondary trigger outfan
And the first control signal outfan；
Described n scanning signal generating subunit be used for according to described first control signal that receives and the second to the n-th+
1 clock signal is sequentially generated n scanning signal, and wherein, described i+1 clock signal is used for controlling i-th scanning signal to produce
Subelement produces scanning signal, and i is the no more than positive integer of n, and each described scanning signal generating subunit includes the first control
Signal input part processed, scan clock signal input and scanning signal outfan；
It is single that the described corresponding described n scanning signal of the first control signal outfan electrical connection latching subelement produces son
First control signal input of unit.
Second aspect, the embodiment of the present invention also provides a kind of driving method of driver element, and described driving method is by above-mentioned
Executing, described driving method includes driver element described in first aspect:
Latch subelement and secondary trigger and the first control signal are produced according to trigger and the first clock signal；
I-th scanning signal generating subunit according to described first control signal receiving and i+1 clock signal according to
The secondary generation corresponding scanning signal of described i-th scanning signal generating subunit, until all scanning signal generating subunit drive
Move and finish.
The third aspect, the embodiment of the present invention also provides a kind of drive circuit, including above-mentioned the first of plural serial stage electrical connection
Driver element described in aspect, wherein, in arbitrary neighborhood two-stage drive unit, the secondary trigger of upper level driver element is defeated
Go out end to electrically connect with the trigger input of next stage driver element.
Fourth aspect, the embodiment of the present invention also provides a kind of array base palte, including a plurality of data lines, multi-strip scanning line and by
Described a plurality of data lines and multi-strip scanning line intersect the multiple pixel cells limiting, and wherein said pixel cell includes film crystal
Pipe and the pixel electrode being connected electrically, also include the drive circuit described in the above-mentioned third aspect, wherein, in described drive circuit
Scanning signal generating subunit each scanning signal outfan electrically connect a scan line.
5th aspect, the embodiment of the present invention also provides a kind of display floater, including the array base described in above-mentioned fourth aspect
Plate.
Driver element provided in an embodiment of the present invention and its driving method, drive circuit, array base palte and display floater, lead to
Cross in the driving unit setting latch subelement and with latch the corresponding n scanning signal generating subunit of subelement, n is big
In 1 positive integer, wherein each scanning signal generating subunit can produce a scanning signal, due to a latch subelement
N scanning signal generating subunit can be driven and produce n scanning signal, therefore, so not only can reduce this drive of application
The power consumption of the drive circuit of moving cell, can also reduce the space of drive circuit occupancy, such that it is able to make this drive circuit of application
Array base palte and display floater easily realize narrow frame；Additionally, drive circuit is by the first clock signal and the second to the (n+1)th
Clock signal, to drive, to be driven by n+1 clock signal, therefore, when grid circuit works, can reduce clock signal
Frequency, such that it is able to reduce the electromagnetic interference that clock signal array substrate and display floater produce.
Brief description
By reading the detailed description that non-limiting example is made made with reference to the following drawings, other of the present invention
Feature, objects and advantages will become more apparent upon:
Fig. 1 is the structural representation of the driver element of prior art；
Fig. 2 is a kind of structural representation of driver element provided in an embodiment of the present invention；
Fig. 3 a is a kind of electrical block diagram latching subelement provided in an embodiment of the present invention；
Fig. 3 b is the sequential chart of the output signal of the input signal of each input and each outfan in Fig. 3 a；
Fig. 4 a is a kind of electrical block diagram of scanning signal generating subunit provided in an embodiment of the present invention；
Fig. 4 b is the sequential chart of the output signal of the input signal of each input and outfan in Fig. 4 a；
Fig. 4 c is the electrical block diagram of another kind scanning signal generating subunit provided in an embodiment of the present invention；
Fig. 4 d is the electrical block diagram of another scanning signal generating subunit provided in an embodiment of the present invention；
Fig. 5 a is a kind of electrical block diagram of driver element provided in an embodiment of the present invention；
Fig. 5 b is the sequential chart of the output signal of the input signal of each input and each outfan in Fig. 5 a；
Fig. 6 is a kind of schematic flow sheet of the driving method of driver element provided in an embodiment of the present invention；
Fig. 7 a is a kind of structural representation of drive circuit provided in an embodiment of the present invention；
Fig. 7 b is a kind of structural representation of specific embodiment of drive circuit in Fig. 7 a；
Fig. 7 c is the sequential chart of the output signal of the input signal of each input of drive circuit in Fig. 7 b and each outfan；
Fig. 8 is a kind of structural representation of array base palte provided in an embodiment of the present invention；
Fig. 9 is a kind of structural representation of display floater provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention rather than full content is illustrate only in description, accompanying drawing.
The embodiment of the present invention provides a kind of driver element.Fig. 2 is a kind of knot of driver element provided in an embodiment of the present invention
Structure schematic diagram.As shown in Fig. 2 described driver element includes: latch subelement 21, and corresponding with described latch subelement 21
N scanning signal generating subunit (corresponds to first scanning signal generating subunit the 221 to the n-th scanning signal in figure to produce
Subelement 22n), n is the positive integer more than 1, and wherein, described latch subelement 21 is used for according to trigger and the first clock letter
Number produce secondary trigger and the first control signal, described latch subelement 21 include trigger input stv, first when
Clock signal input part ckv1, secondary trigger outfan next and the first control signal outfan gtv；Described n scanning
Signal generating subunit is used for being sequentially generated n according to described first control signal receiving and the second to the (n+1)th clock signal
Individual scanning signal, wherein, described i+1 clock signal is used for controlling i-th scanning signal generating subunit to produce scanning signal,
I is the no more than positive integer of n, and each described scanning signal generating subunit 22i includes the first control signal input gtv2_
I, scan clock signal input ckv2_i and scanning signal outfan gouti；Described the first control latching subelement 21
Signal output part gtv electrically connects the first control signal input (gtv2_1 of corresponding described n scanning signal generating subunit
～gtv2_n).
It should be noted that driver element can be arranged on the array base palte of display floater, corresponding scanning signal is defeated
Go out to hold gouti and electrically connect with the scan line being arranged on array base palte, and scan line again with the thin film being arranged on array base palte
Transistor electrically connects, and can control thin film transistor (TFT) by the scanned line of scanning signal that scanning signal outfan gouti produces
Open, therefore, the n scanning signal being produced by scanning signal generating subunit in embodiments of the present invention is to instigate respective films
The signal that transistor is opened, as effective scanning signal.
By the driver element shown in Fig. 2, exported by the first control signal that latch subelement 21 produces and sweep to n
Retouch signal generating subunit, and to control this n scanning signal generating subunit to be sequentially generated with the second to the (n+1)th clock signal
N scanning signal, wherein n are the positive integer more than 1, and that is, technical solution of the present invention a driver element can produce at least two
Individual scanning signal, be merely able to produce a scanning signal with a driver element compared with, improve single driver element and produce and sweep
Retouch the efficiency of signal.
Next be preferred embodiment given the latch subelement in driver element, scanning signal generating subunit with
And driver element.As shown in Figure 3 a, the latch subelement in driver element also includes the first NAND gate nand1, the second NAND gate
Nand2, the 3rd NAND gate nand3, the 4th NAND gate nand4, clamp diode 23, the first phase inverter b1 and constant low level letter
Number input vgl；The first input end of described first NAND gate nand1 is electrically connected with described first control signal outfan gtv,
Its second input is electrically connected with described first clock signal input terminal ckv1, its outfan and described second NAND gate nand2
Second input electrical connection；The first input end of described second NAND gate nand2 is electrically connected with described trigger input stv
Connect, its outfan is electrically connected with the first input end of described 4th NAND gate nand4；The first of described 3rd NAND gate nand3
Input is electrically connected with described first clock signal input terminal ckv1, its second input with described secondary trigger outfan
Next electrically connects, and its outfan is electrically connected with the second input of described 4th NAND gate nand4；Described 4th NAND gate
The outfan of nand4 is electrically connected with described secondary trigger outfan next；The anode p1 of described clamp diode 23 and institute
State constant low level signal input part vgl electrical connection, its negative electrode p2 is electrically connected with described secondary trigger outfan next；Institute
The input stating the first phase inverter b1 is electrically connected with described secondary trigger outfan next, and its outfan is controlled with described first
Signal output part gtv electrical connection processed.
It should be noted that the anode p1 of clamp diode 23 is electrically connected with constant low level signal input part vgl, now
Clamp diode 23 is not turned on, and by its clamping action, its negative electrode p2 can be made to keep low level.Due to secondary trigger
Outfan next is electrically connected with the negative electrode p2 of clamp diode 23, and therefore, clamp diode 23 is used for making latch subelement initial
Secondary trigger outfan next during state keeps low level, and the first control signal outfan gtv keeps high level.
In fig. 3 a, clamp diode 23 is formed by nmos pipe nm1, and the grid of described nmos pipe nm1 is drained with it and is electrically connected
The source electrode of the anode p1 being connected together as clamp diode 23, described nmos pipe nm1 as the negative electrode of clamp diode 23, so
And this is only a specific example realizing clamp diode 23, in another specific example, clamp diode can also be by
Pmos pipe is formed, and the source electrode of described pmos pipe is drained with it and is electrically connected as the anode of clamp diode, the grid of described pmos pipe
The negative electrode being connected together as clamp diode.
Fig. 3 b is the sequential chart of the output signal of the input signal of each input and each outfan in Fig. 3 a.In fig 3b,
Sstv represents the trigger of trigger input stv input；Sckv1 represents the first clock signal input terminal ckv1 input
First clock signal；Snext represents the secondary trigger of secondary trigger outfan output；And sgtv represents the first control
First control signal of signal output part gtv output processed.And during the sequential shown in Fig. 3 b, constant low level signal is defeated
Enter to hold vgl persistently to keep inputting constant low level signal.Next just former to the work latching subelement in Fig. 3 a with reference to Fig. 3 b
Reason is described further.
Before further illustrating, to input signal and output signal be low level signal and high level signal does a letter
It is fixed to set up, and represents with 0 that input signal and output signal are low level signal, represent input signal and output signal with 1
For high level signal.Above-mentioned setting is equally applicable to each embodiment ensuing.
Sequential chart as shown in Figure 3 b, five moment of t1 to t5 are gradually increased successively.Before time tl, due to triggering letter
Number sstv is 0, and therefore, no matter the first clock signal sckv1 becomes 0 by 1, or becomes 1 by 0, and secondary trigger snext is still
So keep 0 during original state, the first control signal sgtv remains in that during original state 1.
In the t1 moment, trigger sstv becomes 1 by 0, and now the first clock signal sckv1 is 1, is 1 before the t1 moment
The first control signal sgtv be sent to the first input end of the first NAND gate nand1, then the first NAND gate nand1 output 0, the
Two NAND gate nand2 outputs 1；It is that 0 secondary trigger snext is sent to the of the 3rd NAND gate nand3 before the t1 moment
Two inputs, then the 3rd NAND gate nand3 output 1, the 4th NAND gate nand4 output 0, therefore in the t1 moment, secondary triggering letter
Number snext is 0, and the first control signal sgtv is 1.
Between the t1 moment to t2 moment, secondary trigger snext remains 0, and the first control signal sgtv remains
1.
In the t2 moment, the first clock signal sckv1 becomes 0 by 1, is that 1 the first control signal sgtv is sent out before the t2 moment
Deliver to the first input end of the first NAND gate nand1, then the first NAND gate nand1 output 1, the second NAND gate nand2 output 0；
Be that 0 secondary trigger snext is sent to the second input of the 3rd NAND gate nand3 before the t2 moment, then the 3rd with non-
Door nand3 output 1, the 4th NAND gate nand4 output 1, therefore in the t2 moment, secondary trigger snext becomes 1, first by 0
Control signal sgtv becomes 0 by 1.
Between the t2 moment to t3 moment, the first control signal sgtv that the t2 moment is 0 is sent to the first NAND gate
The first input end of nand1, then the first NAND gate nand1 output 1, the second NAND gate nand2 output 0；The t2 moment be 1 time
Level trigger snext is sent to the second input of the 3rd NAND gate nand3, then the 3rd NAND gate nand3 output 1, and the 4th
NAND gate nand4 output 1, therefore between the t2 moment to t3 moment, secondary trigger snext remains 1, and first controls letter
Number sgtv remains 0.
In the t3 moment, the first clock signal sckv1 becomes 1 by 0, is that 0 the first control signal sgtv is sent out before the t3 moment
Deliver to the first input end of the first NAND gate nand1, then the first NAND gate nand1 output 1, the second NAND gate nand2 output 0；
Be that 1 secondary trigger snext is sent to the second input of the 3rd NAND gate nand3 before the t3 moment, then the 3rd with non-
Door nand3 output 0, the 4th NAND gate nand4 output 1, therefore in the t3 moment, secondary trigger snext remains 1, first
Control signal sgtv remains 0.
Between the t3 moment to t4 moment, secondary trigger snext remains 1, and the first control signal sgtv remains
0.
In the t4 moment, trigger sstv becomes 0 by 1, is that 0 the first control signal sgtv is sent to the before the t4 moment
The first input end of one NAND gate nand1, then the first NAND gate nand1 output 1, the second NAND gate nand2 output 1；In t4
Before carving, secondary trigger snext for 1 is sent to the second input of the 3rd NAND gate nand3, then the 3rd NAND gate nand3
Output 0, the 4th NAND gate nand4 output 1, therefore in the t4 moment, secondary trigger snext remains 1, the first control signal
Sgtv remains 0.
In the t4 moment to t5 moment, secondary trigger snext is maintained as 1, and the first control signal sgtv is maintained as
0.
In the t5 moment, the first clock signal becomes 0 by 1, is that 0 the first control signal sgtv is sent to the before the t5 moment
The first input end of one NAND gate nand1, then the first NAND gate nand1 output 1, the second NAND gate nand2 output 1；In t5
Before carving, secondary trigger snext for 1 is sent to the second input of the 3rd NAND gate nand3, then the 3rd NAND gate nand3
Output 1, the 4th NAND gate nand4 output 0, therefore in the t5 moment, secondary trigger snext becomes 0 by 1, and first controls letter
Number sgtv becomes 1 by 0.
After the t5 moment, secondary trigger snext remains 0, and the first control signal sgtv remains 1.
By to the sequential chart shown in the description of operation principle latching subelement in Fig. 3 a and Fig. 3 b it follows that
In the t1 moment, although trigger sstv becomes 1 by 0, now latch secondary trigger snext of subelement generation still
For 0；In the t2 moment, the first clock signal sckv1 becomes 0 by 1 and trigger sstv remains as 1, now latches subelement quilt
Triggering, secondary trigger snext that it produces becomes 1 by 0；In the t3 moment, the first clock signal sckv1 is become 1 and touched by 0
Signalling sstv remains 1 and remains 1 in t4 moment first clock signal sckv1 and trigger sstv becomes 0 by 1,
Secondary trigger snext remains 1 accordingly；In the t5 moment, the first clock signal sckv1 becomes 0 and trigger by 1
Sstv remains 0, and now secondary trigger snext becomes 0 by 1.Therefore, after trigger sstv becomes 1 by 0, and
In the cycle of first clock signal sckv1 by 1 moment becoming 0 for first clock signal sckv1, even if in this week
Phase internal trigger signal sstv can become 0 by 1, and secondary trigger snext can be always maintained at exporting 1, and this shows to latch subelement
There is the function of latch.
Start to the t5 moment from the t2 moment in fig 3b, secondary trigger snext latching subelement generation is
1, the first control signal sgtv is 0, and by the setting to scanning signal generating subunit, is 0 in the first control signal sgtv
Time period in, can make and latch the scanning signal generating subunit that subelement electrically connects and produce scanning signal.
Merge, in order to match with the latch subelement in Fig. 3 a, the function of realizing driver element, as shown in fig. 4 a, drive single
Each scanning signal generating subunit in unit at least also includes a nor gate nori, first input of described nor gate nori
End is electrically connected with described scan clock signal input ckv2_i to receive one of described the second to the n-th clock signal clock
Signal, its second input is electrically connected with described first control signal input gtv2_i, its outfan and described scanning signal
Outfan gouti electrically connects to export one of described n scanning signal scanning signal.
Fig. 4 b is the sequential chart of the output signal of the input signal of each input and outfan in Fig. 4 a.In fig. 4b,
Sckv2i represents the i+1 clock signal of scan clock signal input ckv2_i input；Sgtv2i represents the first control signal
First control signal of input gtv2_i input；Sgouti represents the scanning signal of scanning signal outfan gouti output.As
Shown in Fig. 4 b, it is 0 and i+1 clock signal sgtv2i in the first control signal sgtv2i of input scanning signal generating subunit
During for 0, scanning signal sgouti of scanning signal generating subunit output is 1.That is, latch subelement in fig. 3 a
When the first control signal producing is 0, with the change of i+1 clock signal sgtv2i being applied to scanning signal generating subunit
Change, scanning signal generating subunit output scanning signal sgouti be 1, the scanning signal generating subunit in therefore Fig. 4 a and
Latch subelement in Fig. 3 a matches and is capable of the function of driver element.
Because the scanning signal that the scanning signal generating subunit in Fig. 4 a produces is weaker, therefore, in order to strengthen in Fig. 4 a
Scanning signal generating subunit produce scanning signal, as illustrated in fig. 4 c, on the basis of Fig. 4 a, each scanning signal produce
Subelement also includes 2m the second phase inverter (bi_1～bi_2m) being electrically connected in series, and m is the positive integer more than 0, wherein, the
The input of one the second phase inverter bi_1 is electrically connected with the outfan of described nor gate nori, 2m the second phase inverter bi_
The outfan of 2m is electrically connected with described scanning signal outfan gouti.It should be noted that due to the second phase inverter in Fig. 4 c
Number be even number, therefore, scanning signal outfan gouti output scanning signal AND OR NOT gate outfan output letter
Number there is identical level, and 2m the second phase inverter only plays and strengthen the effect of nor gate output signal that is to say, that this kind of
In the case of, the unlatching of the thin film transistor (TFT) in scanning signal and array base palte that the scanning signal generating subunit in Fig. 4 a produces
Required scanning signal in-phase signal each other.In actual design, can as needed the number of the second phase inverter be selected
Select.It is preferably and two the second phase inverters being electrically connected in series are set in each scanning signal generating subunit, so not only may be used
Enhanced effect is played with the output signal to nor gate, production cost can be reduced simultaneously and reduce setting the second phase inverter
Space.
However, can also be with the scanning in Fig. 4 a in the required scanning signal of the unlatching of the thin film transistor (TFT) on array base palte
The scanning signal inversion signal each other that signal generating subunit produces, in such cases, in order to strengthen the scanning signal in Fig. 4 a
The scanning signal that generating subunit produces, as shown in figure 4d, on the basis of Fig. 4 a, each scanning signal generating subunit also wraps
Include 2l-1 the second phase inverter (bi_1～bi_2l-1), wherein l is the positive integer more than 0；For l=1, each scanning signal
Generating subunit includes second phase inverter (for example, bi_1), the input of described second phase inverter and described nor gate
The outfan electrical connection of nori, the outfan of described second phase inverter is electrically connected with described scanning signal outfan gouti；For
L is more than 1, and each scanning signal generating subunit includes 2l-1 the second phase inverter being electrically connected in series, wherein, first second
The input of phase inverter bi_1 is electrically connected with the outfan of described nor gate nori, 2l-1 the second phase inverter bi_2l-1's
Outfan is electrically connected with described scanning signal outfan gouti.Due to sweeping produced by scanning signal generating subunit in Fig. 4 d
Retouch signal and scanning signal inversion signal each other produced by scanning signal generating subunit in Fig. 4 a, accordingly, with respect to Fig. 4 d institute
The waveform of the scanning signal producing, specifically may be referred to Fig. 4 b, will not be described here.Based on foregoing description, ensuing each
In individual embodiment, it is illustrated as a example the scanning signal generating subunit shown in by Fig. 4 c.
In embodiments of the present invention it is preferable that the waveform of described first clock signal and cycle and described the second to the (n+1)th
The waveform of clock signal and cycle phase with, and the time delay between described first clock signal and described second clock signal with
And the time delay between described (n+1)th clock signal and described first clock signal is equal to described the second to the (n+1)th clock letter
Time delay between two clocks of arbitrary neighborhood in number；Described first clock signal and described the second to the (n+1)th clock signal
Dutycycle be equal in a cycle pulse duration and (n+1) × (during described pulse duration+described delay
Between) ratio.
Next combine the circuit structure of above-mentioned latch subelement and scanning signal generating subunit, exemplarily provide one
The circuit structure of individual driver element, and to above-mentioned cycle with regard to the first clock signal and the second to the (n+1)th clock signal, pulse
Persistent period, time delay and dutycycle etc. are described further.As shown in Figure 5 a, the latch subelement in driver element and figure
Identical in 3a, will not be described here；Driver element includes three scanning signal generating subunit (corresponding n=3), each scanning
Signal generating subunit by a nor gate (for three scanning signal generating subunit be respectively nor1, nor2 and
Nor3) and two the second phase inverter compositions being electrically connected in series (are respectively b11 for three scanning signal generating subunit
With b12, b21 and b22 and b31 and b32), three scanning signal generating subunit corresponding three be used for receiving successively second to
Scan clock signal input ckv2_1, ckv2_2 and ckv2_3 of 4th clock signal, and correspond to three for defeated successively
Go out scanning signal outfan gout1, gout2 and gout3 of scanning signal.
Fig. 5 b is the sequential chart of the output signal of the input signal of each input and outfan in Fig. 5 a.In figure 5b,
Sstv represents the trigger of the trigger input stv input latching subelement；Sckv1 represents and latches the first of subelement
First clock signal of clock signal input terminal ckv1 input；Sgtv represents the first control signal outfan latching subelement
First control signal of gtv output；Sckv21, sckv22 and sckv23 represent sweeping of three scanning signal generating subunit respectively
Retouch the second to the 4th clock signal of clock signal input terminal ckv2_1, ckv2_2 and ckv2_3 input；Sgout1, sgout2 and
Sgout3 represents scanning signal outfan gout1, gout2 and gout3 output of three scanning signal generating subunit respectively
Scanning signal.
As shown in Figure 5 b, the cycle of the first clock signal sckv1 and the cycle of the second to the 4th clock signal are t, and
In a cycle t, the corresponding pulse duration is t1, and wherein, described pulse is 0 pulse；And first clock signal
Time delay between sckv1 and second clock signal sckv21, second clock signal sckv21 and the 3rd clock signal
Time delay between time delay between sckv22, the 3rd clock signal sckv22 and the 4th clock signal sckv23 and
Time delay between four clock signals sckv23 and the first clock signal sckv1 is t2, therefore, the first clock signal
The cycle t of sckv1 and second to the 4th clock signal can be expressed as: t=4t1+4t2, correspondingly, the first clock signal
The dutycycle of sckv1 and second to the 4th clock signal can be expressed as t1/t=t1/ (4t1+4t2), and that is, this dutycycle is equal to
The ratio of pulse duration t1 and 4 × (t2 time delay in pulse duration t1+) in a cycle.
By above-mentioned to the setting being applied to the first clock signal sckv1 latching subelement, and to three scanning letters
Number second clock signal sckv21, the 3rd clock signal sckv22 and the 4th clock signal sckv23 that generating subunit is applied
Setting, can make scanning signal sgout1, sgout2 of three scanning signal generating subunit output and the sgout3 be successively
1, therefore, based on to the analysis of Fig. 3 a, Fig. 4 a and Fig. 4 c and associated description, the driver element shown in Fig. 5 a can realize its work(
Can, that is, the driver element producing in scanning signal, and Fig. 5 a can be sequentially generated three scanning signals, with a driver element only
Produce a scanning signal to compare, the driver element that the present invention provides can improve the efficiency producing scanning signal.
It should be noted that Fig. 5 a is only about a specific example of driver element, with regard to its included scanning letter
In the number of number generating subunit and scanning signal generating subunit, the number of the second phase inverter, is not limited thereto.
The embodiment of the present invention also provides a kind of driving method of driver element, and described driving method is described in above-described embodiment
Driver element executing.Fig. 6 is a kind of schematic flow sheet of the driving method of driver element provided in an embodiment of the present invention.As
Shown in Fig. 6, described driving method includes:
Step 31, latch subelement produce secondary trigger and the first control according to trigger and the first clock signal
Signal；
Step 32, i-th scanning signal generating subunit are according to described first control signal receiving and i+1 clock
Signal is sequentially generated the corresponding scanning signal of described i-th scanning signal generating subunit, until all scanning signals produce son
Unit drives and finishes, and wherein i is the no more than positive integer of n.
With regard to the detailed description of above-mentioned steps 31 to step 32, the correlation that refer to above-described embodiment with regard to driver element is retouched
State, will not be described here.
The embodiment of the present invention also provides a kind of drive circuit.Fig. 7 a is a kind of drive circuit provided in an embodiment of the present invention
Structural representation.As shown in Figure 7a, including the driver element described in above-described embodiment of plural serial stage electrical connection, wherein, first
Trigger end stv1 in level driver element is electrically connected with the line trigger signal stv for providing trigger, arbitrary neighborhood
In two-stage drive unit, the secondary trigger outfan nextn of upper level driver element and the triggering of next stage driver element are believed
Number input stvn+1 electrical connection, wherein n is to connect the positive integer of series more than or equal to 1 and less than driver element, afterbody
The secondary trigger outfan of driver element is hanging.In figure 7 a, clk_1～n+1 represents n+1 bar and is used for applying clock signal
Clock cable, defeated with ckv1 the and n scan clock signal of the first clock signal input terminal in every grade of driver element respectively
Enter to hold ckv2_1～ckv2_n to electrically connect, for providing the first clock signal and the second to the (n+1)th clock signal；Gtvr represents every
First control signal outfan of the latch subelement in level driver element, wherein r is more than or equal to 1 and to be less than or equal to series-connected stage
The positive integer of number.
Specifically, in the drive circuit shown in Fig. 7 a, for first order driver element, clk_1 and this grade of driver element
In first clock signal input terminal ckv1 electrical connection, clk_2～clk_n+1 respectively with this grade of driver element in n scan
Clock signal input terminal ckv2_1～ckv2_n electrical connection；For second level driver element, in clk_n+1 and this grade of driver element
First clock signal input terminal ckv1 electrical connection, clk_1～clk_n respectively with this grade of driver element in n scan clock
Signal input part ckv2_1～ckv2_n electrical connection；When the series connection series of driver element is equal to 3, the third level is driven single
Unit, clk_n is electrically connected with the first clock signal input terminal ckv1 in this grade of driver element, clk_n+1 and this grade of driver element
First scan clock signal input ckv2_1 electrical connection, clk_1～clk_n-1 respectively with this grade of driver element in surplus
Remaining n-1 scan clock signal input ckv2_2～ckv2_n electrical connection；When the series connection series of driver element is more than 3, right
In j-th stage driver element, clk_n-j+3 is electrically connected with the first clock signal input terminal ckv1 in this grade of driver element, clk_
N-j+4 to clk_n+1 is electrically connected with scan clock signal input ckv2_1 to the ckv2_n-2 of this grade of driver element, clk_1
Electrically connect to clk_n-j+2 with scan clock signal input ckv2_j-1 to the ckv2_n of this grade of driver element, wherein, j is
Positive integer more than 3.
By applying the second to the (n+1)th clock signal it is ensured that every grade of driver element is defeated successively to every grade of driver element
Go out the scanning signal corresponding with the second to the (n+1)th clock signal；By above-mentioned to the first clock letter in driver elements at different levels
Number input and scan clock signal input are understood with the setting of clock cable, the first clock in next stage driver element
Signal input part is always electrically connected with the clock cable applying the (n+1)th clock signal to its upper level driver element, that is,
Say, when upper level driver element produces last scanning signal, the latch subelement in its next stage driver element can be driven
Start working, so can ensure that driver elements at different levels are sequentially output scanning signal, such that it is able to enable whole drive circuit
It is sequentially output scanning signal.
It should be noted that Fig. 7 a is only to schematically show to be made up of driving electricity the driver element in above-described embodiment
Road, in actual design, constituting the number of scanning signal generating subunit that each driver element of drive circuit includes can
With all equal it is also possible to the number of scanning signal generating subunit in part driver element equal it is also possible to whole drive single
The number of the scanning signal generating subunit in unit is all unequal, specifically can be selected according to practical situation, as long as can
Required drive circuit is constituted by the driver element in above-described embodiment, is not limited thereto.
Drive circuit adopts the driver element described in above-described embodiment, because each driver element can produce at least two
Scanning signal is that is to say, that setting latch subelement in the driving unit can drive at least two scanning signals to produce son
Unit simultaneously produces the scanning signal of respective numbers.The driver element adopting with drive circuit can only produce one for each grid unit
Individual scanning signal often produces scanning signal and is accomplished by one and latches subelement comparing, the driving electricity of technical solution of the present invention
Less latch subelement can be set in road, the power consumption of drive circuit not only can be reduced, drive circuit can also be reduced and account for
Space.Additionally, the driving compared with only needing to the drive circuit that two clock signals to drive, in technical solution of the present invention
Circuit at least needs three clock signals to drive, and therefore, in drive circuit works, can reduce the frequency of clock signal,
Such that it is able to reduce electromagnetic interference produced by clock signal.
Next provide an example operation principle of the drive circuit in Fig. 7 a to be described.Assume the driving electricity in Fig. 7 a
Road has the driver element of thtee-stage shiplock electrical connection, and every grade of driver element includes three scanning signal generating subunit.As figure
Shown in 7b, drive circuit has the driver element of thtee-stage shiplock electrical connection, and every grade of driver element includes three scanning signals and produces
Raw subelement, wherein, latches subelement and scanning signal generating subunit all using shown in Fig. 5 a in every grade of driver element
Latch subelement in driver element and scanning signal generating subunit；Include three scanning signals based on every grade of driver element to produce
Raw subelement understands, whole drive circuit needs the first clock signal and the second to the 4th clock signal, is used for by 4 of in figure
Clock cable clk_1～4 applying clock signal providing, wherein, the first clock signal input of first order driver element
End ckv1 is electrically connected with first clock cable clk_1, three scan clock signal inputs of first order driver element
Ckv2_1, ckv2_2 and ckv2_3 respectively with Article 2 clock cable clk_2, Article 3 clock cable clk_3 and the 4th
Bar clock cable clk_4 electrically connects；First clock signal input terminal ckv1 of second level driver element is believed with Article 4 clock
Number line clk_4 electrical connection, three scan clock signals input ckv2_1, ckv2_2 and ckv2_3 of second level driver element divide
Do not electrically connect with first clock cable clk_1, Article 2 clock cable clk_2 and Article 3 clock cable clk_3；
First clock signal input terminal ckv1 of third level driver element is electrically connected with Article 3 clock cable clk_3, and the third level drives
Three scan clock signals input ckv2_1, ckv2_2 and ckv2_3 of moving cell respectively with Article 4 clock cable clk_
4th, first clock cable clk_1 and Article 2 clock cable clk_2 electrical connection.By above-mentioned in driver elements at different levels
The first clock signal input terminal and the setting of scan clock signal input and clock cable understand, next stage driver element
In the first clock signal input terminal always with to its upper level driver element apply the 4th clock signal clock cable electricity
Connect that is to say, that when upper level driver element produces last scanning signal, can drive in its next stage driver element
Latch subelement to start working, so can ensure that driver elements at different levels are sequentially output scanning signal, such that it is able to make entirely to drive
Galvanic electricity road can be sequentially output scanning signal.
Fig. 7 c is the sequential chart of the output signal of the input signal of each input of drive circuit in Fig. 7 b and each outfan.
In figure 7 c, sstv represents the trigger of line trigger signal stv offer；Sclk1～sclk4 represents 4 clock cables
The clock signal that clk_1～clk_4 provides successively；Sgtv1, sgtv2 and sgtv3 represent in first order driver element respectively
The first control signal outfan in first control signal of one control signal outfan gtv1 generation, second level driver element
The first control that the first control signal outfan gtv3 in the first control signal and third level driver element that gtv2 produces produces
Signal processed；Snext1, snext2 and snext3 represent the secondary trigger outfan next1 in first order driver element respectively
The secondary triggering letter that secondary trigger outfan next2 in the secondary trigger of generation, second level driver element produces
Number and third level driver element in secondary trigger outfan next3 generation secondary trigger；Sgout1～
Sgout9 represents nine scanning signals of drive circuit output.Based on to the analysis of Fig. 5 a and Fig. 5 b and associated description and to figure
The explanation of 7b, knowable to Fig. 7 c, the drive circuit shown in Fig. 7 b can be realized being sequentially output the work(of required scanning signal
Energy.
The embodiment of the present invention also provides a kind of array base palte.Fig. 8 is a kind of array base palte provided in an embodiment of the present invention
Structural representation.As shown in figure 8, array base palte includes gate driver circuit 41, data drive circuit 42, a plurality of data lines (Fig. 8
Shown in d1, d2 ..., dk), multi-strip scanning line (s1 shown in Fig. 8, s2 ..., sm) and by a plurality of data lines and a plurality of sweep
Retouch line and intersect the multiple pixel cells 43 limiting, wherein pixel cell 43 includes thin film transistor (TFT) 431 and the picture being connected electrically
Plain electrode 432, wherein gate driver circuit 41 are the drive circuit described in above-described embodiment.
Specifically, gate driver circuit 41, for each bar scan line (s1, s2 ..., sm) provide scanning signal, its
In, each scanning signal outfan of the scanning signal generating subunit in gate driver circuit 41 electrically connects a scan line；
Data drive circuit 42, for pieces of data line (d1, d2 ..., dk) provide data signal；Thin film in pixel cell 43
The grid of transistor 431 is electrically connected with a scan line, and the source electrode of thin film transistor (TFT) 431 is electrically connected with a data line, thin film
The drain electrode of transistor 431 and the pixel electrode 432 being located in same pixel cell 43 with it are electrically connected, and what scan line provided sweeps
Retouch signal and can control being turned on or off of thin film transistor (TFT) 431, the data signal that data wire provides can be by unlatching
Thin film transistor (TFT) 431 is sent to pixel electrode 432, such that it is able to realize showing corresponding display picture.
Because the gate driver circuit in array base palte adopts the drive circuit described in above-described embodiment, and this driving electricity
The space that road takies is less, and therefore, the frame region arranging the array base palte of this drive circuit can be less, such that it is able to favourable
Easily realize narrow frame in making array base palte.Further, since above-mentioned drive circuit can reduce electricity produced by clock signal
Magnetic disturbance, therefore, the array base palte in the present embodiment also has same effect.
The embodiment of the present invention also provides a kind of display floater.Fig. 9 is a kind of display floater provided in an embodiment of the present invention
Structural representation.Referring to Fig. 9, display floater include array base palte 52 that counter substrate 51 is oppositely arranged with counter substrate 51,
Intermediate layer 53 between counter substrate 51 and array base palte 52.Wherein, array base palte 52 is the array base described in above-described embodiment
Plate.
Specifically, intermediate layer 53 is relevant with the display type of display floater.When using liquid crystal display, intermediate layer 53 is liquid
Crystal layer, counter substrate 51 can be color membrane substrates, by the public electrode that is arranged in counter substrate 31 be arranged on array base
The electric field (corresponding twisted nematic) that formed between pixel electrode in plate 52 or by being arranged on the public affairs in array base palte 52
The electric field (corresponding edge field switch type or plane conversion type) being formed between common electrode and pixel electrode is controlling in liquid crystal layer
Liquid crystal molecule rotation, thus realizing display effect.
When being shown using Organic Light Emitting Diode (organic light-emitting diode, abbreviation oled), in
Interbed 53 is used for arranging organic luminous layer, and counter substrate 51 can be color membrane substrates, packaged glass (cover glass) or lid
Glass sheet (cover lens) etc., controls organic luminous layer to light to realize display effect by array base palte 52.
Because display floater employs the array base palte described in above-described embodiment, therefore, display floater not only can hold
Easily realize narrow frame it is also possible to reduce the electromagnetic interference produced by clock signal driving drive circuit.
Driver element provided in an embodiment of the present invention and its driving method, drive circuit, array base palte and display floater, lead to
Cross in the driving unit setting latch subelement and with latch the corresponding n scanning signal generating subunit of subelement, n is big
In 1 positive integer, wherein each scanning signal generating subunit can produce a scanning signal, due to a latch subelement
N scanning signal generating subunit can be driven and produce n scanning signal, therefore, so not only can reduce this drive of application
The power consumption of the drive circuit of moving cell, can also reduce the space of drive circuit occupancy, such that it is able to make this drive circuit of application
Array base palte and display floater easily realize narrow frame；Additionally, drive circuit is by the first clock signal and the second to the (n+1)th
Clock signal, to drive, to be driven by n+1 clock signal therefore, when grid circuit works, can reduce clock signal
Frequency, such that it is able to reduce the electromagnetic interference that clock signal array substrate and display floater produce.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (11)
1. a kind of driver element is it is characterised in that include: latches subelement, and sweeps with described corresponding n of the subelement that latches
Retouch signal generating subunit, n is the positive integer more than 1, wherein,
Described latch subelement is used for producing secondary trigger and the first control letter according to trigger and the first clock signal
Number, described latch subelement include trigger input, the first clock signal input terminal, secondary trigger outfan and
First control signal outfan；
When described n scanning signal generating subunit is used for according to described first control signal receiving and the second to the (n+1)th
Clock signal is sequentially generated n scanning signal, and wherein, i+1 clock signal is used for controlling i-th scanning signal generating subunit to produce
Raw scanning signal, i is the no more than positive integer of n, and each described scanning signal generating subunit to include the first control signal defeated
Enter end, scan clock signal input and scanning signal outfan；
Described the first control signal outfan latching subelement electrically connects corresponding described n scanning signal generating subunit
First control signal input.
2. driver element according to claim 1 it is characterised in that described latch subelement also include the first NAND gate,
Second NAND gate, the 3rd NAND gate, the 4th NAND gate, clamp diode, the first phase inverter and constant low level signal input part；
The first input end of described first NAND gate is electrically connected with described first control signal outfan, its second input and institute
State the first clock signal input terminal electrical connection, its outfan is electrically connected with the second input of described second NAND gate；
The first input end of described second NAND gate is electrically connected with described trigger input, its outfan with the described 4th with
The first input end electrical connection of not gate；
The first input end of described 3rd NAND gate is electrically connected with described first clock signal input terminal, its second input and institute
State secondary trigger outfan electrical connection, its outfan is electrically connected with the second input of described 4th NAND gate；
The outfan of described 4th NAND gate is electrically connected with described secondary trigger outfan；
The anode of described clamp diode is electrically connected with described constant low level signal input part, and its negative electrode is triggered with described secondary
Signal output part electrically connects；
The input of described first phase inverter is electrically connected with described secondary trigger outfan, and its outfan is controlled with described first
Signal output part electrical connection processed.
3. driver element according to claim 2 is it is characterised in that described clamp diode is formed by nmos pipe, described
The grid of nmos pipe is drained with it and is electrically coupled together as the anode of described clamp diode, the source electrode conduct of described nmos pipe
The negative electrode of described clamp diode；Or
Described clamp diode is formed by pmos pipe, and the source electrode of described pmos pipe is as the anode of described clamp diode, described
The grid of pmos pipe is drained with it and is electrically coupled together as the negative electrode of described clamp diode.
4. driver element according to claim 1 and 2 is it is characterised in that each scanning signal generating subunit is at least gone back
Including a nor gate；
The first input end of described nor gate is electrically connected with described scan clock signal input to receive described the second to the (n+1)th
One of clock signal clock signal, its second input is electrically connected with described first control signal input, its outfan
Electrically connect with described scanning signal outfan to export one of described n scanning signal scanning signal.
5. driver element according to claim 4 is it is characterised in that each scanning signal generating subunit also includes 2l-1
Individual second phase inverter, wherein l is the positive integer more than 0；
For l=1, each scanning signal generating subunit includes second phase inverter, the input of described second phase inverter
Electrically connect with the outfan of described nor gate, the outfan of described second phase inverter is electrically connected with described scanning signal outfan；
1 is more than for l, each scanning signal generating subunit includes 2l-1 the second phase inverter being electrically connected in series, wherein, the
The input of one the second phase inverter is electrically connected with the outfan of described nor gate, the outfan of 2l-1 the second phase inverter with
Described scanning signal outfan electrical connection.
6. driver element according to claim 4 is it is characterised in that each scanning signal generating subunit also includes 2m
The second phase inverter being electrically connected in series, m is the positive integer more than 0, wherein, the input of first the second phase inverter with described or
The outfan electrical connection of not gate, the outfan of 2m the second phase inverter is electrically connected with described scanning signal outfan.
7. driver element according to claim 1 is it is characterised in that the waveform of described first clock signal and cycle and institute
State the waveform of the second to the (n+1)th clock signal and cycle phase with, and described first clock signal and described second clock signal it
Between time delay and described (n+1)th clock signal and described first clock signal between time delay be equal to described second
The time delay between two clock signals of arbitrary neighborhood to the (n+1)th clock signal；
The dutycycle of described first clock signal and described the second to the (n+1)th clock signal is equal to pulse in a cycle and holds
Continuous time and the ratio in (n+1) × (described pulse duration+described time delay).
8. a kind of driving method of driver element, driver element any one of claim 1-7 for the described driving method
To execute it is characterised in that described driving method includes:
Latch subelement and secondary trigger and the first control signal are produced according to trigger and the first clock signal；
I-th scanning signal generating subunit produces successively according to described first control signal receiving and i+1 clock signal
The raw corresponding scanning signal of described i-th scanning signal generating subunit, until all scanning signal generating subunit have driven
Finish.
9. a kind of drive circuit it is characterised in that include plural serial stage electrical connection as any one of claim 1-7
Driver element, wherein, in arbitrary neighborhood two-stage drive unit the secondary trigger outfan of upper level driver element and next
The trigger input electrical connection of level driver element.
10. a kind of array base palte, handed over including a plurality of data lines, multi-strip scanning line and by described a plurality of data lines and multi-strip scanning line
Multiple pixel cells that fork limits, wherein said pixel cell includes thin film transistor (TFT) and the pixel electrode being connected electrically, its
It is characterised by, also includes drive circuit as claimed in claim 9, wherein, the scanning signal in described drive circuit produces son
Each scanning signal outfan of unit electrically connects a scan line.
A kind of 11. display floaters are it is characterised in that include array base palte as claimed in claim 10.
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| CN106843584A (en) * | 2017-01-23 | 2017-06-13 | 武汉华星光电技术有限公司 | A kind of contact panel |
| CN107329612B (en) | 2017-06-29 | 2020-04-21 | 上海天马微电子有限公司 | Scanning circuit, driving circuit and touch display device |
| CN109686296B (en) * | 2019-03-05 | 2022-05-20 | 合肥鑫晟光电科技有限公司 | Shift register module, driving method and grid driving circuit |
| CN110969999B (en) * | 2019-11-25 | 2021-09-07 | 厦门天马微电子有限公司 | Electromagnetic interference weakening circuit, display panel and display device |
| CN110751929B (en) | 2019-11-29 | 2022-12-02 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111754916B (en) * | 2020-07-09 | 2021-07-23 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
| CN112530350B (en) * | 2020-12-18 | 2023-07-18 | 厦门天马微电子有限公司 | Display panel and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202196566U (en) * | 2011-09-21 | 2012-04-18 | 京东方科技集团股份有限公司 | Shift register and grid drive device thereof |
| CN103985361A (en) * | 2013-10-11 | 2014-08-13 | 厦门天马微电子有限公司 | Grid driving circuit and control method thereof, and liquid crystal display |
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| TWI284876B (en) * | 2002-08-19 | 2007-08-01 | Toppoly Optoelectronics Corp | Device and method for driving liquid crystal display |
| KR100969773B1 (en) * | 2008-07-04 | 2010-07-13 | 삼성모바일디스플레이주식회사 | Scan driver and organic light emitting display using the same |
-
2014
- 2014-12-04 CN CN201410733496.3A patent/CN104392687B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202196566U (en) * | 2011-09-21 | 2012-04-18 | 京东方科技集团股份有限公司 | Shift register and grid drive device thereof |
| CN103985361A (en) * | 2013-10-11 | 2014-08-13 | 厦门天马微电子有限公司 | Grid driving circuit and control method thereof, and liquid crystal display |
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