CN103474044B

CN103474044B - A kind of gate driver circuit, array base palte, display device and driving method

Info

Publication number: CN103474044B
Application number: CN201310455250.XA
Authority: CN
Inventors: 徐帅; 王智勇; 朱红; 张郑欣
Original assignee: Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2013-09-29
Filing date: 2013-09-29
Publication date: 2016-01-27
Anticipated expiration: 2033-09-29
Also published as: CN103474044A

Abstract

The embodiment of the invention discloses a kind of gate driver circuit, array base palte, display device and driving method, for solving the existing gate driver circuit problem that operationally power consumption is large.Gate driver circuit of the present invention comprises at least one electronic circuit, arbitrary electronic circuit comprises M shift register cell, M be not less than 3 positive integer, wherein: in arbitrary electronic circuit, for drive the shift register cell of odd-numbered line signal line be successively connected and the output terminal of upper level shift register cell be connected with the input end of next stage shift register cell, for drive the shift register cell of even number line signal line be successively connected and the output terminal of upper level shift register cell be connected with the input end of next stage shift register cell.Under the prerequisite ensureing display quality, reduce power consumption.

Description

Grid driving circuit, array substrate, display device and driving method

Technical Field

The invention relates to the technical field of display, in particular to a gate driving circuit and an array substrate comprising the same. A display device and a driving method.

Background

In recent years, with the rapid development of display technology, Flat Panel Displays (FPDs) have been developed to meet the trend of future image display devices, which have the characteristics of complete planarization, light weight, thin thickness, and power saving. Currently, common flat panel display devices include a Plasma Display Panel (PDP), a Liquid Crystal Display (LCD), a Field Emission Display (FED), an organic light-emitting diode (OLED) display device, a projection display device, and the like.

In the field of flat panel display, the LCD is called as a flat panel display device with the fastest development, the most mature technology and the most extensive application because of its characteristics of light weight, small volume, thin thickness and the like. As shown in fig. 1, the driving circuit of the conventional liquid crystal display device is composed of a gate driving circuit 11 and a source driving circuit 12, wherein the gate driving circuit 11 is used for generating a gate pulse signal to gate a gate line in a horizontal direction, and the source driving circuit 12 is used for generating a data signal to write a voltage corresponding to a gray scale into a source line in a vertical direction, so that the deflection of liquid crystal molecules is changed accordingly, thereby realizing display of different gray scales. In most of the conventional LCDs, the gate driving circuit 11 and the source driving circuit 12 are disposed outside the display panel and are connected to the display panel 13 through cof (chip on film). However, the above-described driving circuit is relatively expensive in design.

In order to further save the cost, especially the COF, a technology of fabricating a gate driving circuit composed of a shift register on a substrate of a display panel, i.e., a Gate In Panel (GIP) technology, is developed. In the conventional GIP-type display device, a progressive scanning mode is adopted for gate signal lines, a Thin Film Transistor (TFT) switch connected with each row of gate signal lines is sequentially turned on, gray scale signals with different polarities are applied to any adjacent data signal lines, namely, the source output is a 1-point inversion mode, so that the polarity of voltage stored in each pixel point is opposite to the polarity of pixels adjacent to the pixel points in the vertical and horizontal directions, namely, a 1-point inversion display effect is achieved.

Disclosure of Invention

The embodiment of the invention provides a gate driving circuit, an array substrate comprising the gate driving circuit, a display device and a driving method, which are used for solving the problem that the whole power consumption of the display device is large when the conventional gate driving circuit works.

The embodiment of the invention provides a gate driving circuit, which comprises at least one sub-circuit, wherein the sub-circuit comprises M shift register units, each shift register unit is used for driving a different gate signal line, M is a positive integer not less than 3, and the gate driving circuit comprises:

in the sub-circuit, the shift register units for driving odd-numbered gate signal lines are sequentially connected, the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage, the shift register units for driving even-numbered gate signal lines are sequentially connected, and the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage;

after the shift register unit for driving the odd-numbered gate signal lines sequentially applies gate scanning signals to at least two gate signal lines, the shift register unit for driving the even-numbered gate signal lines sequentially applies gate scanning signals to the gate signal lines; or after the shift register unit driving the even-numbered gate signal lines sequentially applies the gate scanning signals to at least two gate signal lines, the shift register unit driving the odd-numbered gate signal lines sequentially applies the gate scanning signals to the gate signal lines.

In an implementation, the gate drive circuit, when in operation, for any of the sub-circuits:

firstly starting the shift register unit started to drive the grid signal lines in the odd rows and then starting the shift register unit used for driving the grid signal lines in the even rows; or,

the shift register units started to drive the even-numbered grid signal lines are started first, and then the shift register units used for driving the odd-numbered grid signal lines are started.

In an implementation, the gate driving circuit includes at least two sub-circuits, and an output terminal of a last turned-on shift register cell in a previous sub-circuit is connected to an input terminal of a first turned-on shift register cell in a next sub-circuit.

In the embodiment of the invention, in the gate driving circuit, an input end of a shift register unit for driving a first odd-numbered gate signal line is connected with a first frame starting signal, and/or an input end of a shift register unit for driving a first even-numbered gate signal line is connected with a second frame starting signal;

in any sub-circuit, the clock signal input ends of the shift register units for driving the odd-numbered gate signal lines are connected with different clock control signals, and the clock control signals connected with each shift register unit are sequentially output in a pulse period, so that the shift register units for driving the odd-numbered gate signal lines sequentially generate gate scanning signals; the clock signal input ends of the shift register units for driving the even-numbered gate signal lines are connected with different clock control signals, and the clock control signals connected with each shift register unit are sequentially output in one pulse period, so that the shift register units for driving the odd-numbered gate signal lines sequentially generate gate scanning signals.

In the embodiment of the present invention, the output terminal of the last activated shift register unit in the previous sub-circuit is connected to the input terminal of the first activated shift register unit in the next sub-circuit, which specifically includes:

if the mode of starting the shift register unit for driving the odd-numbered row gate signal lines and then starting the shift register unit for driving the even-numbered row gate signal lines is started, then: the output end of the shift register unit in the last sub-circuit for driving the last even-numbered gate signal line is connected with the input end of the shift register unit in the next sub-circuit for driving the first odd-numbered gate signal line;

if the mode of starting the shift register unit for driving the even-numbered row gate signal lines and then starting the shift register unit for driving the odd-numbered row gate signal lines is started, then: the output end of the shift register unit used for driving the last odd-numbered gate signal line in the previous sub-circuit is connected with the input end of the shift register unit used for driving the first even-numbered gate signal line in the next sub-circuit.

In the gate driving circuit of the embodiment of the invention, the shift register units of any sub-circuit for driving the odd-numbered gate signal lines are sequentially connected, the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage, the shift register units for driving the even-numbered gate signal lines are sequentially connected, and the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage; after the shift register unit for driving the odd-numbered gate signal lines sequentially applies gate scanning signals to at least two gate signal lines, the shift register unit for driving the even-numbered gate signal lines sequentially applies gate scanning signals to the gate signal lines; or after the shift register unit driving the even-numbered gate signal lines sequentially applies the gate scanning signals to at least two gate signal lines, the shift register unit driving the odd-numbered gate signal lines sequentially applies the gate scanning signals to the gate signal lines.

Therefore, when the gate driving circuit provided by the embodiment of the invention is used to drive the gate signal lines, the same data signal line is applied with the gray scale signal with the same polarity (denoted as the first polarity) when the gate signal lines in different odd-numbered rows are scanned, and the same data signal line is applied with the gray scale signal with the second polarity opposite to the first polarity when the gate signal lines in different even-numbered rows are scanned, so that the source output is in the multi-point inversion mode, while the same data signal line is applied with the gray scale signal with the same polarity (denoted as the first polarity) and any two adjacent data signal lines are applied with the gray scale signals with different polarities when the gate signal lines in different odd-numbered rows are scanned, and the same data signal line is applied with the gray scale signal with the second polarity opposite to the first polarity and any two adjacent data signal lines are applied with the gray scale signals with different polarities when the gate signal lines in different even-numbered rows are scanned, the polarity of the voltage stored in each pixel point is opposite to the polarities of the pixels adjacent to the pixel points up, down, left and right, namely the display effect of 1-point overturning is achieved, and therefore the overall power consumption is reduced on the premise that the display quality is guaranteed.

Based on the gate driving circuit, an embodiment of the invention further provides an array substrate, which includes the gate driving circuit.

In order to reduce the width of the left and right frames of the display device, it is preferable that, in the gate driving circuit, all the shift register units for driving the odd-numbered gate signal lines are located on one side of the region where the gate signal lines are located, and all the shift register units for driving the even-numbered gate signal lines are located on the other side of the region where the gate signal lines are located.

In the array substrate of the embodiment of the invention, for the gate signal lines connected with any sub-circuit, the odd-numbered row gate signal lines can be scanned first, then the even-numbered row gate signal lines can be scanned, or the even-numbered row gate signal lines can be scanned first, then the odd-numbered row gate signal lines can be scanned, so that the source output is in a multi-point turnover mode, and the display effect of 1-point turnover is achieved, thereby reducing the overall power consumption on the premise of ensuring the display quality.

Based on the array substrate, the embodiment of the invention also provides a display device, which comprises the array substrate.

According to the display device provided by the embodiment of the invention, in the process of displaying the picture, the source output of the display device is in the multi-point overturning mode, so that the display effect of 1-point overturning is achieved, and the overall power consumption is reduced on the premise of ensuring the display quality.

Based on the display device, an embodiment of the present invention further provides a driving method, including:

for a grid signal line connected with any sub circuit in a grid driving circuit of the display device, sequentially applying grid scanning signals to odd-numbered grid signal lines, applying gray scale signals with the same polarity to the same data signal line, applying gray scale signals with different polarities to any two adjacent data signal lines, sequentially applying grid scanning signals to even-numbered grid signal lines, applying gray scale signals with the same polarity to the same data signal line, and applying gray scale signals with different polarities to any two adjacent data signal lines, wherein when any adjacent odd-numbered grid signal line and any adjacent even-numbered grid signal line are scanned, the polarities of the gray scale signals applied to the same data signal line are opposite; or,

for the grid signal lines connected with any sub circuit in the grid driving circuit of the display device, grid scanning signals are sequentially applied to grid signal lines in even rows, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to any two adjacent data signal lines, grid scanning signals are sequentially applied to grid signal lines in odd rows, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to any two adjacent data signal lines, and when any two adjacent odd-row grid signal lines and any two adjacent even-row grid signal lines scan, the polarities of the gray scale signals applied to the same data signal line are opposite.

For a gate signal line to which any one of the sub-circuits in the display device is connected, further, the driving method further includes:

if grid scanning signals are sequentially applied to the grid signal lines of odd rows and then the grid scanning signals are sequentially applied to the grid signal lines of even rows, the source driving circuit in the display device sequentially stores gray scale signals of pixel points on the odd rows and then sequentially stores gray scale signals of pixel points on the even rows;

if grid scanning signals are sequentially applied to the grid signal lines of the even rows and then the grid scanning signals are sequentially applied to the grid signal lines of the odd rows, the source driving circuit in the display device sequentially stores gray scale signals of pixel points on the even rows and then sequentially stores gray scale signals of pixel points on the odd rows.

As a preferable driving timing, pulse durations of pulse signals output from different shift register units in any one of sub-circuits of a gate driving circuit of the display device do not overlap within one image frame.

As another preferable driving timing, in one image frame, pulse durations of pulse signals output by two adjacent cascaded shift register units in any one sub-circuit of the gate driving circuit of the display device have an overlapping portion, so as to realize a charging process for pixels.

In the driving method provided by the embodiment of the invention, for any gate signal line connected to any sub-circuit, the odd-numbered gate signal lines may be scanned first, then the even-numbered gate signal lines may be scanned first, then the odd-numbered gate signal lines may be scanned, since gray scale signals of the same polarity (denoted as a first polarity) are applied to the same data signal line when different odd-numbered gate signal lines are scanned, and gray scale signals of a second polarity opposite to the first polarity are applied to the same data signal line when different even-numbered gate signal lines are scanned, the source output is in a multi-point inversion mode, and since gray scale signals of the same polarity (denoted as a first polarity) are applied to the same data signal line and gray scale signals of different polarities are applied to any two adjacent data signal lines when different odd-numbered gate signal lines are scanned, the gray scale signals of the second polarity opposite to the first polarity are applied to the same data signal line, and the gray scale signals of different polarities are applied to any two adjacent data signal lines, so that the polarity of the voltage stored by each pixel point is opposite to the polarity of the pixels adjacent to the pixel point up, down, left and right, that is, the display effect of 1-point overturning is achieved, and the overall power consumption is reduced on the premise of ensuring the display quality.

Drawings

FIG. 1 is a diagram of a gate driving circuit of a conventional LCD device in the prior art;

fig. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 3 is a diagram of a shift register unit according to an embodiment of the present invention;

fig. 4 is an input timing diagram of a first sub-circuit of a gate driving circuit according to a first embodiment of the present invention;

FIG. 5 is a timing diagram of the output of the first sub-circuit of the gate driving circuit according to the first embodiment of the present invention;

FIG. 6 is a schematic diagram of pixel data displayed on an LCD panel according to a first embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a pixel data storage format of a source circuit according to a first embodiment of the present invention;

fig. 8 is an input timing diagram of a first sub-circuit of a gate driving circuit according to a second embodiment of the present invention;

fig. 9 is an output timing diagram of the first sub-circuit of the gate driving circuit according to the second embodiment of the present invention.

Detailed Description

According to the invention, the even-numbered row grid signal lines and the odd-numbered row grid signal lines are respectively scanned, so that the source output is in a multi-point overturning mode, the display effect of 1-point overturning is achieved, and the power consumption of the display device is reduced on the premise of ensuring the quality of a display picture.

The embodiments of the present invention will be described in further detail with reference to the drawings attached hereto.

The gate driving circuit provided by the embodiment of the present invention includes at least one sub-circuit, where any sub-circuit includes M shift register units, each shift register unit is used to drive a different gate signal line, and M is a positive integer not less than 3, where:

in any sub-circuit, the shift register units for driving the odd-numbered gate signal lines are sequentially connected, the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage, the shift register units for driving the even-numbered gate signal lines are sequentially connected, and the output end of the shift register unit at the upper stage is connected with the input end of the shift register unit at the lower stage;

Preferably, in a predetermined time, after the shift register unit driving the odd-numbered gate signal lines in any sub-circuit sequentially applies the gate scanning signals to the correspondingly connected gate signal lines, the shift register unit driving the even-numbered gate signal lines sequentially applies the gate scanning signals to the gate signal lines. For example: the predetermined time is 1/2,1/4,1/8.

Preferably, the number of shift register units driving odd-numbered row gate signal lines in any sub-circuit may be the same as the number of shift register units driving odd-numbered row gate signal lines. For example, the sub-circuit includes 1/2,1/4,1/8, which is the number of shift register units of the total number of gate signal lines.

For example, assuming that each sub-circuit includes 8 shift register units, the shift register units in the first sub-circuit for driving the odd-numbered gate signal lines are connected in sequence, that is, the output terminal of the shift register unit for driving the first row of gate signal lines (i.e., the first shift register unit) is connected to the input terminal of the shift register unit for driving the third row of gate signal lines (i.e., the third shift register unit), the output terminal of the third shift register unit is connected to the input terminal of the fifth shift register unit, and the output terminal of the fifth shift register unit is connected to the input terminal of the seventh shift register unit; the shift register units in the first sub-circuit for driving even-numbered gate signal lines are sequentially connected, that is, the output end of the shift register unit for driving the second-row gate signal line (namely, the second shift register unit) is connected with the input end of the shift register unit for driving the fourth-row gate signal line (namely, the fourth shift register unit), the output end of the fourth shift register unit is connected with the input end of the sixth shift register unit, and the output end of the sixth shift register unit is connected with the input end of the eighth shift register unit;

if the shift register unit started for driving the odd-numbered gate signal line is started first and then the shift register unit used for driving the even-numbered gate signal line is started, the output end of the eighth shift register unit in the first sub-circuit is connected with the input end of the first shift register unit in the second sub-circuit, so that the output signal of the last started shift register unit in the first sub-circuit is used as the frame starting signal of the first started shift register unit in the second sub-circuit;

if the shift register unit started for driving the even-numbered gate signal line is started first and then the shift register unit used for driving the odd-numbered gate signal line is started, the output end of the seventh shift register unit in the first sub-circuit is connected with the input end of the second shift register unit in the second sub-circuit, so that the output signal of the last started shift register unit in the first sub-circuit is used as the frame starting signal of the first started shift register unit in the second sub-circuit;

since the connection manner of the shift register units in other sub-circuits is the same, it is not illustrated here.

In the embodiment of the invention, the total number of the shift register units included in the gate driving circuit is equal to the total number of the gate signal lines, and each shift register unit is used for driving a different gate signal line.

Optionally, the gate driving circuit includes at least two sub-circuits, and an output terminal of a last turned-on shift register unit in a previous sub-circuit is connected to an input terminal of a first turned-on shift register unit in a next sub-circuit.

Specifically, the first shift register unit in the first sub-circuit drives a first row gate signal line, the second shift register unit drives a second row gate signal line, … …, the mth shift register unit drives an mth row gate signal line, the first shift register unit in the M +1 sub-circuit drives an M +1 row gate signal line, the M +2 shift register unit drives an M +2 row gate signal line, … …, the 2 mth shift register unit drives a 2 mth row gate signal line, and so on.

In the embodiment of the present invention, the number of the shift register units included in each sub-circuit may be the same or different, and as long as at least three shift register units are included in each sub-circuit, the source output can be in a multi-point flip mode, so as to achieve the effect of reducing power consumption.

Preferably, each sub-circuit of the gate driving circuit includes the same number of shift register units for design convenience.

Furthermore, each sub-circuit of the gate driving circuit comprises 2N shift register units, where N is a positive integer not less than 2. For example, 4, 8 or 16 shift register cells may be included in each sub-circuit.

It should be noted that, the more the number of shift register units included in each sub-circuit is, the more the power consumption is reduced, however, the more the number of shift register units included in each sub-circuit is, the more the wiring (such as clock control signal lines) required by the gate driving circuit is, and accordingly, the larger the space occupied by the wiring of the gate driving circuit is, and the width of the left and right frames of the display device is increased because the gate driving circuit is generally located at the frame position of the display device.

In the embodiment of the present invention, when the gate driving circuit operates, any one of the following manners may be adopted for any one of the sub-circuits in the gate driving circuit:

in the first mode, the shift register unit for driving the odd-numbered gate signal lines is turned on first, and then the shift register unit for driving the even-numbered gate signal lines is turned on.

Specifically, in this way, first, the shift register units in the first sub-circuit, which are used for driving the odd-numbered gate signal lines, are turned on, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be turned on; then, the shift register units in the first sub-circuit, which are used for driving the even-numbered rows of grid signal lines, are started, so that each shift register unit generates a corresponding grid driving signal to drive the corresponding grid signal line to be started; then, the shift register units in the second sub-circuit for driving the odd-numbered gate signal lines are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started; then, the shift register units in the second sub-circuit for driving the even-numbered gate signal lines are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started; and the rest is repeated until the shift register units used for driving the even-numbered gate signal lines in the last sub-circuit are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started.

In this manner, the driving manner of the gate signal line is specifically: for the gate signal lines connected to any sub-circuit, first, gate scanning signals are sequentially applied to the odd-numbered gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to any two adjacent data signal lines, then, gate scanning signals are sequentially applied to the even-numbered gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, and gray scale signals with different polarities are applied to any two adjacent data signal lines, wherein when any two adjacent odd-numbered gate signal lines and any two adjacent even-numbered gate signal lines scan, the polarities of the gray scale signals applied to the same data signal line are opposite, which is specifically referred to the following description of the driving method of the display device, and is not repeated here.

In this way, the output terminal of the shift register unit in the previous sub-circuit for driving the last even-numbered gate signal line is connected to the input terminal of the shift register unit in the next sub-circuit for driving the first odd-numbered gate signal line.

And secondly, starting the shift register unit which is started to drive the even-numbered gate signal lines and then starting the shift register unit which is used for driving the odd-numbered gate signal lines.

Specifically, in this way, first, the shift register units in the first sub-circuit, which are used for driving even-numbered rows of gate signal lines, are turned on, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be turned on; then, the shift register units in the first sub-circuit, which are used for driving the odd-numbered gate signal lines, are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started; then, the shift register units in the second sub-circuit for driving the even-numbered gate signal lines are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started; then, the shift register units in the second sub-circuit for driving the odd-numbered gate signal lines are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started; and the rest is repeated until the shift register units used for driving the even-numbered gate signal lines in the last sub-circuit are started, so that each shift register unit generates a corresponding gate driving signal to drive the corresponding gate signal line to be started.

In this manner, the driving manner of the gate signal line is specifically: for the gate signal lines connected to any sub-circuit, first, gate scanning signals are sequentially applied to even-numbered gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to two adjacent data signal lines, then, gate scanning signals are sequentially applied to odd-numbered gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, and gray scale signals with different polarities are applied to two adjacent data signal lines, wherein when any adjacent odd-numbered gate signal line and even-numbered gate signal line scan, the polarities of the gray scale signals applied to the same data signal line are opposite, which is specifically referred to the following description of the driving method of the display device, and is not repeated here.

In this way, the output terminal of the shift register unit in the previous sub-circuit for driving the last odd-numbered gate signal line is connected to the input terminal of the shift register unit in the next sub-circuit for driving the first even-numbered gate signal line.

In the gate driving circuit provided in the embodiment of the present invention, an input terminal of a shift register unit for driving a first odd-numbered gate signal line is connected to a first frame start signal, and/or an input terminal of a shift register unit for driving a first even-numbered gate signal line is connected to a second frame start signal;

Specifically, the connection of the frame start signal as one image frame in the gate driving circuit includes the following three modes:

in mode 1, the input terminal of the shift register unit for driving the first odd-numbered gate signal line is connected to the first frame start signal, and the input terminal of the shift register unit for driving the first even-numbered gate signal line is connected to the second frame start signal.

In this manner, the gate driving circuit is configured with two frame start signals, wherein:

if the gate driving circuit operates in the first manner, in the first image frame, after the high level pulse of the first frame start signal (STVL signal), the clock control signals connected to the shift register units for driving the odd-numbered gate signal lines in the first sub-circuit are sequentially output to start the corresponding shift register units; the high level pulse of the second frame start signal (STVR signal) is the same as the high level pulse of the clock control signal connected to the shift register unit in the first sub-circuit for driving the last odd-numbered gate signal line, and after the high level pulse of the second frame start signal (STVR signal), the clock control signals connected to the shift register units in the first sub-circuit for driving the even-numbered gate signal lines are sequentially output to start the corresponding shift register units; then, in the second sub-circuit, the clock control signals connected to the shift register units for driving the odd-numbered row gate signal lines are sequentially output to turn on the corresponding shift register units, and then, in the second sub-circuit, the clock control signals connected to the shift register units for driving the even-numbered row gate signal lines are sequentially output to turn on the corresponding shift register units; and so on;

if the gate driving circuit operates in the second manner, the output timing of the clock control signal (i.e., the input timing of the gate driving circuit) is similar to that of the clock control signal, and thus the description thereof is omitted here.

In this mode, the first stage shift register unit supplies an input signal to the next stage shift register unit and a gate scan signal to the gate signal line connected thereto under the control of a frame start signal (STVL signal) and a clock control signal, the intermediate stage shift register unit supplies an input signal to the next stage shift register unit and a gate scan signal to the gate signal line connected thereto under the control of an output signal and a clock control signal of the previous stage shift register unit, and the last stage shift register unit supplies an input signal to the first stage shift register unit in the next sub-circuit and a gate scan signal to the gate signal line connected thereto under the control of an output signal and a clock control signal of the previous stage shift register unit.

It should be noted that the first stage shift register unit in the first sub-circuit refers to a shift register unit that is turned on first in the first sub-circuit, the second stage shift register unit refers to a shift register unit that is turned on second in the first sub-circuit, and so on.

Mode 2, if the gate driving circuit operates in the first mode, the input end of the shift register unit for driving the first odd-numbered gate signal line is connected to the first frame start signal.

In this mode, the difference from mode 1 is that the gate driving circuit is configured with only one frame start signal, where an output terminal of a shift register unit in the first sub-circuit for driving the last odd-numbered gate signal line is connected to an input terminal of a shift register unit in the first sub-circuit for driving the first even-numbered gate signal line, that is, an output signal of a shift register unit in the first sub-circuit for driving the last odd-numbered gate signal line is used as a frame start signal of a shift register unit in the first sub-circuit for driving the first even-numbered gate signal line. Otherwise, similar to the mode 1, the description of the mode 1 is specifically referred to, and the description is omitted here.

Mode 3, if the gate driving circuit operates in the above-described mode two, the input end of the shift register unit for driving the first even-numbered gate signal line is connected to the second frame start signal.

In this mode, the difference from mode 1 is that the gate driving circuit is configured with a frame start signal, where an output terminal of the shift register unit in the first sub-circuit for driving the last even-numbered gate signal line is connected to an input terminal of the shift register unit in the first sub-circuit for driving the first odd-numbered gate signal line, that is, an output signal of the shift register unit in the first sub-circuit for driving the last even-numbered gate signal line is used as a frame start signal of the shift register unit in the first sub-circuit for driving the first odd-numbered gate signal line. Otherwise, similar to the mode 1, the description of the mode 1 is specifically referred to, and the description is omitted here.

In the gate driving circuit provided in the embodiment of the present invention, in an image frame, pulse durations of pulse signals of clock control signals of different shift register units in any one sub-circuit are not overlapped, so that pulse durations of pulse signals output by different shift register units in each sub-circuit are not overlapped;

or,

in one image frame, the pulse duration of the pulse signals of the clock control signals of two adjacent cascaded shift register units in any one sub-circuit has an overlapping part, so that the pulse duration of the pulse signals output by two adjacent cascaded shift register units in each sub-circuit has an overlapping part.

Preferably, in any sub-circuit, two shift register units are cascaded with each other, and the pulse duration of the pulse signal output by the next shift register unit has a pulse width lag of 1/2 with respect to the pulse duration of the pulse signal output by the previous shift register unit.

In the gate driving circuit of the embodiment of the invention, the shift register units of any sub-circuit for driving the odd-numbered gate signal lines are sequentially connected, the output end of the shift register unit of the previous stage is connected with the input end of the shift register unit of the next stage, the shift register units for driving the even-numbered gate signal lines are sequentially connected, and the output end of the shift register unit of the previous stage is connected with the input end of the shift register unit of the next stage, so that, when the gate driving circuit works, for any sub-circuit, the shift register units for driving the odd-numbered gate signal lines can be started first to provide the gate scanning signals for the corresponding odd-numbered gate signal lines, then the shift register units for driving the even-numbered gate signal lines can be started first to provide the gate scanning signals for the corresponding odd-numbered gate signal lines, and the shift register units for driving the even-numbered gate signal lines can also be started first, providing a gate scanning signal to the corresponding odd-numbered gate signal line, turning on the shift register unit for driving the odd-numbered gate signal line, and providing a gate scanning signal to the corresponding odd-numbered gate signal line, wherein no matter which method is adopted, a gray scale signal with the same polarity (denoted as a first polarity) is applied to the same data signal line when different odd-numbered gate signal lines are scanned, and a gray scale signal with a second polarity opposite to the first polarity is applied to the same data signal line when different even-numbered gate signal lines are scanned, so that the source output is in a multi-point inversion mode, while a gray scale signal with the same polarity (the first polarity) is applied to the same data signal line and gray scale signals with different polarities are applied to any two adjacent data signal lines when different odd-numbered gate signal lines are scanned, the gray scale signals of the second polarity opposite to the first polarity are applied to the same data signal line, and the gray scale signals of different polarities are applied to any two adjacent data signal lines, so that the polarity of the voltage stored by each pixel point is opposite to the polarity of the pixels adjacent to the pixel point up, down, left and right, that is, the display effect of 1-point overturning is achieved, and the overall power consumption is reduced on the premise of ensuring the display quality.

The structure of the gate driver circuit provided in the embodiment of the present invention is described below by taking an example in which each sub-circuit includes 8 shift register units, and other cases are similar to this and are not described one by one here.

Referring to fig. 2, the gate driving circuit includes a plurality of sub-circuits, and each sub-circuit includes 8 shift register units, and taking a first sub-circuit as an example, the first sub-circuit includes a shift register unit 1 to a shift register unit 8, where the shift register unit 1 is configured to drive a 1 st gate signal line, the shift register unit 2 is configured to drive a 2 nd gate signal line, and so on, the shift register unit 8 is configured to drive an 8 th gate signal line; wherein:

the connection relationship of the shift register units for driving the odd-numbered grid signal lines is as follows: the shift register unit 1 (i.e. the first stage shift register unit) provides an INPUT signal to the shift register unit 3 and a gate scan signal to the 1 st gate signal line under the control of a frame start signal (STVL signal) and a clock control signal CLK1, i.e. the INPUT terminal (INPUT) of the shift register unit 1 is connected to the STVL signal, the CLK terminal is connected to CLK1, the CLKB terminal is connected to CLK5, and the OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 3 and the 1 st gate signal line, respectively; the shift register unit 3 (i.e. the middle stage shift register unit) provides an INPUT signal to the shift register unit 5 and a gate scan signal to the 3 rd gate signal line under the control of an OUTPUT signal of the shift register unit 1 and a clock control signal CLK3, i.e. an INPUT terminal (INPUT) of the shift register unit 3 is connected to an OUTPUT terminal of the shift register unit 1, a CLK terminal is connected to CLK3, a CLKB terminal is connected to CLK7, and an OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 5 and the 3 rd gate signal line, respectively; the shift register unit 5 (i.e. the middle stage shift register unit) provides an INPUT signal to the shift register unit 7 and a gate scan signal to the 5 th gate signal line under the control of an OUTPUT signal of the shift register unit 3 and a clock control signal CLK5, that is, an INPUT terminal (INPUT) of the shift register unit 5 is connected to an OUTPUT terminal of the shift register unit 3, a CLK terminal is connected to CLK5, a CLKB terminal is connected to CLK1, and an OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 7 and the 5 th gate signal line, respectively; the shift register unit 7 (i.e., the last stage shift register unit) provides the gate scan signal to the 7 th gate signal line under the control of the OUTPUT signal of the shift register unit 5 and the clock control signal CLK7, i.e., the INPUT terminal (INPUT) of the shift register unit 7 is connected to the OUTPUT terminal of the shift register unit 5, the CLK terminal is connected to CLK7, the CLKB terminal is connected to CLK3, and the OUTPUT terminal (OUTPUT) is connected to the 7 th gate signal line.

The connection relationship of the shift register units for driving the even-numbered grid signal lines is as follows: the shift register unit 2 (i.e. the first stage shift register unit) provides an INPUT signal to the shift register unit 4 and a gate scan signal to the 2 nd gate signal line under the control of a frame start signal (STVR signal) and a clock control signal CLK2, i.e. the INPUT terminal (INPUT) of the shift register unit 2 is connected to the STVR signal, the CLK terminal is connected to CLK2, the CLKB terminal is connected to CLK6, and the OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 4 and the 2 nd gate signal line, respectively; the shift register unit 4 (i.e. the middle stage shift register unit) provides an INPUT signal to the shift register unit 6 and a gate scan signal to the 4 th gate signal line under the control of an OUTPUT signal of the shift register unit 2 and a clock control signal CLK4, i.e. an INPUT terminal (INPUT) of the shift register unit 4 is connected to an OUTPUT terminal of the shift register unit 2, a CLK terminal is connected to CLK4, a CLKB terminal is connected to CLK8, and an OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 6 and the 4 th gate signal line, respectively; the shift register unit 6 (i.e. the middle stage shift register unit) provides an INPUT signal to the shift register unit 8 and a gate scan signal to the 6 th gate signal line under the control of an OUTPUT signal of the shift register unit 4 and a clock control signal CLK6, that is, an INPUT terminal (INPUT) of the shift register unit 6 is connected to an OUTPUT terminal of the shift register unit 4, a CLK terminal is connected to CLK6, a CLKB terminal is connected to CLK2, and an OUTPUT terminal (OUTPUT) is connected to the INPUT terminal of the shift register unit 8 and the 6 th gate signal line, respectively; the shift register unit 8 (i.e. the last stage shift register unit) provides an INPUT signal to the shift register unit 9 and a gate scan signal to the 8 th gate signal line under the control of the OUTPUT signal of the shift register unit 6 and a clock control signal CLK8, i.e. the INPUT terminal (INPUT) of the shift register unit 8 is connected to the OUTPUT terminal of the shift register unit 6, the CLK terminal is connected to CLK8, the CLKB terminal is connected to CLK4, and the OUTPUT terminal (OUTPUT) is connected to the 8 th gate signal line.

Fig. 3 shows a schematic diagram of a typical shift register unit, which includes an INPUT terminal (INPUT), an OUTPUT terminal (OUTPUT), clock signal INPUT terminals (CLK and CLKB), and a VGL terminal for putting the shift register unit in an operating state. Of course, the shift register unit in the embodiment of the present invention may also adopt other structures, and it does not affect the specific implementation effect of the present invention to specifically adopt which kind of shift register, and the embodiment of the present invention does not limit the structure of the shift register unit.

Based on the same inventive concept, an embodiment of the present invention further provides an array substrate including any one of the gate driving circuits, and since a principle of the array substrate for solving the problem is similar to that of the gate driving circuit, implementation of the array substrate may refer to implementation of the gate driving circuit, and repeated details are not repeated.

In the embodiment of the invention, in order to reduce the width of the left frame and the right frame of the display device, in the gate driving circuit on the array substrate, all the shift register units for driving the odd-numbered rows of gate signal lines are positioned on one side of the area where the gate signal lines are positioned, and all the shift register units for driving the even-numbered rows of gate signal lines are positioned on the other side of the area where the gate signal lines are positioned, so that the design of a narrow frame can be realized, and the productivity and the yield are improved.

Specifically, because the plurality of gate signal lines are arranged in parallel in the horizontal direction of the array substrate, in the gate driving circuit, all the shift register units for driving the odd-numbered gate signal lines are arranged in parallel in the vertical direction and are located on the left side of the area where the gate signal lines are located, and all the shift register units for driving the even-numbered gate signal lines are arranged in parallel in the vertical direction and are located on the right side of the area where the gate signal lines are located, which can be specifically seen in the structural diagram of the gate driving circuit shown in fig. 2.

Based on the same inventive concept, embodiments of the present invention further provide a display device including the array substrate, and since the principle of the display device to solve the problem is similar to that of the gate driving circuit, the implementation of the display device may refer to the implementation of the gate driving circuit, and repeated details are not repeated.

Further, the display device further comprises: the source electrode driving circuit comprises a first source electrode driving circuit and a second source electrode driving circuit, wherein the first source electrode driving circuit is used for sequentially storing gray scale signals of pixel points on odd rows; and the second source electrode driving circuit is used for sequentially storing and outputting the gray scale signals of the pixel points on the even-numbered rows.

It can be understood that the number of the gate signal lines for storing and outputting the gray scale signals of the pixels on the odd-numbered rows (or even-numbered rows) is adapted to the number of the gate signal lines on the odd-numbered rows (or even-numbered rows) that can be scanned by each sub-circuit, and corresponds to the scanning order of the corresponding gate signal lines.

The display device provided by the embodiment of the invention can be applied to liquid crystal display technologies of various modes, for example, an In-plane switching (IPS) and advanced super dimension switching (ADS) type liquid crystal display technology capable of realizing a wide viewing angle, and can also be applied to a conventional Twisted Nematic (TN) type liquid crystal display technology, which is not limited herein.

The display device provided by the embodiment of the invention can be as follows: the display device comprises any product or component with a display function, such as a liquid crystal display panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a display device, which can be implemented in any one of the following two ways:

in the first driving mode, for a gate signal line corresponding to any sub-circuit in the display device, gate scanning signals are sequentially applied to odd-numbered rows of gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to any two adjacent data signal lines, gate scanning signals are sequentially applied to even-numbered rows of gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, and gray scale signals with different polarities are applied to any two adjacent data signal lines; when any adjacent odd-numbered row gate signal line and even-numbered row gate signal line scan, the polarity of the gray scale signal applied to the same data signal line is opposite.

Specifically, in the present driving method, first, a gate scanning signal is applied to a gate signal line corresponding to a first sub-circuit in a gate driving circuit of the display device, specifically: sequentially applying grid scanning signals to odd-numbered grid signal lines corresponding to a first sub-circuit, applying positive polarity (or negative polarity) gray scale signals to the same data signal line, applying gray scale signals with different polarities to two adjacent data signal lines, sequentially applying grid scanning signals to even-numbered grid signal lines corresponding to the first sub-circuit, applying negative polarity (or positive polarity) gray scale signals to the same data signal line, and applying gray scale signals with different polarities to two adjacent data signal lines; then, applying a gate scanning signal to the gate signal line corresponding to the second sub-circuit, specifically: sequentially applying grid scanning signals to odd-numbered grid signal lines corresponding to the second sub-circuit, applying positive polarity (or negative polarity) gray scale signals to the same data signal line, applying gray scale signals with different polarities to two adjacent data signal lines, sequentially applying grid scanning signals to even-numbered grid signal lines corresponding to the second sub-circuit, applying negative polarity (or positive polarity) gray scale signals to the same data signal line, and applying gray scale signals with different polarities to two adjacent data signal lines; … …, respectively; and so on, thereby completing the driving of the display device.

Further, the storage and output modes of the source driving circuit in the display device are as follows: gray scale signals of pixel points on odd-numbered lines are stored and output in sequence, and gray scale signals of pixel points on even-numbered lines are stored and output in sequence. It can be understood that the number of the gate signal lines for storing and outputting the gray scale signals of the pixels on the odd-numbered rows (or even-numbered rows) is adapted to the number of the gate signal lines on the odd-numbered rows (or even-numbered rows) that can be scanned by each sub-circuit, and corresponds to the scanning order of the corresponding gate signal lines.

For example, first, a gate scanning signal is applied to a gate signal line corresponding to a first sub-circuit in a gate driving circuit of the display device, specifically: sequentially applying grid scanning signals to a first row of grid signal lines, applying positive gray scale signals to a first row of data signal lines, applying negative gray scale signals to a second row of data signal lines, applying positive gray scale signals to a third row of data signal lines, and applying negative gray scale signals to a fourth row of data signal lines, … …; sequentially applying gate scanning signals to a third row of gate signal lines, applying positive polarity gray scale signals to a first row of data signal lines, applying negative polarity gray scale signals to a second row of data signal lines, applying positive polarity gray scale signals to a third row of data signal lines, and applying negative polarity gray scale signals to a fourth row of data signal lines, … …; and sequentially finishing scanning of odd-numbered row gate signal lines corresponding to the first sub-circuit, wherein in the process, a source driving circuit in the display device sequentially stores and outputs gray scale signals of 1/3/5/7 th row pixel points. Then, applying gate scanning signals to the second row of gate signal lines in sequence, applying negative polarity gray scale signals to the first row of data signal lines, applying positive polarity gray scale signals to the second row of data signal lines, applying negative polarity gray scale signals to the third row of data signal lines, and applying positive polarity gray scale signals to the fourth row of data signal lines, … …; sequentially applying gate scanning signals to the fourth row of gate signal lines, applying negative polarity gray scale signals to the first row of data signal lines, applying positive polarity gray scale signals to the second row of data signal lines, applying negative polarity gray scale signals to the third row of data signal lines, and applying positive polarity gray scale signals to the fourth row of data signal lines, … …; and sequentially finishing scanning of even-numbered rows of grid signal lines corresponding to the first sub-circuit, wherein in the process, a source driving circuit in the display device sequentially stores and outputs gray scale signals of 2/4/6/8 th rows of pixel points. After the scanning of the gate signal lines corresponding to the first sub-circuit is completed, the gate signal lines corresponding to the second sub-circuit are scanned, and the specific process is similar to the scanning process of the gate signal lines corresponding to the first sub-circuit, and is not described one by one here.

In the second driving mode, for the gate signal lines corresponding to any sub-circuit in the display device, gate scanning signals are sequentially applied to even-numbered rows of gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, gray scale signals with different polarities are applied to two adjacent data signal lines, gate scanning signals are sequentially applied to odd-numbered rows of gate signal lines, gray scale signals with the same polarity are applied to the same data signal line, and gray scale signals with different polarities are applied to two adjacent data signal lines; when any adjacent odd-numbered row gate signal line and even-numbered row gate signal line scan, the polarity of the gray scale signal applied to the same data signal line is opposite.

Specifically, in the present driving method, first, a gate scanning signal is applied to a gate signal line corresponding to a first sub-circuit in a gate driving circuit of the display device, specifically: sequentially applying grid scanning signals to even-numbered grid signal lines corresponding to a first sub-circuit, applying positive polarity (or negative polarity) gray scale signals to the same data signal line, applying gray scale signals with different polarities to two adjacent data signal lines, sequentially applying grid scanning signals to odd-numbered grid signal lines corresponding to the first sub-circuit, applying negative polarity (or positive polarity) gray scale signals to the same data signal line, and applying gray scale signals with different polarities to two adjacent data signal lines; then, applying a gate scanning signal to the gate signal line corresponding to the second sub-circuit, specifically: sequentially applying grid scanning signals to even-numbered grid signal lines corresponding to the second sub-circuit, applying positive polarity (or negative polarity) gray scale signals to the same data signal line, applying gray scale signals with different polarities to two adjacent data signal lines, sequentially applying grid scanning signals to odd-numbered grid signal lines corresponding to the second sub-circuit, applying negative polarity (or positive polarity) gray scale signals to the same data signal line, and applying gray scale signals with different polarities to two adjacent data signal lines; … …, respectively; and so on, thereby completing the driving of the display device.

Furthermore, the source electrode driving circuit in the display device sequentially stores and outputs the gray scale signals of the pixel points on the even-numbered lines, and then sequentially stores and outputs the gray scale signals of the pixel points on the odd-numbered lines.

In both driving methods, the pulse durations of the pulse signals output from different shift register units in any sub-circuit of the display device do not overlap in one image frame.

The driving method provided by the embodiment of the invention is explained with reference to the first embodiment.

In the first embodiment, the first driving method is still described by taking the structure diagram of the gate driving circuit shown in fig. 2 as an example, and other cases are similar to this, and no description is given here.

Fig. 4 is an input timing diagram of the first sub-circuit of the gate driving circuit of the present embodiment, and the input timing diagrams of other sub-circuits are similar to this and are not listed here. Fig. 4 includes frame start signals (STVL signal and STVR signal), in which after the high level pulse of the STVL signal is output, the high level pulses of CLK1/CLK3/CLK5/CLK7 signals are sequentially output, so that the shift register 1/3/5/7 generates gate scan signals for driving 1/3/5/7 th row gate signal lines (i.e., gate scan signals of odd row gate signal lines); the high level pulse of the STVR signal is the same as the high level pulse of the CLK7 signal, and after the high level pulse of the STVR signal is output, the high level pulses of the CLK2/CLK4/CLK6/CLK8 signals are sequentially output, so that the shift register 2/4/6/8 generates the gate scan signals of the gate signal lines of the 2/4/6/8 th row (i.e., the gate scan signals of the gate signal lines of the even rows), in the figure, the pulse duration of the high level pulse of the STVL signal is H1, and the pulse duration of the high level pulse of the generated clock control signal CLK1/CLK3/CLK5/CLK7 signal is also H1; the pulse duration of the high level pulse of the STVR signal is H1, and the pulse duration of the high level pulse of the generated CLK2/CLK4/CLK6/CLK8 signal is also H1.

Fig. 5 is a timing diagram of the output of the first sub-circuit of the gate driving circuit of the present embodiment, in which G1/G3/G5/G7 are gate scan signals generated by the shift register unit 1/3/5/7 and applied to the corresponding odd-numbered gate signal lines, specifically: G1/G3/G5/G7 are generated in sequence after the STVL signal high-level pulse and are in one-to-one correspondence with CLK1/CLK3/CLK5/CLK7 signals respectively; in the figure, G2/G4/G6/G8 are gate scan signals generated by the shift register unit 2/4/6/8 and applied to corresponding even-numbered gate signal lines, specifically: G2/G4/G6/G8 are generated in sequence after the high-level pulse of the STVR signal and are respectively in one-to-one correspondence with the signals CLK2/CLK4/CLK6/CLK8, and in the figure, the pulse durations of the pulse signals G1/G3/G5/G7 and G2/G4/G6/G8 are H1 and do not overlap.

According to the output timing diagram shown in fig. 5, the turn-on sequence of the gate scan signals is G1 → G3 → G5 → G7 → G2 → G4 → G6 → G8 → … …; in order to make the display image quality more fine and smooth, when the gray scale signal is applied to the data signal line, the polarities of any two adjacent pixels are opposite, and the pixel data displayed on the liquid crystal display image is shown in fig. 6, in which two different fillings are used to distinguish the pixel data with different polarities. In order to match the GIP driving timing shown in fig. 4 and 5, the pixel data storage and output format of the source circuit needs to be adjusted accordingly, and specifically, referring to fig. 7, the pixel data of 1/3/5/7 rows is stored and output in sequence, the pixel data of 2/4/6/8 rows is stored and output in sequence, the pixel data of 9/11/13/15 rows is stored and output in sequence, the pixel data of 10/12/14/16 rows is stored and output in sequence, … …, and so on.

As can be seen from the pixel data displayed on the liquid crystal display screen shown in fig. 6, the gate driving circuit and the driving method thereof according to the embodiment of the present invention enable the polarity of the voltage stored and output by each pixel point to be opposite to the polarity of the pixels adjacent to the pixel points, i.e., the display effect of 1-point inversion can be achieved, and as can be seen from the data storage and output format shown in fig. 7, when the source electrode outputs, the polarities of the voltages stored and output by each 4 adjacent pixel points are the same, i.e., the source electrode outputs in a 4-point inversion manner, so that the power consumption is greatly reduced.

It should be noted that, if each sub-circuit includes 4 shift register units, a 2-point inversion mode of source output is realized, and a 1-point inversion display effect is achieved; if each sub-circuit comprises 16 shift register units, the source output is in an 8-point overturning mode, and the display effect of 1-point overturning is achieved; and so on.

For the two driving methods, in one image frame, the pulse duration of the pulse signals output by two adjacent cascaded shift register units in any sub-circuit of the display device has an overlapping part.

In implementation, it is necessary to configure a pair of frame start signals (STVL signal and STVR signal) for each sub-circuit, and control the input timings of the shift register units for driving the odd-numbered row gate signal lines and the input timings of the shift register units for driving the even-numbered row gate signal lines, respectively.

In the second embodiment, the first driving method is still described by taking the structure diagram of the gate driving circuit shown in fig. 2 as an example, and other situations are similar to this, and no description is given here.

In this embodiment, a precharge process of the pixel is added on the basis of the first embodiment, an input timing diagram of the first sub-circuit of the gate driving circuit is shown in fig. 8, and input timing diagrams of other sub-circuits are similar to this, and are not listed here. In fig. 8, the pulse duration of the high level pulse of the STVL signal is still H1, the pulse duration of the high level pulse of the generated signal CLK1/CLK3/CLK5/CLK7 signal is H1+ H2, the pulse duration of the high level pulse of the STVR signal is still H1, and the pulse duration of the high level pulse of the generated signal CLK 56 2/CLK4/CLK6/CLK8 signal is H1+ H2, i.e., there is an overlap of H2 width between two adjacent clock control signals (such as CLK1 and CLK3, CLK3 and CLK5, CLK5 and CLK7, CLK2 and CLK4, CLK4 and CLK6, CLK6 and CLK8, … …) to realize the charging process of the pixel.

Fig. 9 is a timing diagram of an output of the first sub-circuit of the gate driving circuit according to the present embodiment, which is the same as the first embodiment and therefore will not be described herein again.

The pixel data displayed on the liquid crystal display screen and the pixel data storage and output format of the source circuit in this embodiment are the same as those in the first embodiment, and refer to fig. 6 and 7 specifically, which are not described herein again.

When the gate driving circuit provided by the embodiment of the invention works, for the gate signal lines connected with any sub-circuit, the odd-numbered row gate signal lines can be scanned firstly and then the even-numbered row gate signal lines can be scanned, and the even-numbered row gate signal lines can be scanned firstly and then the odd-numbered row gate signal lines can be scanned, so that the source output is in a multi-point overturning mode, and the display effect of 1-point overturning is achieved, thereby reducing the overall power consumption on the premise of ensuring the display quality.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A gate driving circuit, comprising at least two sub-circuits, each of the sub-circuits comprising M shift register units, each of the shift register units being configured to drive a different gate signal line, M being a positive integer not less than 3, wherein:

the output end of the last started shift register unit in the previous sub-circuit is connected with the input end of the first started shift register unit in the next sub-circuit;

2. A gate drive circuit as claimed in claim 1, wherein the gate drive circuit, in operation, for any one of the sub-circuits:

3. A gate drive circuit as claimed in claim 2,

in the grid driving circuit, the input end of a shift register unit for driving a first odd-numbered grid signal line is connected with a first frame starting signal, and/or the input end of a shift register unit for driving a first even-numbered grid signal line is connected with a second frame starting signal;

in any sub-circuit, the clock signal input ends of the shift register units for driving the odd-numbered gate signal lines are connected with different clock control signals, and the clock control signals connected with each shift register unit are sequentially output in a pulse period, so that the shift register units for driving the odd-numbered gate signal lines sequentially generate gate scanning signals; the clock signal input ends of the shift register units for driving the even-numbered gate signal lines are connected with different clock control signals, and the clock control signals connected with each shift register unit are sequentially output in one pulse period, so that the shift register units for driving the even-numbered gate signal lines sequentially generate gate scanning signals.

4. The gate driving circuit according to claim 2, wherein the output terminal of the last activated shift register cell in the previous sub-circuit is connected to the input terminal of the first activated shift register cell in the next sub-circuit, specifically:

5. An array substrate, comprising the gate driving circuit as claimed in any one of claims 1 to 4.

6. The array substrate of claim 5, wherein in the gate driving circuit, all shift register units for driving odd-numbered rows of gate signal lines are located at one side of the area where the gate signal lines are located, and all shift register units for driving even-numbered rows of gate signal lines are located at the other side of the area where the gate signal lines are located.

7. A display device comprising the array substrate according to any one of claims 5 to 6.

8. A driving method of a display device, using the gate driving circuit according to any one of claims 1 to 4, the driving method comprising:

9. The driving method according to claim 8, wherein for a gate signal line to which any one of the sub-circuits in the display device is connected, the driving method further comprises:

10. The driving method according to claim 8 or 9,

in an image frame, pulse durations of pulse signals output by different shift register units in any sub-circuit of a gate driving circuit of the display device are not overlapped; or,

in one image frame, the pulse duration of the pulse signals output by two adjacent cascaded shift register units in any sub-circuit of the gate driving circuit of the display device has an overlapping part.