CN103985361B - Gate driver circuit and control method thereof and liquid crystal display - Google Patents
Gate driver circuit and control method thereof and liquid crystal display Download PDFInfo
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- CN103985361B CN103985361B CN201310473356.2A CN201310473356A CN103985361B CN 103985361 B CN103985361 B CN 103985361B CN 201310473356 A CN201310473356 A CN 201310473356A CN 103985361 B CN103985361 B CN 103985361B
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Abstract
Gate driver circuit provided by the invention and control method and liquid crystal display, described gate driver circuit includes: multiple shift register cells; Described shift register cell includes the first latch, the second latch, the 3rd latch, the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit; The outfan of described first latch is connected with the input of described first NAND circuit and the input of the second NAND circuit respectively; The outfan of described 3rd latch is connected with the described input of the 3rd NAND circuit and the input of the 4th NAND circuit respectively; The input of described second latch is connected with the outfan of described first latch, and the outfan of described second latch is connected with the input of described 3rd latch; Described shift register cell is sequentially connected with, and the outfan of the 3rd latch of previous shift register cell is connected with the input of the first latch of later shift register cell.
Description
Technical field
The present invention relates to LCD Technology field, particularly to a kind of gate driver circuit and control method thereof and liquid crystal display.
Background technology
Along with the development of semiconductor technologies, flat-panel screens product also rises therewith. In the middle of numerous flat-panel screens, liquid crystal display (LiquidCrystalDisplay) is based on the advantage such as its low-power consumption, Low emissivity, lightweight and volume be little, it has also become the main flow of display product.
Liquid crystal display generally comprises source electrode drive circuit, gate driver circuit and display panels, wherein, display panels generally comprises M bar scanning line and N data line, every row (column) scanning line connects all pixels of same row (column), each column (OK) data wire connects all pixels of same string (OK), M bar scanning line correspondence M row (column) pixel, N data line correspondence N arranges (OK) pixel, namely has M × N number of pixel on display panels. Source electrode drive circuit and gate driver circuit carry data signal and scanning signal respectively to data wire and scanning line, in order to drive pixel. Accordingly, gate driver circuit generally comprises M level, and each level at a frame period inner grid drive circuit all exports a scanning signal. Each level of gate driver circuit includes a latch, a NAND gate and a buffer.
Refer to Fig. 1, it is the part-structure block diagram of gate driver circuit of the prior art. as shown in Figure 1, in gate driver circuit 10 in the prior art, the latch 11 of the 1st grade is controlled output shift signal next1 by clock signal ckv3, the NAND gate 12 of the 1st grade receives output and the non-computational result buffer 13 to the 1st grade after shift signal next1 and clock signal ckv1, and thus the buffer 13 of the 1st grade exports a scanning signal Gout1. the latch 21 of the 2nd grade is controlled output shift signal next2 by clock signal ckv1, the NAND gate 22 of the 2nd grade receives output and the non-computational result buffer 23 to the 2nd grade after shift signal next2 and clock signal ckv3, thus the buffer 23 of the 2nd grade exports a scanning signal Gout2, same, the latch 31 of 3rd level is controlled output shift signal next3 by clock signal ckv3, the NAND gate 32 of 3rd level exports with non-computational result to the buffer 33 of 3rd level after receiving shift signal next3 and clock signal ckv1, thus the buffer 33 of 3rd level exports a scanning signal Gout3, by that analogy, clock signal ckv1 or ckv3 according to reception at different levels are sequentially output a scanning signal Gout.
Visible, one scanning signal Gout of every grade of output in gate driver circuit, export a scanning signal Gout and be accomplished by a latch, a NAND gate and a buffer. Common, gate driver circuit has hundreds of even thousands of levels, and therefore, the Area comparison of gate driver circuit is big.
Development along with high definition HD display and full HD (FHD) display, in display panels, the pixel in unit are can get more and more, the quantity of scanning line also can increase therewith, accordingly, the scanning signal Gout of gate driver circuit output also can increase, and will increase output one scanning signal Gout and be accomplished by increasing a latch, a NAND gate and a buffer. The area of gate driver circuit also can be increasing, becomes the obstacle of narrow frame design.
And, in the shift signal next pulse width of the latch cycle equal to a clock signal ckv in the gate driver circuit of prior art, the dutycycle of clock signal ckv is less than 1:4. Refer to Fig. 2, it is the portion waveshape simulation drawing of gate driver circuit of the prior art. As in figure 2 it is shown, the pulse of a shift signal next only covers a clock signal ckv signal, remainder is all wasted.
Base this, how to solve the excessive narrow frame design affecting liquid crystal display of the area of gate driver circuit in prior art, the only small problem causing signal to waste of dutycycle of clock signal has become as those skilled in the art and needs badly and solve the technical problem that simultaneously.
Summary of the invention
It is an object of the invention to provide a kind of gate driver circuit and control method thereof and liquid crystal display device, the excessive narrow frame design affecting liquid crystal display of area to solve existing gate driver circuit, the simultaneously only small problem causing signal to waste of dutycycle of clock signal.
For solving above-mentioned technical problem, the present invention provides a kind of gate driver circuit, and described gate driver circuit includes: multiple shift register cells; Described shift register cell includes the first latch, the second latch, the 3rd latch, the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit; The outfan of described first latch is connected with the input of described first NAND circuit and the input of the second NAND circuit respectively; The outfan of described 3rd latch is connected with the described input of the 3rd NAND circuit and the input of the 4th NAND circuit respectively; The input of described second latch is connected with the outfan of described first latch, and the outfan of described second latch is connected with the input of described 3rd latch; Described shift register cell is sequentially connected with, and the outfan of the 3rd latch of previous shift register cell is connected with the input of the first latch of later shift register cell.
Present invention also offers a kind of liquid crystal display, described liquid crystal display includes: display panels, source electrode drive circuit and two gate driver circuits as above;
Described display panels includes multi-strip scanning line and many signal line, and described source electrode drive circuit is connected with described many signal line, and said two gate driver circuit lays respectively at the opposite sides of described display panels and is connected with described multi-strip scanning line.
Present invention also offers the control method of a kind of gate driver circuit, the control method of described gate driver circuit includes:
First latch, the second latch, the 3rd latch export shift signal respectively according to clock signal;
First NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit receive shift signal and clock signal respectively and export and non-computational result;
Buffer exports scanning signal according to described respectively with non-computational result.
The present invention also provides for a kind of liquid crystal display, and described liquid crystal display includes above-mentioned gate driver circuit.
In gate driver circuit provided by the invention and control method and liquid crystal display thereof, first latch and the 3rd latch carry out and non-computational with two clock signals respectively, it is simultaneously introduced the second latch in order to push shift signal, it is achieved thereby that the type of drive of dual output deposited by monolock, 4 scanning signals just can be exported from there through 3 latch, save 1 latch, therefore, it is possible to the area of reduction of gate drive circuit effectively, simultaneously, the shift signal of described gate driver circuit can cover 4 clock signals, increases the dutycycle of clock signal.
Accompanying drawing explanation
Fig. 1 is the part-structure block diagram of gate driver circuit of the prior art;
Fig. 2 is the portion waveshape simulation drawing of gate driver circuit of the prior art;
Fig. 3 is the part-structure block diagram of the gate driver circuit of the embodiment of the present invention;
Fig. 4 is the circuit structure diagram of the latch of the embodiment of the present invention;
Fig. 5 is the circuit structure diagram of the NAND gate of the embodiment of the present invention;
Fig. 6 is the circuit structure diagram of the buffer of the embodiment of the present invention;
Fig. 7 is the portion waveshape simulation drawing of the gate driver circuit of the embodiment of the present invention;
Fig. 8 is the structured flowchart of the liquid crystal display of the embodiment of the present invention.
Detailed description of the invention
The gate driver circuit present invention proposed below in conjunction with the drawings and specific embodiments and control method and liquid crystal display thereof are described in further detail. According to the following describes and claims, advantages and features of the invention will be apparent from. It should be noted that, accompanying drawing all adopts the form simplified very much and all uses non-ratio accurately, only in order to convenience, the purpose aiding in illustrating the embodiment of the present invention lucidly.
Refer to Fig. 3, it is the part-structure block diagram of gate driver circuit of the embodiment of the present invention. As it is shown on figure 3, described gate driver circuit 100 includes: multiple shift register cells 50; Described shift register cell 50 includes the first latch the 101, second latch the 201, the 3rd latch the 301, first NAND gate the 102, second NAND gate the 202, the 3rd NAND gate 302 and the 4th NAND gate 402; The outfan of described first latch 101 is connected with the input of described first NAND gate 102 and the input of the second NAND gate 202 respectively; The outfan of described 3rd latch 301 is connected with the described input of the 3rd NAND gate 302 and the input of the 4th NAND gate 402 respectively; The input of described second latch 201 is connected with the outfan of described first latch 101, and the outfan of described second latch 201 is connected with the input of described 3rd latch 301; Described shift register cell 50 is sequentially connected with, and the outfan of the 3rd latch 301 of previous shift register cell 50 is connected with the input of the first latch 101 of later shift register cell 50.
Concrete, described shift register cell 50 includes the first latch the 101, second latch 201 and the 3rd latch 301, described second latch 201 is between described first latch 101 and described 3rd latch 11, the input of the second latch 201 is connected with the outfan of described first latch 101, and the outfan of the second latch 201 is connected with the input of described 3rd latch 301.
Described shift register cell 50 also includes 4 buffers, the outfan of first NAND gate the 102, second NAND gate the 202, the 3rd NAND gate 302 and the 4th NAND gate 402 is connected with a buffer respectively, described 4 buffers are the first buffer the 103, second buffer the 203, the 3rd buffer 303 and the 4th buffer 403 respectively, respectively output 4 scanning signal.
Visible, the shift register cell 50 in the present embodiment includes 3 latch, 4 NAND gate and 4 buffers.
Respectively latch, NAND gate and buffer will be described in detail below.
Latch includes the circuit structure of first latch the 101, second latch 201 and the 3rd latch 301 and includes 2 phase inverters and 2 clocked inverters. the particular circuit configurations of latch refer to Fig. 4, and it is the circuit structure diagram of latch of the embodiment of the present invention. as shown in Figure 4, described latch includes phase inverter 51, phase inverter 52, clocked inverter 53 and clocked inverter 54, the outfan of phase inverter 51 connects the input of clocked inverter 53 and clocked inverter 54, the outfan of clocked inverter 53 connects the input of phase inverter 52 and clocked inverter 54, the outfan of phase inverter 52 is connected with the outfan of clocked inverter 54, wherein, phase inverter 51, the input of clocked inverter 53 and clocked inverter 54 all accesses real-time sequential signal ckv, the input of clocked inverter 53 accesses a high level Vin, shift signal next is exported by the outfan of phase inverter 52.
NAND gate includes the particular circuit configurations of first NAND gate the 102, second NAND gate the 202, the 3rd NAND gate the 302, the 4th NAND gate 402 and refer to Fig. 5, and it is the circuit structure diagram of NAND gate of the embodiment of the present invention. As it is shown in figure 5, described NAND gate is made up of a N-type transistor and a P-type transistor, the two ends of N-type transistor and P-type transistor connect high level Vin1 and low level Vin2 respectively. What deserves to be explained is, in the present embodiment, NAND circuit includes being all a NAND gate, is one of the present invention and preferred embodiment but is not limited to this, as long as it is all feasible for being capable of the logic circuit with non-computational, is all within protection scope of the present invention.
Buffer includes the circuit structure of first buffer the 103, second buffer the 203, the 3rd buffer 303 and the 4th buffer 403 and includes odd number phase inverter 55, and described odd number phase inverter 55 scans signal according to the output of non-computational result. The particular circuit configurations of buffer refer to Fig. 6, and it is the circuit structure diagram of buffer of the embodiment of the present invention. As shown in Figure 6, described buffer includes 3 phase inverters 55, and the output of previous phase inverter 55 connects the input of later phase inverter 55, and 3 phase inverters 55 are sequentially connected with. Inputted and non-computational result IN by the input of the 1st phase inverter 55 in a buffer, the outfan of the 3rd phase inverter 55 export scanning signal Gout.
With continued reference to Fig. 3 and Fig. 7, in described gate driver circuit 50, described first latch the 101, second latch 201 and the 3rd latch 301 control output shift signal next by clock signal ckv. Described clock signal ckv includes the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the four clock signal ckv4. Wherein, described first latch 101 is controlled by the 4th clock signal ckv4, and described second latch 201 is controlled by the second clock signal ckv2 or the 3rd clock signal ckv3, and described 3rd latch 301 is controlled ckv1 by the first clock signal.
As it is shown in fig. 7, the rising edge of the rising edge of shift signal next1 that goes out of described first latch defeated 101 and trailing edge corresponding 4th clock signal ckv4 respectively; The rising edge of the shift signal next2 of described second latch 201 output and the rising edge of trailing edge corresponding second clock signal ckv2 or the 3rd clock signal ckv3 respectively;The rising edge of the shift signal next3 of described 3rd latch 301 output and the rising edge of trailing edge corresponding first clock signal ckv1 respectively.
Wherein, the trailing edge time of described first clock signal ckv1 is corresponding with the rising time of the second clock signal ckv2, and free interval; The trailing edge time of described second clock signal ckv2 is corresponding with the rising time of the 3rd clock signal ckv3, and free interval; The trailing edge time of described 3rd clock signal ckv3 is corresponding with the rising time of the 4th clock signal ckv4, and free interval; The trailing edge time of described 4th clock signal ckv4 is corresponding with the rising time of the first clock signal ckv1, and free interval. And the pulse width of described shift signal (next1, next2 and next3) more than or equal to described first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the four clock signal ckv4 pulse width sum.
Described first latch 101 exports after shift signal next1 terminates, and described 3rd latch 301 starts to export shift signal next3. In the process, described second latch 201 is used for pushing shift signal.
Accordingly, present invention also offers the control method of a kind of gate driver circuit, the control method of described gate driver circuit comprises the following steps:
First latch the 101, second latch 201 and the 3rd latch 30 export shift signal next respectively according to clock signal;
First NAND gate the 102, second NAND gate the 202, the 3rd NAND gate the 302, the 4th NAND gate 402 receives shift signal next and clock signal ckv respectively and exports and non-computational result;
Buffer according to described with non-computational result respectively export scanning signal Gout.
Concrete, described first latch the 101, second latch 201 and the 3rd latch 301 control output shift signal next by clock signal. Described clock signal includes the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the four clock signal ckv4, described first latch 101 is controlled by the 4th clock signal ckv4, described second latch 201 is controlled by the second clock signal ckv2 or the 3rd clock signal ckv3, and described 3rd latch 301 is controlled by the first clock signal ckv1.
The rising time of shift signal next and trailing edge time are all subject to the control of clock signal, wherein, the rising edge of the shift signal next1 of described first latch 101 output and the rising edge of trailing edge corresponding 4th clock signal ckv4 respectively, the rising edge of the shift signal next2 of described second latch output and the rising edge of trailing edge corresponding second clock signal ckv2 or the 3rd clock signal ckv3 respectively, the rising edge of the shift signal next3 of described 3rd latch 301 output and the rising edge of trailing edge corresponding first clock signal ckv1 respectively.
Wherein, in 4 clock signals, two clock signals (ckv4 and ckv1) control the first latch 101 and the 3rd latch 301. Simultaneously, first NAND gate the 102, second NAND gate the 202, the 3rd NAND gate 302 and the 4th NAND gate 402 receive 4 clock signals (ckv1, ckv2, ckv3 and ckv4) respectively, and shift signal next1 or next3 exported with the first latch 101 and the 3rd latch 301 carries out and non-computational.
First NAND gate 102 carries out and non-computational after receiving the shift signal next1 and the first clock signal ckv1 of the first latch 101 output, and exports result of calculation to the first buffer 103, and thus the first buffer 103 exports a scanning signal Gout1;Second NAND gate 202 receives shift signal next1 and the three clock signal ckv3 of the first latch 101 output and carries out and non-computational, and exports result of calculation to the second buffer 203, and thus the second buffer 203 exports a scanning signal Gout3; 3rd NAND gate 302 receives the shift signal next3 and the second clock signal ckv2 of the 3rd latch 301 output and carries out and non-computational, and exports result of calculation to the 3rd buffer 303, and thus the 3rd buffer 303 exports a scanning signal Gout6; 4th NAND gate 402 receives shift signal next3 and the four clock signal ckv4 of the 3rd latch 301 output and carries out and non-computational, and exports result of calculation to the 4th buffer 403, and thus the 4th buffer 403 exports a scanning signal Gout8.
In the shift register cell 50 of the embodiment of the present invention, the second latch 201 is used for pushing shift signal next. Refer to Fig. 7, it is the portion waveshape simulation drawing of gate driver circuit of the embodiment of the present invention. As shown in Figure 7, the shift signal next2 of the second latch 201 output and the shift signal next1 of the first latch 101 output overlaps each other in high level period, the shift signal next2 of shift signal next3 and the second latch 201 output of the 3rd latch 301 output overlaps each other in high level period, and after the output that the first latch 101 completes shift signal next1, the 3rd latch 301 starts the shift signal next3 exported. Visible, the shift signal next of the first latch 101 output pushes to the 3rd latch 301 via the second latch 201, and the 3rd latch 301 exports the shift signal next of next cycle.
In the present embodiment, the pulse width of described shift signal (next1, next2 and next3) is all higher than or is equal to the pulse width sum of described first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the four clock signal ckv4. please continue to refer to Fig. 7, as shown in Figure 7, in 4 clock signals, the trailing edge time of the first clock signal ckv1 is corresponding with the rising time of the second clock signal ckv2, and free interval, the trailing edge time of the second clock signal ckv2 is corresponding with the rising time of the 3rd clock signal ckv3, and free interval, the rising time that the trailing edge time is the 4th clock signal ckv4 of the 3rd clock signal ckv3 is corresponding, and free interval, the trailing edge time of the 4th clock signal ckv4 is corresponding with the rising time of the first clock signal ckv1, and free interval, the pulse width of shift signal next covers 4 clock signal ckv. visible, shift signal next is fully utilized, and the dutycycle of clock signal ckv is very big.
Described gate driver circuit 100 includes in multiple shift register cell 50(Fig. 3 not shown multiple), the plurality of shift register cell 50 is sequentially connected with, and the outfan of the 3rd latch 301 of previous shift register cell 50 is connected with the input of the first latch 101 of later shift register cell 50.
The shift signal next3 of the 3rd latch 301 output of previous shift register cell 50 is supplied to the first latch 101 of later shift register cell 50, first latch 101 of later shift register cell 50 is equally by being controlled by the 4th clock signal ckv4, first latch 101 of later shift register cell 50 exports shift signal next4 according to the 4th clock signal ckv4, first NAND gate 102 of later shift register cell 50 receives the shift signal next4 and the first clock signal ckv1 of the first latch 101 output of later shift register cell 50, and export and non-computational result to later shift register cell 50 the first buffer 103, thus, first buffer 103 of later shift register cell 50 exports a scanning signal Gout9.
Same, second NAND gate 202 of later shift register cell 50 receives shift signal next4 and the three clock signal ckv3 of the first latch 101 output of later shift register cell 50, and export and non-computational result to the second buffer 203 of later shift register cell 50, thus the second buffer 203 exports one and scans signal Gout11; 3rd NAND gate 302 of later shift register cell 50 receives the shift signal next6 and the second clock signal ckv2 of the 3rd latch 301 output of later shift register cell 50, and export and non-computational result to the 3rd buffer 303 of later shift register cell 50, thus the 3rd buffer 303 exports one and scans signal Gout14; 4th NAND gate 402 of later shift register cell 50 receives shift signal next6 and the four clock signal ckv4 of the 3rd latch 301 output of later shift register cell 50, and export and non-computational result to the 4th buffer 403 of later shift register cell 50, thus the 4th buffer 403 exports one and scans signal Gout16.
Visible, in described gate driver circuit 100, the first latch 101 and the 3rd latch 301 carry out and non-computational with two clock signals respectively, realize monolock and deposit the type of drive of dual output, simultaneously, the shift signal next of the first latch 101 output is pushed to the 3rd latch 301 by the second latch 201,3rd latch 301 exports the shift signal next of next cycle, and the shift signal next of the 3rd latch 301 output can as the input of the first latch 101 of next shift register cell 50. So, multiple shift register cells 50 transmit shift signal next successively and export scanning signal Gout. Therefore, described gate driver circuit 100 can realize the cross complementary driving of left and right sides drive circuit.
The particular number of shift register cell 50 is that the resolution according to liquid crystal display determines, if the liquid crystal display of high definition (HD) pattern, its resolution is 720 × 1280, then in gate driver circuit 100, the quantity of shift register cell 50 is 180, within a frame period, gate driver circuit 100 sequentially exports 720 scanning signal Gout, and 720 scanning signals are sequentially provided to the scanning line of display panels. The liquid crystal display of full HD if (FHD) pattern, its resolution is 1080 × 1920, then in gate driver circuit 100, the quantity of shift register cell 50 is 270, within a frame period, gate driver circuit 100 sequentially exports 1080 scanning signal Gout, and 1080 scanning signals are sequentially provided to the scanning line of display panels.
Owing to a shift register cell 3 latch of 50 need just can export 4 scanning signals, gate driver circuit 100 exports the signal Gout latch the adopted gate driver circuit 10 more of the prior art that scans of equal number and lacks. For the liquid crystal display of high definition (HD) pattern, gate driver circuit 100 has only to 540 latch just can export 720 scanning signal Gout. For the liquid crystal display of full HD (FHD) pattern, gate driver circuit 100 has only to 810 latch just can export 1080 scanning signal Gout. Liquid crystal display adopts one side to drive, and gate driver circuit 10 more of the prior art decreases 190 and 270 latch respectively.
And, the gate driver circuit 100 that the embodiment of the present invention provides, by buffer output scanning signal Gout, therefore, has good driving force.
At present, in order to reduce the manufacturing cost of liquid crystal display and use the purpose realizing narrow frame, on display panels, typically directly form gate driver circuit in the fabrication process. Display panels has the viewing area for showing image and the non-display area around viewing area, and wherein, gate driver circuit is positioned at non-display area.
Accordingly, present invention also offers a kind of liquid crystal display 200, refer to Fig. 8, it is the structured flowchart of liquid crystal display of the embodiment of the present invention. As shown in Figure 8, described liquid crystal display 200 includes: display panels 60, source electrode drive circuit 70 and two above-mentioned gate driver circuits 100; Described display panels 60 includes multi-strip scanning line 61 and many signal line 62, described source electrode drive circuit 70 is connected with described many signal line 62, and said two gate driver circuit 100 lays respectively at the opposite sides of described display panels 60 and is connected with described multi-strip scanning line 61.
Concrete, source electrode drive circuit 70 and gate driver circuit 100 are respectively positioned on the non-display area of display panels 60. Two gate driver circuits 100 export scanning signal Gout respectively according to clock signal, and scanning signal Gout is sent to the scanning line of display panels 60 in order to drive pixel. In the liquid crystal display 200 that the present embodiment provides, the gate driver circuit 100 of display panels 60 both sides exports scanning signal Gout respectively, it is possible to the brightness of balance liquid LCD panel both sides. And gate driver circuit 100 gate driver circuit more of the prior art 10 adopts less latch. In the present embodiment, liquid crystal display adopts both sides to drive, if 190 or 270 latch can be reduced by the liquid crystal display side of high definition (HD) pattern or full HD (FHD) pattern. It is thereby possible to reduce the area of the non-display area of display panels both sides, it is achieved the purpose of narrow frame, reduces the power consumption of gate driver circuit simultaneously.
To sum up, in the gate driver circuit provided in the embodiment of the present invention and control method and liquid crystal display, one latch carries out and non-computational with two clock signals respectively, between two latch, add a latch be used for pushing shift signal simultaneously, thus realizing monolock to deposit the type of drive of dual output, described gate driver circuit has only to 3 latch just can export 4 scanning signals, thus can save substantial amounts of latch, the area of the non-display area of display panels both sides is reduced, it is achieved the purpose of narrow frame while reducing power consumption. Meanwhile, the pulse of the shift signal of described gate driver circuit covers 4 clock signals, substantially increases the dutycycle of clock signal, improves the utilization rate of shift signal.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belongs to the protection domain of claims.
Claims (11)
1. a gate driver circuit, it is characterised in that including: multiple shift register cells;
Described shift register cell includes the first latch, the second latch, the 3rd latch, the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit;
The outfan of described first latch is connected with the input of described first NAND circuit and the input of the second NAND circuit respectively;
The outfan of described 3rd latch is connected with the described input of the 3rd NAND circuit and the input of the 4th NAND circuit respectively;
The input of described second latch is connected with the outfan of described first latch, and the outfan of described second latch is connected with the input of described 3rd latch;
Described first latch, the second latch, the 3rd latch control output shift signal by clock signal, and described clock signal includes the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal; Wherein, described first latch is controlled by the 4th clock signal, and described second latch is controlled by the second clock signal or the 3rd clock signal, and described 3rd latch is controlled by the first clock signal;
The rising edge of the shift signal of described first latch output and the rising edge of trailing edge corresponding 4th clock signal respectively; The rising edge of the shift signal of described second latch output and the rising edge of trailing edge corresponding second clock signal or the 3rd clock signal respectively; The rising edge of the shift signal of described 3rd latch output and the rising edge of trailing edge corresponding first clock signal respectively;
The trailing edge time of described first clock signal is corresponding with the rising time of the second clock signal, and free interval; The trailing edge time of described second clock signal is corresponding with the rising time of the 3rd clock signal, and free interval; The trailing edge time of described 3rd clock signal is corresponding with the rising time of the 4th clock signal, and free interval; The trailing edge time of described 4th clock signal is corresponding with the rising time of the first clock signal, and free interval;
Described shift register cell is sequentially connected with, and the outfan of the 3rd latch of previous shift register cell is connected with the input of the first latch of later shift register cell.
2. gate driver circuit as claimed in claim 1, it is characterised in that described shift register cell also includes multiple buffer, and described buffer is used for exporting scanning signal;
The outfan of described first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit is connected with described buffer respectively.
3. gate driver circuit as claimed in claim 2, it is characterised in that described buffer includes odd number phase inverter, and described odd number phase inverter is sequentially connected with.
4. gate driver circuit as claimed in claim 1, it is characterised in that described first NAND circuit includes one first NAND gate; Described second NAND circuit includes one second NAND gate; Described 3rd NAND circuit includes one the 3rd NAND gate; Described 4th NAND circuit includes one the 4th NAND gate.
5. gate driver circuit as claimed in claim 1, it is characterised in that the pulse width of described shift signal is more than or equal to the pulse width sum of described first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal.
6. gate driver circuit as claimed in claim 5, it is characterised in that after described first latch output shift signal terminates, described 3rd latch starts to export shift signal.
7. a liquid crystal display, it is characterised in that including: display panels, source electrode drive circuit and two gate driver circuits as described in any one in claim 1 to 6;
Described display panels includes multi-strip scanning line and many signal line, and described source electrode drive circuit is connected with described many signal line, and said two gate driver circuit lays respectively at the opposite sides of described display panels and is connected with described multi-strip scanning line.
8. the control method of a gate driver circuit, it is characterised in that including:
First latch, the second latch, the 3rd latch export shift signal respectively according to clock signal;
First NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit receive shift signal and clock signal respectively and export and non-computational result;
Described clock signal includes the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal; Described first latch is controlled by the 4th clock signal, and described second latch is controlled by the second clock signal or the 3rd clock signal, and described 3rd latch is controlled by the first clock signal;
The rising edge of the shift signal of described first latch output and the rising edge of trailing edge corresponding 4th clock signal respectively; The rising edge of the shift signal of described second latch output and the rising edge of trailing edge corresponding second clock signal or the 3rd clock signal respectively; The rising edge of the shift signal of described 3rd latch output and the rising edge of trailing edge corresponding first clock signal respectively;
The trailing edge time of described first clock signal is corresponding with the rising time of the second clock signal, and free interval; The trailing edge time of described second clock signal is corresponding with the rising time of the 3rd clock signal, and free interval; The trailing edge time of described 3rd clock signal is corresponding with the rising time of the 4th clock signal, and free interval; The trailing edge time of described 4th clock signal is corresponding with the rising time of the first clock signal, and free interval;
Buffer exports scanning signal according to described respectively with non-computational result.
9. the control method of gate driver circuit as claimed in claim 8, it is characterised in that described buffer includes odd number phase inverter, and described odd number phase inverter is sequentially connected with;
Described scanning signal is exported by described odd number phase inverter.
10. the control method of gate driver circuit as claimed in claim 8, it is characterized in that, the pulse width of described shift signal is more than or equal to the pulse width sum of described first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal.
11. the control method of gate driver circuit as claimed in claim 10, it is characterised in that after described first latch output shift signal terminates, described 3rd latch starts to export shift signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310473356.2A CN103985361B (en) | 2013-10-11 | 2013-10-11 | Gate driver circuit and control method thereof and liquid crystal display |
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| CN104392687B (en) * | 2014-12-04 | 2017-01-18 | 厦门天马微电子有限公司 | Drive unit as well as drive method thereof, drive circuit, array substrate and display panel |
| CN104485061B (en) * | 2014-12-23 | 2018-03-23 | 上海天马有机发光显示技术有限公司 | Dynamic logic circuit, gate driving circuit, display panel and display device |
| CN104537973A (en) * | 2014-12-29 | 2015-04-22 | 厦门天马微电子有限公司 | Shifting register, grid drive circuit, array substrate and display panel |
| CN104537996A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Notand gate latching drive circuit and notand gate latching shift register |
| CN104599622B (en) * | 2015-02-13 | 2018-03-23 | 上海天马有机发光显示技术有限公司 | Dynamic logic circuit, gate driving circuit, display panel and display device |
| CN104952413B (en) * | 2015-07-17 | 2018-05-29 | 武汉华星光电技术有限公司 | A kind of low-power consumption phase inverter, low-power consumption GOA circuits and liquid crystal display panel |
| CN104966501B (en) * | 2015-07-21 | 2017-07-28 | 深圳市华星光电技术有限公司 | GOA circuit structure for narrow frame LCD |
| CN105185338B (en) * | 2015-09-28 | 2018-01-30 | 武汉华星光电技术有限公司 | CMOS GOA circuits |
| CN105931606B (en) * | 2016-05-27 | 2019-07-12 | 厦门天马微电子有限公司 | Gate drive configuration and display device |
| CN108447436B (en) * | 2018-03-30 | 2019-08-09 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, display device |
| CN111210776B (en) * | 2020-01-19 | 2021-08-06 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
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| JP3758503B2 (en) * | 2001-01-15 | 2006-03-22 | セイコーエプソン株式会社 | Electro-optical device, drive circuit, and electronic device |
| JP4693424B2 (en) * | 2005-01-18 | 2011-06-01 | 東芝モバイルディスプレイ株式会社 | Bidirectional shift register drive circuit, bidirectional shift register |
| CN102368380A (en) * | 2011-09-14 | 2012-03-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and gate drive circuit |
| CN103106881A (en) * | 2013-01-23 | 2013-05-15 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN103345911B (en) * | 2013-06-26 | 2016-02-17 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display device |
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