CN104537973A - Shifting register, grid drive circuit, array substrate and display panel - Google Patents
Shifting register, grid drive circuit, array substrate and display panel Download PDFInfo
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Abstract
The invention discloses shifting registers, grid drive circuits, an array substrate and a display panel. The shifting registers comprise first units used for generating scanning control signals and subprime trigger signals, and scanning signal generating units which are electrically connected with the first units and used for generating scanning signals. For the first units, when first control signals are high level and second control signals are low level, first input and output ends receive trigger signals, and second input and output ends output the subprime trigger signals; when the first control signals are low level and the second control signal are high level, the first input and output ends output the subprime trigger signals, and the second input and output ends receive the trigger signals. According to the technical scheme provided by the shifting registers, the grid drive circuits, the array substrate and the display panel, electric connections between the ports of all shifting registers which form the grid drive circuits are simplified, design spaces needed by the grid drive circuits can be decreased, so that narrow border of corresponding display panel is easy to achieve.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of shift register, gate driver circuit, array base palte and display panel.
Background technology
Recently, along with the development of display technique, the application of display panel is also more and more extensive.When display panel works, the gate driver circuit being arranged in display panel will produce sweep signal, to drive each sweep trace in array base palte seriatim, makes data-signal can be transferred to each pixel cell in array base palte.Above-mentioned sweep signal is produced by the shift register in gate driver circuit.
Along with display panel is to positive and negative demand of sweeping, occur that there is the positive and negative shift register sweeping function.Fig. 1 a is the structural representation of the shift register of prior art.As shown in Figure 1a, shift register comprises: the first NMOS tube NP1, second NMOS tube NP2, first PMOS MP1, second PMOS MP2, for receiving the first control signal input end U2D of the first control signal, for receiving the second control signal input end D2U of the second control signal, first input end IN_F, second input end IN_B, first output terminal OUT_F, second output terminal OUT_B and shift unit 10, wherein, the drain electrode of the first NMOS tube NP1 and the source electrode of the first PMOS MP1 are electrically connected and are electrically connected with first input end IN_F, the source electrode of the first NMOS tube NP1, the drain electrode of the first PMOS MP1, the source electrode of the second NMOS tube NP2 and the drain electrode of the second PMOS MP2 are electrically connected and are electrically connected with the first input end A0 of shift unit 10, the drain electrode of the second NMOS tube NP2 and the source electrode of the second PMOS MP2 are electrically connected and are electrically connected with the second input end IN_B, the grid of the first NMOS tube NP1 is electrically connected with the grid of the second PMOS MP2 and is electrically connected with the first signal control input end U2D, the grid of the first PMOS MP1 and the second NMOS tube NP2 is electrically connected and is electrically connected with secondary signal control input end D2U, first output terminal B0 of shift unit 10 is electrically connected with the first output terminal OUT_F of shift register and the second output terminal OUT_B respectively.
Fig. 1 b is the circuit diagram of the shift unit in Fig. 1 a.As shown in Figure 1 b, shift unit comprises three phase inverters (the first phase inverter A1, the second phase inverter A2 and the 3rd phase inverter A3), two clocked inverters (the first clocked inverter A4 and second clock phase inverter A5), Sheffer stroke gate A6, the first clock signal input terminal CKV1, second clock signal input part CKV2, first input end A0, the first output terminal B0 and a sweep signal output terminal GOUT.
By above-mentioned shift register is electrically connected step by step and can obtains gate driver circuit, wherein, for arbitrary neighborhood three grades of shift registers, the first input end IN_F of middle one-level shift register is electrically connected with the first output terminal OUT_F of its upper level shift register, second input end IN_B of middle one-level shift register is electrically connected with the second output terminal OUT_B of its next stage shift register, first output terminal OUT_F of middle one-level shift register is electrically connected with the first input end IN_F of its next stage shift register, second output terminal OUT_B of middle one-level shift register is electrically connected with the second input end IN_B of its upper level shift register, the secondary trigger pip output terminal of upper level shift register is electrically connected with the trigger pip input end of next stage driver element, first control signal input end U2D of shift register at different levels is electrically connected and as the first control signal end of gate driver circuit, second control signal end D2U of shift register at different levels is electrically connected and as the second control signal input end of gate driver circuit.
For gate driver circuit, when just sweeping, first control signal is high level, second control signal is low level, trigger pip inputs from the first input end of first order shift register, and the first input end of shift unit is transferred to from the first NMOS tube of conducting and the first PMOS, export from the first output terminal of shift unit again and export to the first input end of its next stage shift register through the first output terminal of this grade of shift register, similarly, remain shift register at different levels to work successively, complete just inswept journey to make gate driver circuit; When counter sweeping, first control signal is low level, second control signal is high level, trigger pip is from the second input end input of afterbody shift register, and the first input end of shift unit is transferred to from the second NMOS tube of conducting and the second PMOS, export from the first output terminal of shift unit again and export to the second input end of its upper level shift register through the second output terminal of this grade of shift register, similarly, remain shift register at different levels to work successively, complete anti-inswept journey to make gate driver circuit.
In prior art, be there is the positive and negative input end (first input end IN_F and the second input end IN_B) sweeping the trigger pip of the shift register of function arranged with shift unit 10 is independent by above-mentioned, and the trigger pip entering shift unit 10 can export from its first output terminal B0, the external-connected port of such shift register is more, not only make form gate driver circuit shift registers at different levels port between electrical connection more complicated, and make the circuit structure more complicated of corresponding shift register, and display panel is made to be difficult to realize narrow frame.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of shift register, gate driver circuit, array base palte and display panel, makes display panel be difficult to realize the technical matters of narrow frame with the circuit structure more complicated of the electrical connection more complicated between the port solving in prior art the shift registers at different levels being formed gate driver circuit and corresponding shift register.
First aspect, the embodiment of the present invention provides a kind of shift register, comprise: first module and sweep signal generation unit, wherein, described first module is for generation of scan control signal and secondary trigger pip, wherein, described first module comprises the first control signal input end, second control signal input end, first input/output terminal, second input/output terminal and the scan control signal output terminal for exporting described scan control signal, and when the first control signal that described first control signal input end receives is high level and the second control signal that described second control signal input end receives is low level, described first input/output terminal is for receiving trigger pip, described second input/output terminal is for exporting secondary trigger pip, when described first control signal is low level and described second control signal is high level, described first input/output terminal is for exporting described secondary trigger pip, and described second input/output terminal is for receiving described trigger pip,
Described sweep signal generation unit comprises scan control signal input end, and described scan control signal input end is electrically connected with the scan control signal output terminal of described first module, and described sweep signal generation unit is for generation of sweep signal.
Second aspect, the embodiment of the present invention also provides a kind of gate driver circuit, comprise: the shift register described in the above-mentioned first aspect of M level, M be greater than 1 positive integer, wherein, for arbitrary neighborhood two-stage shift register, the first input/output terminal of rear stage shift register is electrically connected with the second input/output terminal of its previous stage shift register.
The third aspect, the embodiment of the present invention also provides a kind of array base palte, comprises the gate driver circuit described in above-mentioned second aspect.
Fourth aspect, the embodiment of the present invention also provides a kind of display panel, comprises the array base palte described in the above-mentioned third aspect.
The shift register that the embodiment of the present invention provides, gate driver circuit, array base palte and display panel, by arranging the first module of the secondary trigger pip for generation of scan control signal in a shift register, wherein first module comprises the first input/output terminal and the second input/output terminal, when the first control signal that the first control signal input end receives is high level and the second control signal that the second control signal input end receives is low level, first input/output terminal is for receiving trigger pip, and the second input/output terminal is for exporting secondary trigger pip; When the first control signal is low level and the second control signal is high level, first input/output terminal is for exporting secondary trigger pip, second input/output terminal is for receiving trigger pip, namely the first input/output terminal and the second input/output terminal all have the function of input end and output terminal, can simplify like this form gate driver circuit shift registers at different levels port between electrical connection, also can reduce the design space needed for gate driver circuit, thus corresponding display panel can be made to be easy to realize narrow frame.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 a is the structural representation of the shift register of prior art;
Fig. 1 b is the circuit diagram of shift unit in Fig. 1 a;
Fig. 2 is the structural representation of a kind of shift register that the embodiment of the present invention provides;
Fig. 3 a is the circuit diagram of a kind of first module that the embodiment of the present invention provides;
Fig. 3 b is a kind of sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal;
Fig. 3 c is the another kind of sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal;
Fig. 4 a is the circuit diagram of a kind of sweep signal generation unit that the embodiment of the present invention provides;
Fig. 4 b is a kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 4 a;
Fig. 4 c is the circuit diagram of the another kind of sweep signal generation unit that the embodiment of the present invention provides;
Fig. 5 a is the circuit diagram of a kind of shift register that the embodiment of the present invention provides;
Fig. 5 b is a kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 5 a;
Fig. 5 c is the another kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 5 a;
Fig. 6 a is the structural representation of a kind of gate driver circuit that the embodiment of the present invention provides;
Fig. 6 b is the structural representation of the another kind of gate driver circuit that the embodiment of the present invention provides;
Fig. 7 a is the structural representation of the embodiment of a kind of gate driver circuit that the embodiment of the present invention provides;
Fig. 7 b is the sequential chart of each signal when gate driver circuit is just swept in Fig. 7 a;
The sequential chart of each signal of Fig. 7 c when to be that in Fig. 7 a, gate driver circuit is counter sweep;
Fig. 8 is the structural representation of a kind of array base palte that the embodiment of the present invention provides;
Fig. 9 is the structural representation of a kind of display panel that the embodiment of the present invention provides.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
The embodiment of the present invention provides a kind of shift register.Fig. 2 is the structural representation of a kind of shift register that the embodiment of the present invention provides.As shown in Figure 2, shift register comprises: first module 21 and sweep signal generation unit 22, wherein, first module 21 is for generation of scan control signal and secondary trigger pip, wherein, first module 21 comprises the first control signal input end U2D, second control signal input end D2U, first input/output terminal IO1, second input/output terminal IO2 and the scan control signal output terminal GTV for exporting scan control signal, and when the first control signal that the first control signal input end U2D receives is high level and the second control signal that the second control signal input end D2U receives is low level, first input/output terminal IO1 is for receiving trigger pip, second input/output terminal IO2 is for exporting secondary trigger pip, when the first control signal is low level and the second control signal is high level, the first input/output terminal IO1 is for exporting secondary trigger pip, and the second input/output terminal IO2 is for receiving trigger pip, sweep signal generation unit 22 comprises scan control signal input end GTVI, and scan control signal input end GTVI is electrically connected with the scan control signal output terminal GTV of first module 21, and wherein, sweep signal generation unit 22 is for generation of sweep signal.
As mentioned above, when the first control signal is high level and the second control signal is low level, the first input/output terminal IO1 is for receiving trigger pip, and the second input/output terminal IO2 is for exporting secondary trigger pip, when the first control signal is low level and the second control signal is high level, first input/output terminal IO1 is for exporting secondary trigger pip, second input/output terminal IO2 is for receiving trigger pip, this shows that the first input/output terminal IO1 and the second input/output terminal IO2 all has the function of input end and output terminal, namely time as input end, for receiving trigger pip, during as output terminal, for exporting secondary trigger pip, therefore, with the input end for receiving trigger pip and the output terminal for exporting secondary trigger pip, only there is corresponding simple function to compare, technical scheme of the present invention can simplify the circuit structure of shift register.
In an embodiment of the present invention, further, as shown in Figure 3 a, first module, except comprising the first control signal input end U2D in Fig. 1, the second control signal input end D2U, the first input/output terminal IO1, the second input/output terminal IO2 and scan control signal output terminal GTV, can also comprise the first clocked inverter CINV1, second clock phase inverter CINV2, the 3rd clocked inverter CINV3, the 4th clocked inverter CINV4, the first phase inverter INV1 and the first clock signal input terminal CKV1; Wherein, the input end of the first clocked inverter CINV1 is electrically connected with the first input/output terminal IO1, first control end of the first clocked inverter CINV1 is electrically connected with the output terminal of the first phase inverter INV1, second control end of the first clocked inverter CINV1 is electrically connected with the first clock signal input terminal CKV1, and the output terminal of the first clocked inverter CINV1 is electrically connected with the output terminal of second clock phase inverter CINV2; The input end of second clock phase inverter CINV2 is electrically connected with scan control signal output terminal GTV and the second input/output terminal IO2 respectively, first control end of second clock phase inverter CINV2 is electrically connected with the first clock signal input terminal CKV1, and second control end of second clock phase inverter CINV2 is electrically connected with the output terminal of the first phase inverter INV1; The input end of the 3rd clocked inverter CINV3 is electrically connected with the output terminal of second clock phase inverter CINV2, first control end of the 3rd clocked inverter CINV3 is electrically connected with the first control signal input end U2D, second control end of the 3rd clocked inverter CINV3 is electrically connected with the second control signal input end D2U, and the output terminal of the 3rd clocked inverter CINV3 is electrically connected with the first input/output terminal IO1; The input end of the 4th clocked inverter CINV4 is electrically connected with the output terminal of second clock phase inverter CINV2, first control end of the 4th clocked inverter CINV4 is electrically connected with the second control signal input end D2U, second control end of the 4th clocked inverter CINV4 is electrically connected with described first control signal input end U2D, and the output terminal of the 4th clocked inverter CINV4 is electrically connected with the second input/output terminal IO2; The input end of the first phase inverter INV1 is electrically connected with the first clock signal input terminal CKV1.
In embodiments of the present invention, the first control signal and the second control signal inversion signal each other.By making the first control signal and the second control signal inversion signal each other, and the control to first module, when can make the first input/output terminal as input end, second input/output terminal is as output terminal, or when can make the first input/output terminal as output terminal, second input/output terminal, as input end, that is, makes the first input/output terminal and the second input/output terminal all have the function of input end and output terminal.
In embodiments of the present invention, the first clock signal input terminal CKV1 is for receiving the first clock signal.By the first clock signal, the first control signal and the second control signal to the control of first module, first module can be made to produce scan control signal and secondary trigger pip.
Fig. 3 b is a kind of sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal; Fig. 3 c is the another kind of sequential chart of the input signal of each input end in Fig. 3 a and the output signal of each output terminal.Wherein, in Fig. 3 b and Fig. 3 c, the trigger pip that STV representative is received by the first input/output terminal IO1 or the second input/output terminal IO2; SCKV1 represents the first clock signal that the first clock signal input terminal CKV1 receives; SU2D represents the first control signal that the first control signal input end U2D receives; SD2U represents the second control signal that the second control signal input end D2U receives; SGTV represents the scan control signal that scan control signal output terminal GTV exports; The secondary trigger pip that SSTV representative is exported by the first input/output terminal IO1 or the second input/output terminal IO2.And in fig 3b, the first control signal SU2D is high level, the second control signal SD2U is low level; In figure 3 c, the first control signal SU2D is low level, and the second control signal SD2U is high level.Next, the principle of work of composition graphs 3b and Fig. 3 c to the first module shown in Fig. 3 a is done and is described further respectively.
As shown in Figure 3 b, because the first control signal SU2D is high level, second control signal SD2U is low level, therefore, sequential chart shown in corresponding diagram 3b, the first input/output terminal IO1 in Fig. 3 a is for receiving trigger pip STV, and the second input/output terminal IO2 is for exporting secondary trigger pip SSTV, and the input end of the 3rd clocked inverter CINV3 and output terminal disconnect, the 4th clocked inverter CINV4 is equivalent to a phase inverter.
In the T11 stage, trigger pip STV is high level, first clock signal SCKV1 is high level, first clocked inverter CINV1 is equivalent to a phase inverter, the input end of second clock phase inverter CINV2 and output terminal disconnect, namely in the T11 stage, the equivalent electrical circuit of first module is: the first input/output terminal IO1 is electrically connected with the second input/output terminal IO2 by two phase inverters be electrically connected in series, the trigger pip that first input/output terminal IO1 receives exports from the second input/output terminal IO2 after the effect of the phase inverter of two series connection, therefore, the secondary trigger pip that this stage second input/output terminal IO2 exports is high level.
In the T12 stage, first clock signal SCKV1 becomes low level, the input end of the first clocked inverter CINV1 and output terminal disconnect, second clock phase inverter CINV2 is equivalent to a phase inverter, namely in the T12 stage, the equivalent electrical circuit of first module is: the second input/output terminal IO2 is electrically connected with the phase inverter of two reverse parallel connections, and therefore, the secondary trigger pip exported at this stage second input/output terminal IO2 is still high level.
In the T13 stage, trigger pip STV is low level, first clock signal SCKV1 first becomes high level from the low level in T12 stage, the equivalent electrical circuit of corresponding first module is identical with the equivalent electrical circuit of the first module in T11 stage, therefore, for the T13 stage, when the first clock signal SCKV1 is high level, the secondary trigger pip that the second input/output terminal IO2 exports is low level; Then the first clock signal SCKV1 becomes low level from high level again, the equivalent electrical circuit of corresponding first module is identical with the equivalent electrical circuit of the first module in T12 stage, therefore, for the T13 stage, when the first clock signal SCKV1 is low level, the secondary trigger pip that the second input/output terminal IO2 exports is still low level.
In above-mentioned T11, T12 and T13 stage, scan control signal SGTV is identical with the secondary trigger pip that the second input/output terminal IO2 exports.It is known by the description of the above-mentioned principle of work to first module: when the first control signal SU2D is high level and the second control signal SD2U is low level, first input/output terminal IO1 is for receiving trigger pip STV, second input/output terminal IO2 is for exporting secondary trigger pip SSTV, and first module can realize the function of latch.
As shown in Figure 3 c, because the first control signal SU2D is low level, second control signal SD2U is high level, therefore, sequential chart shown in corresponding diagram 3c, the first input/output terminal IO1 in Fig. 3 a is for exporting secondary trigger pip SSTV, and the second input/output terminal IO2 is for receiving trigger pip STV, and the 3rd clocked inverter CINV3 is equivalent to a phase inverter, the input end of the 4th clocked inverter CINV4 and output terminal disconnect.
In the T21 stage, trigger pip STV is high level, first clock signal SCKV1 is low level, the input end of the first clocked inverter CINV1 and output terminal disconnect and are equivalent to a phase inverter, second clock phase inverter CINV2 is equivalent to a phase inverter, namely in the T11 stage, the equivalent electrical circuit of first module is: the second input/output terminal IO2 is electrically connected with the first input/output terminal IO1 by two phase inverters be electrically connected in series, the trigger pip that second input/output terminal IO2 receives exports from the first input/output terminal IO2 after the effect of the phase inverter of two series connection, therefore, the secondary trigger pip that this stage first input/output terminal IO1 exports is high level.
In the T22 stage, first clock signal SCKV1 becomes high level, first clocked inverter CINV1 is equivalent to input end and the output terminal disconnection of a phase inverter, the input end of second clock phase inverter CINV2 and output terminal disconnect, namely in the T22 stage, the equivalent electrical circuit of first module is: the first input/output terminal IO1 is electrically connected with the phase inverter of two reverse parallel connections, and therefore, the secondary trigger pip exported at this stage first input/output terminal IO1 is still high level.
In the T23 stage, trigger pip STV is low level, first clock signal SCKV1 first becomes low level from the high level in T22 stage, the equivalent electrical circuit of corresponding first module is identical with the equivalent electrical circuit of the first module in T21 stage, therefore, for the T23 stage, when the first clock signal SCKV1 is low level, the secondary trigger pip that the first input/output terminal IO1 exports is low level; Then the first clock signal SCKV1 becomes high level from low level again, the equivalent electrical circuit of corresponding first module is identical with the equivalent electrical circuit of the first module in T22 stage, therefore, for the T23 stage, when the first clock signal SCKV1 is high level, the secondary trigger pip that the first input/output terminal IO1 exports is still low level.
In above-mentioned T21, T22 and T23 stage, scan control signal SGTV is identical with the trigger pip that the second input/output terminal IO2 inputs.It is known by the description of the above-mentioned principle of work to first module: when the first control signal SU2D is low level and the second control signal SD2U is high level, first input/output terminal IO1 is for exporting secondary trigger pip SSTV, second input/output terminal IO2 is for receiving trigger pip STV, and first module can realize the function of latch.Therefore, first module shown in corresponding diagram 3a, no matter be that the first input/output terminal receives trigger pip as input end, second input/output terminal exports secondary trigger pip as output terminal, or the first input/output terminal exports secondary trigger pip as output terminal, second input/output terminal receives trigger pip as input end, and first module can both realize the function latched.
In embodiments of the present invention, further, sweep signal generation unit, except comprising the scan control signal input end GTVI in Fig. 1, can also comprise the first Sheffer stroke gate NAND1, the second phase inverter INV2, second clock signal input part CKV2 and the sweep signal output terminal GOUT for exporting described sweep signal; The first input end of the first Sheffer stroke gate NAND1 is electrically connected with second clock signal input part CKV2, second input end of the first Sheffer stroke gate NAND1 is electrically connected with scan control signal input end GTVI, the output terminal of the first Sheffer stroke gate NAND1 is electrically connected with the input end of the second phase inverter INV2, and the output terminal of the second phase inverter INV2 is electrically connected with sweep signal output terminal GOUT.
In embodiments of the present invention, second clock signal input part CKV2 for receiving second clock signal, wherein, the first clock signal and second clock signal inversion signal each other.By making the first clock signal and second clock signal inversion signal each other, and two signals are to the control of shift register, and shift register can be made to realize the function of shift LD.
Fig. 4 b is a kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 4 a.In fig. 4b, SCKV2 represents the second clock signal that second clock signal input part CKV2 receives; SGTVI represents the scan control signal that scan control signal input end GTVI receives; SGOUT represents the sweep signal that sweep signal output terminal GOUT exports.As shown in Figure 4 b, when the scan control signal SGTVI being input to sweep signal generation unit is high level and second clock signal SCKV is also high level, the sweep signal SGOUT that sweep signal generation unit exports is high level.
The sweep signal produced due to the sweep signal generation unit in Fig. 4 a is more weak, therefore, in order to the sweep signal that the sweep signal generation unit strengthened in Fig. 4 a produces, as illustrated in fig. 4 c, sweep signal generation unit can also comprise the second Sheffer stroke gate NAND2, N number of the 3rd phase inverter INV3, the second clock signal input part CKV2 that are electrically connected in series and the sweep signal output terminal GOUT for exporting described sweep signal, wherein, N be greater than 1 odd number; The first input end of the second Sheffer stroke gate NAND2 is electrically connected with second clock signal input part CKV2, second input end of the second Sheffer stroke gate NAND2 is electrically connected with scan control signal input end GTVI, the output terminal of the second Sheffer stroke gate NAND2 is electrically connected with the input end of first the 3rd phase inverter INV3, and the output terminal of N number of described 3rd phase inverter INV3 is electrically connected with sweep signal output terminal GOUT.
Next the principle of the circuit shown in Fig. 4 a to shift register is adopted to be described further for sweep signal generation unit.
Fig. 5 a is the circuit diagram of a kind of shift register that the embodiment of the present invention provides.The circuit of the shift register shown in Fig. 5 a obtains by being electrically connected by the scan control signal input end GTVI of the sweep signal generation unit in the scan control signal output terminal GTV of the first module in Fig. 3 a and Fig. 4 a.Fig. 5 b is a kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 5 a.In figure 5b, the first control signal SU2D is high level, and the second control signal SD2U is low level, and correspondingly, the first input/output terminal IO1 in Fig. 5 a is for receiving trigger pip STV, and the second input/output terminal IO2 is for exporting secondary trigger pip SSTV.In figure 5b, when the first clock signal SCKV1 and second clock signal SCKV2 is initial, be low level, then alternately export the signal of high level.And when scan control signal SGTV is high level, when second clock signal SCKV2 is high level, it is high level that shift register exports sweep signal SGOUT from sweep signal output terminal GOUT.
Fig. 5 c is the another kind of sequential chart of the input signal of each input end and the output signal of output terminal in Fig. 5 a.In fig. 5 c, the first control signal SU2D is low level, and the second control signal SD2U is high level, and correspondingly, the first input/output terminal IO1 in Fig. 5 a is for exporting secondary trigger pip SSTV, and the second input/output terminal IO2 is for receiving trigger pip STV.In fig. 5 c, when the first clock signal SCKV1 and second clock signal SCKV2 is initial, be high level, then replace the signal of output low level.And when scan control signal SGTV is high level, when second clock signal SCKV2 is high level, it is high level that shift register exports sweep signal SGOUT from sweep signal output terminal GOUT.
The sequential chart given by Fig. 5 b and Fig. 5 c and relevant description known, the circuit of the shift register in Fig. 5 a, no matter be that the first input/output terminal receives trigger pip as input end, second input/output terminal exports secondary trigger pip as output terminal, or the first input/output terminal exports secondary trigger pip as output terminal, second input/output terminal receives trigger pip as input end, and shift register can both realize corresponding function.
The embodiment of the present invention also provides a kind of gate driver circuit.Fig. 6 a is the structural representation of a kind of gate driver circuit that the embodiment of the present invention provides.As shown in Figure 6 a, gate driver circuit comprises M level shift register, M be greater than 1 positive integer, wherein, for arbitrary neighborhood two-stage shift register, first input/output terminal IO1 of rear stage shift register is electrically connected with the second input/output terminal IO2 of its previous stage shift register, and wherein, described shift register is the shift register described in each embodiment above-mentioned.
The shift registers at different levels forming gate driver circuit in the embodiment of the present invention realize electrical connection by the first input/output terminal and the second input/output terminal, the electrical connection between the port that can simplify shift register at different levels like this; And the shift register forming gate driver circuit has the circuit structure of simplification, therefore, can reduce the design space needed for gate driver circuit.
In Fig. 6 a, gate driver circuit also comprises the first NMOS tube NM1, the second NMOS tube NM2, the first control signal wire u2d, the second control signal wire to d2u and line trigger signal stv; Wherein, the first input/output terminal IO1 of first order shift register is electrically connected with the source electrode of the first NMOS tube NM1, and the drain electrode of the first NMOS tube NM1 is electrically connected with line trigger signal stv, and the grid of the first NMOS tube NM1 is electrically connected with the first control signal wire u2d; First control signal input end U2D of shift register at different levels is electrically connected with the first control signal wire u2d, and the second control signal input end D2U of shift register at different levels is electrically connected with the second control signal wire d2u; Second input/output terminal IO2 of M level shift register is electrically connected with the source electrode of the second NMOS tube NM2, and the drain electrode of the second NMOS tube NM2 is electrically connected with line trigger signal stv, and the grid of the second NMOS tube NM2 is electrically connected with described second control signal wire d2u.Particularly, the first control signal end that first control signal wire u2d is shift register at different levels provides the first control signal, the second control signal end that second control signal wire d2u is shift register at different levels provides the second control signal, and line trigger signal stv provides trigger pip for the first order shift register that is connected electrically or M level shift register.
In Fig. 6 a, gate driver circuit also comprises: the first clock cable ckv1 and second clock signal wire ckv2, wherein, the first clock signal input terminal CKV1 of adjacent two-stage shift register and second clock signal input part CKV2 is alternately electrically connected with the first clock cable ckv1 and second clock signal wire ckv2 respectively.Particularly, in Fig. 6 a, the first clock signal input terminal CKV1 of odd level shift register is electrically connected with the first clock cable ckv1, and second clock signal input part CKV2 is electrically connected with second clock signal wire ckv2; First clock signal input terminal CKV1 of even level shift register is electrically connected with second clock signal wire ckv2, and second clock signal input part CKV2 is electrically connected with the first clock cable ckv1.Wherein, the first clock signal input terminal CKV1 of M level shift register is electrically connected with the first clock cable ckv1, and second clock signal input part CKV2 is electrically connected with second clock signal wire ckv2, and namely M level shift register belongs to odd level shift register.But, in other concrete example, M level shift register also can belong to even level shift register, namely the first clock signal input terminal CKV1 of M level shift register is electrically connected with second clock signal wire ckv2, second clock signal input part CKV2 is electrically connected with the first clock cable ckv1, in this no limit.
In Fig. 6 a, when the first control signal is high level and the second control signal is low level, first NMOS tube NM1 conducting, second NMOS tube NM2 cut-off, the trigger pip that line trigger signal stv provides is transferred to the first input/output terminal IO1 of first order shift register by the first NMOS tube NM1 of conducting, namely the first input/output terminal IO1 of first order shift register receives trigger pip as input end, correspondingly, gate driver circuit exports sweep signal (namely exporting corresponding sweep signal successively from sweep signal output terminal GOUT1 to the GOUTM Fig. 6 a) according to the first clock signal and second clock signal successively from first order shift register to M level shift register, when the first control signal is low level and the second control signal is high level, first NMOS tube NM1 cut-off, second NMOS tube NM2 conducting, the trigger pip that line trigger signal stv provides is transferred to the second input/output terminal IO2 of M level shift register by the second NMOS tube NM2 of conducting, namely the second input/output terminal of M level shift register receives trigger pip as input end, correspondingly, gate driver circuit exports sweep signal (namely exporting corresponding sweep signal successively from sweep signal output terminal GOUTM to the GOUT1 Fig. 6 a) according to the first clock signal and described second clock signal successively from M level shift register to first order shift register, therefore, gate driver circuit achieves once just inswept journey.
Except the gate driver circuit shown in Fig. 6 a, as shown in Figure 6 b, gate driver circuit also can comprise the first PMOS PM1, the second PMOS PM2, the first control signal wire u2d, the second control signal wire d2u first clock cable ckv1, second clock signal wire ckv2 and line trigger signal stv; First input/output terminal IO1 of first order shift register is electrically connected with the drain electrode of the first PMOS PM1, and the source electrode of the first PMOS PM1 is electrically connected with described line trigger signal stv, and the grid of the first PMOS PM1 is electrically connected with the second control signal wire d2u; First control signal input end U2D of shift register at different levels is electrically connected with described first control signal wire u2d, and the second control signal input end D2U of shift register at different levels is electrically connected with described second control signal wire d2u; Second input/output terminal IO2 of M level shift register is electrically connected with the drain electrode of the second PMOS PM2, and the source electrode of the second PMOS PM2 is electrically connected with line trigger signal stv, and the grid of the second PMOS PM2 is electrically connected with the first control signal wire u2d; First clock signal input terminal CKV1 of adjacent two-stage shift register and second clock signal input part CKV2 is alternately electrically connected with the first clock cable ckv1 and second clock signal wire ckv2 respectively.Particularly, in figure 6b, the first clock signal input terminal CKV1 of odd level shift register is electrically connected with the first clock cable ckv1, and second clock signal input part CKV2 is electrically connected with second clock signal wire ckv2; First clock signal input terminal CKV1 of even level shift register is electrically connected with second clock signal wire ckv2, and second clock signal input part CKV2 is electrically connected with the first clock cable ckv1.Wherein, the first clock signal input terminal CKV1 of M level shift register is electrically connected with the first clock cable ckv1, and second clock signal input part CKV2 is electrically connected with second clock signal wire ckv2, and namely M level shift register belongs to odd level shift register.But, in other concrete example, M level shift register also can belong to even level shift register, namely the first clock signal input terminal CKV1 of M level shift register is electrically connected with second clock signal wire ckv2, second clock signal input part CKV2 is electrically connected with the first clock cable ckv1, in this no limit.
In figure 6b, when the first control signal is high level and the second control signal is low level, first PMOS PM1 conducting, second PMOS PM2 cut-off, the trigger pip that line trigger signal stv provides is transferred to the first input/output terminal IO1 of first order shift register by the first PMOS PM1 of conducting, namely the first input/output terminal IO1 of first order shift register receives trigger pip as input end, correspondingly, gate driver circuit exports sweep signal (namely exporting corresponding sweep signal successively from sweep signal output terminal GOUT1 to the GOUTM Fig. 6 b) according to the first clock signal and second clock signal successively from first order shift register to M level shift register, when the first control signal is low level and the second control signal is high level, first PMOS PM1 cut-off, second PMOS PM2 conducting, the trigger pip that line trigger signal stv provides is transferred to the second input/output terminal IO2 of M level shift register by the second PMOS PM2 of conducting, namely the second input/output terminal IO2 of M level shift register receives trigger pip as input end, correspondingly, described gate driver circuit exports sweep signal (namely exporting corresponding sweep signal successively from sweep signal output terminal GOUTM to the GOUT1 Fig. 6 b) according to described first clock signal and described second clock signal successively from M level shift register to first order shift register, therefore, gate driver circuit achieves once anti-inswept journey.
Because the principle of work of the gate driver circuit shown in Fig. 6 a with Fig. 6 b is identical, therefore, be next only described further for the principle of work of gate driver circuit to gate driver circuit shown in Fig. 6 a.
Fig. 7 a is the structural representation of the embodiment of a kind of gate driver circuit that the embodiment of the present invention provides.As shown in Figure 7a, gate driver circuit comprises the shift register of level Four electrical connection, namely gets 4 to obtain by the progression M of the shift register by the gate driver circuit in Fig. 6 a.Fig. 7 b is the sequential chart of each signal when gate driver circuit is just swept in Fig. 7 a.In fig .7b, STV represents trigger pip; SCKV1 represents the first clock signal; SCKV2 represents second clock signal; SU2D represents the first control signal; SD2U represents the second control signal; The scan control signal that the sweep signal output terminal GOUT1 that SGOUT1 to SGOUT4 represents first order shift register respectively to the sweep signal output terminal GOUT4 of fourth stage shift register exports; And in fig .7b, the first control signal SU2D is high level, the second control signal SD2U is low level, and the first clock signal SCKV1 and second clock signal SCKV2 is initially low level, then alternately exports high level; Trigger pip STV covers first high level of the first clock signal SCKV1, then from first high level of second clock signal SCKV2, export the sweep signal SGOUT4 of sweep signal SGOUT1 to fourth stage shift register of first order shift register successively, thus make gate driver circuit complete once just inswept journey.
The sequential chart of each signal of Fig. 7 c when to be that in Fig. 7 a, gate driver circuit is counter sweep.In figure 7 c, the first control signal SU2D is low level, and the second control signal SD2U is high level, and the first clock signal SCKV1 and second clock signal SCKV2 is initially high level, then replaces output low level; Trigger pip STV covers first low level of second clock signal SCKV2, and from first low level of second clock signal SCKV2, export the sweep signal SGOUT1 of sweep signal SGOUT4 to first order shift register of fourth stage shift register successively, thus gate driver circuit is made to complete once anti-inswept journey.
As mentioned above, the gate driver circuit that the embodiment of the present invention provides has positive and negative function of sweeping.
The embodiment of the present invention also provides a kind of array base palte.Fig. 8 is the structural representation of a kind of array base palte that the embodiment of the present invention provides.As shown in Figure 8, array base palte comprise gate driver circuit 31, data drive circuit 32, a plurality of data lines (D1, D2 ..., Dk), multi-strip scanning line (S1, S2 ..., Sm) and intersect by a plurality of data lines and multi-strip scanning line the multiple pixel cells 33 limited, wherein pixel cell 33 comprises thin film transistor (TFT) 331 and the pixel electrode 332 be connected electrically, and wherein gate driver circuit 31 is the gate driver circuit described in the various embodiments described above.
Particularly, gate driver circuit 31, for each bar sweep trace (S1, S2 ..., Sm) sweep signal is provided, wherein, the sweep signal output terminal of the shift registers at different levels in gate driver circuit 31 is electrically connected a sweep trace; Data drive circuit 32, for pieces of data line (D1, D2 ..., Dk) data-signal is provided; The grid of the thin film transistor (TFT) 331 in pixel cell 33 is electrically connected with a sweep trace, the source electrode of thin film transistor (TFT) 331 is electrically connected with a data line, the drain electrode of thin film transistor (TFT) 331 and being electrically connected with its pixel electrode 332 being arranged in same pixel cell 33, the sweep signal that sweep trace provides can control unlatching or the closedown of thin film transistor (TFT) 331, the data-signal that data line provides can be transferred to pixel electrode 332 by the thin film transistor (TFT) 331 opened, thus realizes the corresponding display frame of display.
Have employed the gate driver circuit in above-described embodiment due to array base palte, and design space needed for this gate driver circuit is less, therefore, array base palte can be made to be easy to realize narrow frame.
The embodiment of the present invention also provides a kind of display panel.Fig. 9 is the structural representation of a kind of display panel that the embodiment of the present invention provides.See Fig. 9, display panel comprises array base palte 42 that counter substrate 41 and counter substrate 41 be oppositely arranged, middle layer 43 between counter substrate 41 and array base palte 42.Wherein, array base palte 42 is the array base palte described in above-described embodiment.
Particularly, middle layer 43 is relevant with the display type of display panel.When adopting liquid crystal display, middle layer 43 is liquid crystal layer, counter substrate 41 can be color membrane substrates, by the electric field (corresponding twisted nematic) that formed between the public electrode that is arranged in counter substrate 41 and the pixel electrode being arranged in array base palte 42 or the rotation controlling the liquid crystal molecule in liquid crystal layer by being arranged on the electric field (corresponding edge field switch type or plane conversion type) formed between public electrode in array base palte 42 and pixel electrode, thus realize display effect.
As employing Organic Light Emitting Diode (Organic Light-Emitting Diode, be called for short OLED) when showing, middle layer 43 is for arranging organic luminous layer, counter substrate 41 can be color membrane substrates, packaged glass (Cover Glass) or cover-plate glass (Cover Lens) etc., controls organic luminous layer luminescence realize display effect by array base palte 42.
It should be noted that, above-mentioned display panel can have touch controllable function, also can not have touch controllable function, when actual fabrication, can carry out Choice and design according to concrete needs.Wherein, touch controllable function can be electromagnetic touch function, capacitive touch function or electromagnetism capacitive touch function etc.
Above-mentioned display panel can be applied in the display device such as mobile phone, desktop computer, notebook, panel computer, electron album and Electronic Paper.
The shift register that the embodiment of the present invention provides, gate driver circuit, array base palte and display panel, by arranging the first module of the secondary trigger pip for generation of scan control signal in a shift register, wherein first module comprises the first input/output terminal and the second input/output terminal, when the first control signal that the first control signal input end receives is high level and the second control signal that the second control signal input end receives is low level, first input/output terminal is for receiving trigger pip, and the second input/output terminal is for exporting secondary trigger pip; When the first control signal is low level and the second control signal is high level, first input/output terminal is for exporting secondary trigger pip, second input/output terminal is for receiving trigger pip, namely the first input/output terminal and the second input/output terminal all have the function of input end and output terminal, so not only can simplify form gate driver circuit shift registers at different levels port between electrical connection, the design space needed for gate driver circuit can also be reduced, thus corresponding display panel can be made to be easy to realize narrow frame.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (13)
1. a shift register, is characterized in that, comprising: first module and sweep signal generation unit, wherein,
Described first module is for generation of scan control signal and secondary trigger pip, wherein, described first module comprises the first control signal input end, second control signal input end, first input/output terminal, second input/output terminal and the scan control signal output terminal for exporting described scan control signal, and when the first control signal that described first control signal input end receives is high level and the second control signal that described second control signal input end receives is low level, described first input/output terminal is for receiving trigger pip, described second input/output terminal is for exporting secondary trigger pip, when described first control signal is low level and described second control signal is high level, described first input/output terminal is for exporting described secondary trigger pip, and described second input/output terminal is for receiving described trigger pip,
Described sweep signal generation unit comprises scan control signal input end, and described scan control signal input end is electrically connected with the scan control signal output terminal of described first module, and described sweep signal generation unit is for generation of sweep signal.
2. shift register according to claim 1, is characterized in that, described first module also comprises the first clocked inverter, second clock phase inverter, the 3rd clocked inverter, the 4th clocked inverter, the first phase inverter and the first clock signal input terminal;
The input end of described first clocked inverter is electrically connected with described first input/output terminal, first control end of described first clocked inverter is electrically connected with the output terminal of described first phase inverter, second control end of described first clocked inverter is electrically connected with described first clock signal input terminal, and the output terminal of described first clocked inverter is electrically connected with the output terminal of described second clock phase inverter;
The input end of described second clock phase inverter is electrically connected with described scan control signal output terminal and described second input/output terminal respectively, first control end of described second clock phase inverter is electrically connected with described first clock signal input terminal, and the second control end of described second clock phase inverter is electrically connected with the output terminal of described first phase inverter;
The input end of described 3rd clocked inverter is electrically connected with the output terminal of described second clock phase inverter, first control end of described 3rd clocked inverter is electrically connected with described first control signal input end, second control end of described 3rd clocked inverter is electrically connected with described second control signal input end, and the output terminal of described 3rd clocked inverter is electrically connected with described first input/output terminal;
The input end of described 4th clocked inverter is electrically connected with the output terminal of described second clock phase inverter, first control end of described 4th clocked inverter is electrically connected with described second control signal input end, second control end of described 4th clocked inverter is electrically connected with described first control signal input end, and the output terminal of described 4th clocked inverter is electrically connected with described second input/output terminal;
The input end of described first phase inverter is electrically connected with described first clock signal input terminal.
3. shift register according to claim 2, is characterized in that, described sweep signal generation unit also comprises the first Sheffer stroke gate, the second phase inverter, second clock signal input part and the sweep signal output terminal for exporting described sweep signal;
The first input end of described first Sheffer stroke gate is electrically connected with described second clock signal input part, second input end of described first Sheffer stroke gate is electrically connected with described scan control signal input end, the output terminal of described first Sheffer stroke gate is electrically connected with the input end of described second phase inverter, and the output terminal of described second phase inverter is electrically connected with described sweep signal output terminal.
4. shift register according to claim 2, it is characterized in that, described sweep signal generation unit also comprises the second Sheffer stroke gate, N number of the 3rd phase inverter, second clock signal input part and sweep signal output terminal for exporting described sweep signal be electrically connected in series, wherein, N be greater than 1 odd number;
The first input end of described second Sheffer stroke gate is electrically connected with described second clock signal input part, second input end of described second Sheffer stroke gate is electrically connected with described scan control signal input end, the output terminal of described second Sheffer stroke gate is electrically connected with the input end of first described 3rd phase inverter, and the output terminal of N number of described 3rd phase inverter is electrically connected with described sweep signal output terminal.
5. shift register according to claim 1, is characterized in that, described first control signal and described second control signal inversion signal each other.
6. the shift register according to claim 3 or 4, it is characterized in that, described first clock signal input terminal is for receiving the first clock signal, described second clock signal input part is for receiving second clock signal, wherein, described first clock signal and described second clock signal inversion signal each other.
7. a gate driver circuit, it is characterized in that, comprise the shift register of M level according to any one of claim 1-6, M be greater than 1 positive integer, wherein, for arbitrary neighborhood two-stage shift register, the first input/output terminal of rear stage shift register is electrically connected with the second input/output terminal of its previous stage shift register.
8. gate driver circuit according to claim 7, is characterized in that, described gate driver circuit also comprises the first NMOS tube, the second NMOS tube, the first control signal wire, the second control signal wire and line trigger signal;
First input/output terminal of first order shift register is electrically connected with the source electrode of described first NMOS tube, and the drain electrode of described first NMOS tube is electrically connected with described line trigger signal, and the grid of described first NMOS tube is electrically connected with described first control signal wire;
First control signal input end of shift register at different levels is electrically connected with described first control signal wire, and the second control signal input end of shift register at different levels is electrically connected with described second control signal wire;
Second input/output terminal of M level shift register is electrically connected with the source electrode of described second NMOS tube, and the drain electrode of described second NMOS tube is electrically connected with described line trigger signal, and the grid of described second NMOS tube is electrically connected with described second control signal wire.
9. gate driver circuit according to claim 7, is characterized in that, described gate driver circuit also comprises the first PMOS, the second PMOS, the first control signal wire, the second control signal wire and line trigger signal;
First input/output terminal of first order shift register is electrically connected with the drain electrode of described first PMOS, and the source electrode of described first PMOS is electrically connected with described line trigger signal, and the grid of described first PMOS is electrically connected with described second control signal wire;
First control signal input end of shift register at different levels is electrically connected with described first control signal wire, and the second control signal input end of shift register at different levels is electrically connected with described second control signal wire;
Second input/output terminal of M level shift register is electrically connected with the drain electrode of described second PMOS, and the source electrode of described second PMOS is electrically connected with described line trigger signal, and the grid of described second PMOS is electrically connected with described first control signal wire.
10. gate driver circuit according to claim 8 or claim 9, it is characterized in that, described gate driver circuit also comprises: the first clock cable and second clock signal wire;
First clock signal input terminal of adjacent two-stage shift register and second clock signal input part are alternately electrically connected with described first clock cable and described second clock signal wire respectively.
11. gate driver circuits according to claim 10, is characterized in that:
When the first control signal is high level and the second control signal is low level, described gate driver circuit successively exports sweep signal from first order shift register to M level shift register according to the first clock signal and second clock signal;
When described first control signal is low level and described second control signal is high level, described gate driver circuit successively exports sweep signal from M level shift register to first order shift register according to described first clock signal and described second clock signal.
12. 1 kinds of array base paltes, is characterized in that, comprise the gate driver circuit according to any one of claim 7-11.
13. 1 kinds of display panels, is characterized in that, comprise array base palte as claimed in claim 12.
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| CN201410834941.5A CN104537973A (en) | 2014-12-29 | 2014-12-29 | Shifting register, grid drive circuit, array substrate and display panel |
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Application publication date: 20150422 |