CN109256083A - Shift register cell and its driving method, gate driving circuit and display device - Google Patents
Shift register cell and its driving method, gate driving circuit and display device Download PDFInfo
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- CN109256083A CN109256083A CN201811409467.6A CN201811409467A CN109256083A CN 109256083 A CN109256083 A CN 109256083A CN 201811409467 A CN201811409467 A CN 201811409467A CN 109256083 A CN109256083 A CN 109256083A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The present invention provides a kind of shift register cell and its driving method, gate driving circuit and display device.Shift register cell includes input module, reseting module, first switching element, pull-down module, auxiliary pull-down module, first capacitor and the second capacitor.First switching element is both used to pull up and is also used for pulling down, coupling when using two capacitor charge and discharges acts come the pull-up for assisting first switching element and drop-down, output end voltage, and then chopped pulse signal failing edge time are dragged down rapidly in downdraw process with this, eliminate motion blur phenomenon.
Description
Technical field
The present invention relates to packing technique fields, in particular to a kind of shift register cell and its driving method, also
It is related to a kind of gate driving circuit and display device.
Background technique
With the development of optical technology and semiconductor technology, people require increasingly the display effect of display device
It is high.
The resolution ratio of display device and working frequency are higher and higher at present, and the gate driving circuit of conventional display device is in height
Frequency is easy to appear display motion blur phenomenon under refreshing, and seriously affects display quality.The reason of causing such phenomenon is gate driving
The circuit pulse signal failing edge time (Falling Time) is too long, thus the failing edge time under high refreshing frequency operating condition
The too long grayscale value for leading to pixel write error.
It should be noted that the information in the invention of above-mentioned background technology part is only used for reinforcing the reason to background of the invention
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The purpose of the present invention is to provide a kind of shift register cell and its driving methods, further relate to a kind of gate driving
Circuit and display device solve display motion blur phenomenon existing in the prior art.
According to an aspect of the present invention, a kind of shift register cell is provided, comprising:
Input module is connect with input signal end, first node and first voltage signal end, for responding input letter
Number, first voltage signal is transmitted to the first node；
Reseting module is connect, for ringing with reset signal end, first node, second node and second voltage signal end
Reset signal is answered, second voltage signal is transmitted to the first node and second node；
First switching element is connect, for responding described first with output end, first node and the first clock signal terminal
The voltage signal of node, by the first clock signal transmission to output end；
Pull-down module is connect with second clock signal end, first node, second node and second voltage signal end, is used
In response second clock signal, the second voltage signal is transmitted to the first node and second node；
Pull-down module is assisted, is connect with tertiary voltage signal end, second node, it, will for responding tertiary voltage signal
The tertiary voltage signal is transmitted to the second node；
First capacitor is connected between the first node and second node；
Second capacitor is connected between the second node and the output end.
In a kind of illustrative embodiments of the invention, the input module includes: second switch element, control terminal
Input signal end is connected, first end connects first voltage signal end, and second end connects the first node.
In a kind of illustrative embodiments of the invention, the reseting module includes: third switch element, control terminal
Reset signal end is connected, first end connects second voltage signal end, and second end connects the first node；With the 4th switch member
Part, control terminal connect reset signal end, and first end connects the second voltage signal end, and second end connects second section
Point.
In a kind of illustrative embodiments of the invention, the pull-down module includes: the 5th switch element, control terminal
Second clock signal end is connected, first end connects the second voltage signal end, and second end connects the first node；With the 6th
Switch element, control terminal connect second clock signal end, and first end connects the second voltage signal end, and second end connects institute
State second node.
In a kind of illustrative embodiments of the invention, the auxiliary pull-down module includes: the 7th switch element, control
End processed connects tertiary voltage signal end, and first end connects the tertiary voltage signal end, and second end connects the second node.
In a kind of illustrative embodiments of the invention, the switch element is thin film transistor (TFT).
In a kind of illustrative embodiments of the invention, the first switching element breadth length ratio is greater than other switch members
Part.
According to another aspect of the present invention, a kind of gate driving circuit, including multiple cascade shift LDs are also provided
Device unit；
Wherein, first input signal in m grades of shift register cells is in m-1 grades of shift register cells
Output signal, the third input signal in the m grades of shift register cells is m+1 grades of shift register cells
In output signal, the output signal in the m grades of shift register cells is defeated in m+1 grades of shift register cells
Enter signal；1 < m < N, N are natural number.
In a kind of illustrative embodiments of the invention, described 2nd grade to the m-1 grades of shift register cells
In, shift register cell described in any level further include: cascade terminal connects shift register cell described in adjacent two-stage, uses
In using the voltage signal at the cascade terminal as the first input signal of shift register cell described in next stage；It is opened with the 8th
Element is closed, for responding the voltage signal of the first node, by first clock signal transmission to the tandem node.
In a kind of illustrative embodiments of the invention, the 8th switch element is thin film transistor (TFT).
According to a further aspect of the invention, a kind of display device is also provided, including grid described in any of the above embodiments drives
Dynamic circuit.
According to a further aspect of the invention, a kind of driving method of shift register cell is also provided, for drive with
Upper described in any item shift register cells；The driving method includes:
First period controlled the reseting module by the reset signal and second voltage signal is transmitted to first node
And second node；
Second period controlled the input module by the input signal and first voltage signal is transmitted to described first
Node is simultaneously stored in the first capacitor；
The third period controls the first switching element by the voltage signal of the first node and is connected, by described the
One clock signal is transmitted to the output end and is stored in second capacitor；
4th period, by the control of the tertiary voltage signal auxiliary pull-down module by the tertiary voltage signal
It is transmitted to the second node and is stored in the first capacitor；Meanwhile institute is controlled by the voltage signal of the first node
First switching element conducting is stated, by first clock signal transmission to the output end；Wherein, first clock signal exists
Third period and the 4th period opposite in phase；
5th period was transmitted the second voltage signal by the control pull-down module of the second voltage signal
To the first node and second node.
The first switching element of shift register cell of the present invention is both used to pull up and is also used for pulling down, and is filled using two capacitors
Coupling when electric discharge acts come the pull-up for assisting first switching element and drop-down.Make first node under by coupling
The drawing stage maintains the conducting to first switching element to act on, and drags down output end voltage rapidly with this, and then under chopped pulse signal
Drop is along the time, the problem of so as to improve the pixel gray level value write error as caused by pulse signal failing edge overlong time, disappears
Motion blur phenomenon is shown except thus caused.The number of elements that the structure uses is less, and circuit structure is simple, can simplify preparation
Technique reduces cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
It can the limitation present invention.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.It should be evident that the accompanying drawings in the following description is only the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is shift register cell electrical block diagram of the present invention；
Fig. 2 is shift register cell circuit simulation figure of the present invention；
Fig. 3 is gate driving circuit cascade graphs of the present invention；
Fig. 4 is gate driving circuit analogous diagram of the present invention；
Structural schematic diagram when Fig. 5 is shift register cell circuits cascading of the present invention.
In figure, 101, input module；102, reseting module；103, first switching element；104, pull-down module；105, it assists
Pull-down module；106, the 8th switch element.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical attached drawing in figure
Label indicates same or similar structure, thus the detailed description that will omit them.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note indicates same or similar part, thus will omit repetition thereof.Some block diagrams shown in the drawings are function
Energy entity, not necessarily must be corresponding with physically or logically independent entity.These function can be realized using software form
Energy entity, or these functional entitys are realized in one or more hardware modules or integrated circuit, or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
A kind of shift register cell is provided in embodiment of the present invention, as shown in Figure 1, may include:
Input module 101 is connect with input signal end, first node and first voltage signal end, for responding input
First voltage signal is transmitted to first node by signal；
Reseting module 102 connect with reset signal end, first node, second node and second voltage signal end, is used for
Reset signal is responded, second voltage signal is transmitted to first node and second node；
First switching element 103 is connect with output end, first node and the first clock signal terminal, for responding first
The voltage signal of node, by the first clock signal transmission to output end；
Pull-down module 104 is connect with second clock signal end, first node, second node and second voltage signal end,
For responding second clock signal, second voltage signal is transmitted to first node and second node；
Pull-down module 105 is assisted, is connect with tertiary voltage signal end, second node, for responding tertiary voltage signal, with
Tertiary voltage signal is transmitted to second node；
First capacitor is connected between first node and second node；
Second capacitor, is connected between second node and output end.
Shift register cell provided by embodiment of the present invention, first switching element are both used to pull up and be also used for down
It draws, coupling when using two capacitor charge and discharges acts come the pull-up for assisting first switching element and drop-down.In pull-up rank
Section, input module improves first node voltage and charges to first capacitor, when first switch module makees upper trombone slide, in the first electricity
Holding under the coupling with the second capacitor, first node voltage is persistently lifted, Continuity signal can be provided to first switch module,
And keep first switch module fully under capacitive coupling effect.In the drop-down stage, pull-down module drags down output end voltage, together
When auxiliary pull-down module persistently to first capacitor charge, by coupling make first node maintenance first switching element is led
Logical effect, drags down output end voltage rapidly with this.
Coupling when embodiment of the present invention is using two capacitor charge and discharges assists the pull-up of first switching element
It is acted with drop-down, output end voltage, and then chopped pulse signal failing edge time is dragged down rapidly in downdraw process with this, thus
It is the problem of improving the pixel gray level value write error as caused by pulse signal failing edge overlong time, aobvious caused by eliminating thus
Show motion blur phenomenon.The number of elements that the structure uses is less, and circuit structure is simple, can simplify preparation process, reduce cost.
The shift register cell of embodiment of the present invention is described in detail below:
In this illustrative embodiments, with reference to Fig. 1, first node is Q node, and second node is N node.Input module
It may include second switch element M2, the control terminal of second switch element M2 connects input signal end, the first electricity of first end connection
Signal end VGH is pressed, second end connects Q node, and second switch element M2 can be used for responding the Continuity signal at input signal end to incite somebody to action
First voltage signal is transferred to Q node.When the shift register cell is located at first in multiple cascaded shift registers units
It is a or the last one when, input signal can be trigger signal STU, when the shift register cell is located at other positions,
Its input signal can be the output signal of upper level shift register cell.
In this illustrative embodiments, reseting module may include third switch element M3 and the 4th switch element M4.
The control terminal of third switch element M3 connects reset signal end T_RST, and first end connects second voltage signal end VGL, second end
Q node is connected, third switch element M3 can be used for being connected in response to reset signal second voltage signal is transferred to Q node.
The control terminal of 4th switch element M4 also connects reset signal end T_RST, and first end connects second voltage signal end VGL, and second
End connection N node, the 4th switch element M4 can be used for being connected in response to reset signal second voltage signal is transferred to N section
Point.
In this illustrative embodiments, pull-down module includes the 5th switch element M5 and the 6th switch element M6.5th
The control terminal of switch element M5 connects second clock signal end CLK3, and first end connects second voltage signal end VGL, and second end connects
Q node is connect, the 5th switch element M5 is for being connected in response to second clock signal second voltage signal is transmitted to Q node.
The control terminal of 6th switch element M6 also connects second clock signal end CLK3, and first end also connects second voltage signal end VGL,
Second end connects N node, and the 6th switch element M6 is for being connected in response to second clock signal to transmit second voltage signal
To N node.
In this illustrative embodiments, auxiliary pull-down module includes the 7th switch element M7, and control terminal connects third
Voltage signal end, first end also connect tertiary voltage signal end, and second end connects N node, and the 7th switch element M7 is for responding
Tertiary voltage signal and be connected, tertiary voltage signal is transmitted to N node.When the shift register cell is located at multiple cascades
When in shift register cell, tertiary voltage signal end can be the output end of next stage shift register cell.When the displacement
When register cell is located at the both ends in multiple cascaded shift registers units, tertiary voltage signal end can be other power supplys
End.
Based on above-mentioned circuit structure, all switch elements can be P-type TFT or be that N-type film is brilliant
Body pipe.For the transistor of different doping types, the significant level of coherent signal need to be only adjusted.Such as all switch elements
When being N-type TFT, significant level is high level, and when all switch elements are P-type TFT,
Significant level is low level.
Below by taking all switch elements are N-type transistor as an example, shift register cell and Fig. 2 as shown in connection with fig. 1
Shown in signal waveforms, the course of work of the shift register cell within a frame period is specifically described.Its
In, first voltage signal is high level, and second voltage signal is low level, and tertiary voltage signal is high level.
In the T0 stage, i.e., before each frame image starts, reset signal end T_RST is high level, at this time third switch element
M3, the 4th switch element M4 are opened, and first node and second node are set low second voltage signal VGL, make shift register
Unit returns to original state.
After frame scan starts, in the T1 stage, for input module as trigger module, this stage belongs to trigger signal STU (input
Signal) write phase, trigger signal STU is high level, this stage second switch element M2 is opened, and first voltage signal VGH writes
Enter to Q node, Q node voltage value is made to be lifted to first step, while N node is also lifted due to the coupling of first capacitor C1
It rises.
In the T2 stage, first switching element M1 does trombone slide use.The first clock signal clk 1 is high level at this time, due to
T1 stage Q node voltage has been lifted, and is written to output end OUT, the lift of output end OUT node voltage by first switching element M1
It rises.At this time by the coupling of first capacitor C1 and the second capacitor C2, Q node voltage continues to be lifted to second step, one from
And first switching element M1 is fully opened, the first clock signal clk 1 is completely written to output end OUT node.N node voltage by
It is also lifted again in the coupling of the second capacitor C2.
In the T3 stage, first switching element M1 makees lower trombone slide and uses.Since the first clock signal clk 1 is low level at this time,
Q node is high level, so output end OUT node voltage is pulled down by first switching element M1.If without the 7th switch member
Part M7 work, output end OUT node voltage can pass through the coupling of first capacitor C1 and the second capacitor C2 in downdraw process
Q node voltage is set also to pull down to low-voltage, which increases the pulse signal failing edge times, cause display abnormal.Therefore, originally
Invention opens the 7th switch element M7 in this stage, and the output voltage signal (tertiary voltage signal) that next stage is written arrives N node,
So that N node is kept high voltage with this, then so that Q node is maintained at third plateau voltage by first capacitor C1 coupling.This electricity
Pressure can be such that first switching element M1 fully opens, and drag down OUT node voltage rapidly by the first clock signal clk 1.
In the T4 stage, this stage second clock signal CLK3 is high level, opens the 5th switch element M5, the 6th switch member
Part M6 drags down Q node, N node to low-voltage VGL respectively.
Based on above-mentioned working sequence, which completes shift LD function, provides stable output
Voltage, and output end voltage is pulled down rapidly, the chopped pulse signal failing edge time, and then eliminate motion blur phenomenon.
In this illustrative embodiments, the breadth length ratio of first switching element M1 is greater than other switch elements, is pulling down
It can be reduced to a certain extent the failing edge time when pipe, further eliminate motion blur phenomenon.
Present embodiment additionally provides a kind of driving method of shift register cell, applied to above-mentioned shift register
Below unit.The driving method includes:
First period controlled reseting module by reset signal and second voltage signal is transmitted to first node and the second section
Point.
First voltage signal is transmitted to first node by input signal control input module and is stored in by the second period
First capacitor.
The third period controls first switching element conducting by the voltage signal of first node, the first clock signal is passed
It transports to output end and is stored in the second capacitor.
4th period assisted pull-down module that tertiary voltage signal is transmitted to the second section by the control of tertiary voltage signal
It puts and is stored in first capacitor；Meanwhile first switching element conducting is controlled by the voltage signal of first node, by the first clock
Signal is transmitted to output end；Wherein, the first clock signal is in third period and the 4th period opposite in phase.
5th period, by the control pull-down module of second voltage signal by second voltage signal be transmitted to first node and
Second node.
A kind of specific implementation of the driving method can correspond to the course of work of above-mentioned shift register cell, herein no longer
It repeats.
Embodiment of the present invention also provides a kind of gate driving circuit, as shown in figure 3, including multiple cascade above-mentioned implementations
The shift register cell of mode；Wherein, the first input signal in m grades of shift register cells is that m-1 grades of displacements are posted
Output signal in storage unit, the third input signal in m grades of shift register cells are m+1 grades of shift register lists
Output signal in member, the output signal in m grades of shift register cells are the input in m+1 grades of shift register cells
Signal；1 < m < N, N are natural number.
In figure, when CLK1 and CLK2 in each shift register cell indicate first in the shift register cell
Clock signal CLK1 receiving port and second clock signal CLK3 receiving port, four clock signals in left side refer to for all
The different clocks signal of shift register offer low and high level.According to connection relationship in figure, four clock signals can be used for more
A shift register cell provides different clock signals, meets the requirement of each shift register cell working sequence.According to Fig. 4
Shown in signal waveforms, the control to shift register cells different in the gate driving circuit can be realized.
In this illustrative embodiments, as shown in figure 5, the 2nd grade of gate driving circuit to m-1 grades of shift registers
In unit, any level shift register cell further includes cascade terminal CR, connects adjacent two-stage shift register cell, and being used for will
First input signal of the voltage signal as next stage shift register cell at the cascade terminal.Output end OUT can as a result,
Separately as the output port of grid line, terminal CR is cascaded as the cascade port of the superior and the subordinate, output and next stage are inputted and separated,
Row point ratio can be reduced.It opens in adaptable every level-one shift register cell including the 8th switch element 106, for ringing therewith
The voltage signal for answering first node, by the first clock signal transmission to tandem node.
8th switch element may be P-type TFT or be N-type TFT, with other switch element classes
Type matching.Such as in this illustrative embodiment, the 8th switch element M8 is N-type TFT, and control terminal connects Q
The voltage signal of node, first end connect the first clock signal terminal CKL1, and second end connects tandem node CR.8th switch element
The effect of M8 is identical as first switching element M1, and the signal condition at grade interface CR is identical as output end OUT.Grade interface CR
The input terminal for connecting next stage shift register cell, can be used for controlling the turn-on and turn-off of second switch element M2.
The present invention also provides a kind of display devices to eliminate display including the gate driving circuit in embodiment of above
The phenomenon that smear, image quality improve.The display device can be liquid crystal display, OLED (Organic Light
Emitting Diode, Organic Light Emitting Diode) display, PLED (Polymer Light-Emitting Diode, macromolecule
Light emitting diode) a variety of displays such as display, PDP (Plasma Display Panel, plasma are shown) display, here
Applicable for display device is not particularly limited.The display device can be used for mobile phone, tablet computer, television set, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.Display device in embodiment of the present invention
It can be high frequency display unit, be also possible to low frequency display device.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification
The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show
The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will
As the component in "lower".When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures
On, or refer to that certain structure is " direct " and be arranged in other structures, or refer to that certain structure is arranged by the way that another structure is " indirect " in other knots
On structure.
Term "one", " one ", "the", " described " and "at least one" be to indicate that there are one or more elements/groups
At part/etc.；Term " comprising " and " having " is to indicate the open meaning being included and refer in addition to listing
Element/component part/also may be present except waiting other element/component part/etc..
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to of the invention its
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the invention, these modifications, purposes or
Person's adaptive change follows general principle of the invention and including the undocumented common knowledge in the art of the present invention
Or conventional techniques.The description and examples are only to be considered as illustrative, and true scope and spirit of the invention are by appended
Claim is pointed out.
Claims (12)
1. a kind of shift register cell characterized by comprising
Input module is connect with input signal end, first node and first voltage signal end, for responding input signal, with
First voltage signal is transmitted to the first node；
Reseting module is connect with reset signal end, first node, second node and second voltage signal end, multiple for responding
Position signal, is transmitted to the first node and second node for second voltage signal；
First switching element is connect, for responding the first node with output end, first node and the first clock signal terminal
Voltage signal, by the first clock signal transmission to output end；
Pull-down module is connect, for ringing with second clock signal end, first node, second node and second voltage signal end
Second clock signal is answered, the second voltage signal is transmitted to the first node and second node；
Pull-down module is assisted, is connect with tertiary voltage signal end, second node, it, will be described for responding tertiary voltage signal
Tertiary voltage signal is transmitted to the second node；
First capacitor is connected between the first node and second node；
Second capacitor is connected between the second node and the output end.
2. shift register cell according to claim 1, which is characterized in that the input module includes:
Second switch element, control terminal connect input signal end, and first end connects first voltage signal end, and second end connects institute
State first node.
3. shift register cell according to claim 1, which is characterized in that the reseting module includes:
Third switch element, control terminal connect reset signal end, and first end connects second voltage signal end, and second end connects institute
State first node；
4th switch element, control terminal connect reset signal end, and first end connects the second voltage signal end, and second end connects
Connect the second node.
4. shift register cell according to claim 1, which is characterized in that the pull-down module includes:
5th switch element, control terminal connection second clock signal end, the first end connection second voltage signal end, second
End connects the first node；
6th switch element, control terminal connection second clock signal end, the first end connection second voltage signal end, second
End connects the second node.
5. shift register cell according to claim 1, which is characterized in that the auxiliary pull-down module includes:
7th switch element, control terminal connection tertiary voltage signal end, the first end connection tertiary voltage signal end, second
End connects the second node.
6. shift register cell according to any one of claims 1-5, which is characterized in that the switch element is
Thin film transistor (TFT).
7. shift register cell according to claim 6, which is characterized in that the first switching element breadth length ratio is greater than
Other switch elements.
8. a kind of gate driving circuit, which is characterized in that including multiple cascade such as shifting of any of claims 1-7
Bit register unit；
Wherein, first input signal in m grades of shift register cells is defeated in m-1 grades of shift register cells
Signal out, the third input signal in the m grades of shift register cells are in m+1 grades of shift register cells
Output signal, the output signal in the m grades of shift register cells are that the input in m+1 grade shift register cells is believed
Number；1 < m < N, N are natural number.
9. gate driving circuit according to claim 8, which is characterized in that described 2nd grade to the m-1 grades of displacements is posted
In storage unit, shift register cell described in any level further include:
Cascade terminal, connect shift register cell described in adjacent two-stage, for using the voltage signal at the cascade terminal as
First input signal of shift register cell described in next stage；
8th switch element, for responding the voltage signal of the first node, by first clock signal transmission to institute
State tandem node.
10. gate driving circuit according to claim 9, which is characterized in that the 8th switch element is film crystal
Pipe.
11. a kind of display device, which is characterized in that including gate driving circuit described in any one of claim 8-10.
12. a kind of driving method of shift register cell, for driving shift LD of any of claims 1-7
Device unit；It is characterized in that, the driving method includes:
First period controlled the reseting module by the reset signal and second voltage signal is transmitted to first node and the
Two nodes；
Second period controlled the input module by the input signal and first voltage signal is transmitted to the first node
And it is stored in the first capacitor；
The third period controls the first switching element by the voltage signal of the first node and is connected, when by described first
Clock signal is transmitted to the output end and is stored in second capacitor；
4th period was transmitted the tertiary voltage signal by the control of the tertiary voltage signal auxiliary pull-down module
To the second node and it is stored in the first capacitor；Meanwhile described the is controlled by the voltage signal of the first node
One switching elements conductive, by first clock signal transmission to the output end；Wherein, first clock signal is in third
Period and the 4th period opposite in phase；
The second voltage signal is transmitted to institute by the control pull-down module of the second voltage signal by the 5th period
State first node and second node.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109859669A (en) * | 2019-03-20 | 2019-06-07 | 北京大学深圳研究生院 | A kind of high speed drive element of the grid and circuit |
| CN113314076A (en) * | 2021-05-31 | 2021-08-27 | 合肥京东方卓印科技有限公司 | Shift register unit, grid driving circuit and control method thereof |
| CN114241992A (en) * | 2021-12-30 | 2022-03-25 | 合肥京东方卓印科技有限公司 | Shift register, gate drive circuit and display device |
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| WO2024045452A1 (en) * | 2022-08-29 | 2024-03-07 | 惠科股份有限公司 | Gate drive circuit and display apparatus |
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| CN113314076A (en) * | 2021-05-31 | 2021-08-27 | 合肥京东方卓印科技有限公司 | Shift register unit, grid driving circuit and control method thereof |
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| WO2024045452A1 (en) * | 2022-08-29 | 2024-03-07 | 惠科股份有限公司 | Gate drive circuit and display apparatus |
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