CN102708777B - Shift register unit and gate drive device - Google Patents
Shift register unit and gate drive device Download PDFInfo
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- CN102708777B CN102708777B CN201110381861.5A CN201110381861A CN102708777B CN 102708777 B CN102708777 B CN 102708777B CN 201110381861 A CN201110381861 A CN 201110381861A CN 102708777 B CN102708777 B CN 102708777B
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Abstract
The invention provides a shift register unit and a gate drive device. The shift register unit comprises a latch and a control circuit, wherein the control circuit comprises a first thin film transistor, a second thin film transistor and a third thin film transistor; the gate of the first thin film transistor is connected with a clock signal input end; the source of the first thin film transistor is connected with a signal input end; the drain of the first thin film transistor is connected with the input end of the latch; the gate of the second thin film transistor is connected with the clock signal input end; the source of the second thin film transistor is connected with a first signal output end; the gate of the third thin film transistor is connected with the signal input end; the source of the third thin film transistor is connected with a high-level signal input end; the drain of the third thin film transistor is connected with the drain of the second thin film transistor; the latch comprises a first phase inverter and a second phase inverter which are connected with each other end to end; the input end of the latch is connected with a second signal output end; the output end of the latch is connected with the first signal output end; and the levels of output signals of the first signal output end and the second signal output end are opposite. According to the shift register unit, the circuit is simple in structure, a small number of signal wires are arranged, the power consumption is low, and the area of a layout is small.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of shift register cell and gate drive apparatus.
Background technology
The gate drive apparatus of display is used for providing drive singal for grid line, gate drive apparatus comprises the shift register cell of multiple cascade, be illustrated in figure 1 a structural representation of shift register cell of the prior art, this shift register cell comprises: 2 latch 101 and 4 transmission gates 102, one of them latch 101 is for programming, another latch 101 is for latch output signal, and transmission gate 102 is programmed or latch output signal for controlling latch 101.As can be seen from Figure 1, each latch 101 forms (in figure, the Reset signal of Reset (reset) the signal input part input of NAND gate is high level, and thus this NAND gate is also equivalent to a phase inverter) by two phase inverters.In figure, CLK is clock signal, and D node is the input node of latch, and Q node is the reverse output node of latch.
As can be seen from Figure 1, existing shift register cell needs two latch, and its transistor adopted is more, thus makes shift register cell can produce larger power consumption.
Summary of the invention
In view of this, the invention provides a kind of shift register cell and gate drive apparatus, circuit structure is simple, signal routing is few, make the lower power consumption of whole shift register cell, the gate drive apparatus area occupied of its cascade structure formation is simultaneously few, taking the display area of display floater can be reduced further, thus realize the high-res of display device and narrow frame.
For solving the problem, the invention provides a kind of shift register cell, comprising:
Latch and control circuit;
Described control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with signal input part, and drain electrode is connected with the input of described latch;
Second thin film transistor (TFT), its grid is connected with described clock signal input terminal, and source electrode is connected with the first signal output part;
3rd thin film transistor (TFT), its grid is connected with described signal input part, and source electrode is connected with described high level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT);
Described latch comprises: end to end first phase inverter and the second phase inverter, and the input of described latch is connected with the drain electrode of described the first film transistor and secondary signal output, and output is connected with described first signal output part;
Wherein, described first signal output part is contrary with the level of the output signal of described secondary signal output.
Optionally, described shift register cell also comprises:
4th thin film transistor (TFT), its grid is connected with reset signal input, and source electrode is connected with low level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT).
Optionally, described first phase inverter comprises:
5th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the input of described latch;
6th thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
7th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the output of described latch;
8th thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
Optionally, described first phase inverter comprises:
9th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
Tenth thin film transistor (TFT), its grid is connected with the source electrode of described 9th thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the input of described latch;
11 thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
12 thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
13 thin film transistor (TFT), its grid is connected with the source electrode of described 12 thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the output of described latch;
14 thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
The present invention also provides a kind of gate drive apparatus, comprising: be deposited on the multiple above-mentioned shift register cell on array base palte, wherein,
Except first shift register cell, the signal input part of all the other shift register cells is connected with the secondary signal output of an adjacent upper shift register cell;
The signal input part of first shift register cell is connected with frame start signal input;
Except last shift register cell, the secondary signal output of all the other shift register cells is connected with the signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with the first clock cable, and the clock signal input terminal of even number shift register cell is connected with second clock holding wire;
The high level signal input of each shift register cell is connected with high level signal line, and low level signal input is connected with low level signal line;
The level of the clock signal that described first clock cable and described second clock holding wire export is contrary.
Optionally, except last shift register cell, the reset signal input of all the other shift register cells is connected with the first signal output part of adjacent next shift register cell; The reset signal input of last shift register cell is connected with described frame start signal input.
The present invention also provides a kind of shift register cell, comprising:
Latch and control circuit;
Described control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with the first signal input part, and drain electrode is connected with the input of described latch;
Second thin film transistor (TFT), its grid is connected with described clock signal input terminal, and source electrode is connected with described first signal output part;
3rd thin film transistor (TFT), its grid is connected with secondary signal input, and drain electrode is connected with described high level signal input, and source electrode is connected with the drain electrode of described second thin film transistor (TFT);
Described latch comprises: end to end first phase inverter and the second phase inverter, and the input of described latch is connected with the drain electrode of described the first film transistor and secondary signal output, and output is connected with described first signal output part;
Wherein, described first signal input part is contrary with the level of the input signal of described secondary signal input, and described first signal output part is contrary with the level of the output signal of described secondary signal output.
Optionally, described shift register cell also comprises:
4th thin film transistor (TFT), its grid is connected with reset signal input, and source electrode is connected with low level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT).
Optionally, described first phase inverter comprises:
5th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the input of described latch;
6th thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
7th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the output of described latch;
8th thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
Optionally, described first phase inverter comprises:
9th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
Tenth thin film transistor (TFT), its grid is connected with the source electrode of described 9th thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the input of described latch;
11 thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
12 thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
13 thin film transistor (TFT), its grid is connected with the source electrode of described 12 thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the output of described latch;
14 thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
The present invention is a kind of gate drive apparatus also, is deposited on the multiple above-mentioned shift register cell on array base palte, wherein,
Except first shift register cell, first signal input part of all the other shift register cells is connected with the secondary signal output of an adjacent upper shift register cell, and secondary signal input is connected with the first signal output part of an adjacent upper shift register cell;
First signal input part of first shift register cell is connected with the first frame start signal input, and secondary signal input is connected with the second frame start signal input;
Except last shift register cell, first signal output part of all the other shift register cells is connected with the secondary signal input of adjacent next shift register cell, and secondary signal output is connected with the first signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with the first clock cable, and the clock signal input terminal of even number shift register cell is connected with second clock holding wire;
The high level signal input of each shift register cell is connected with high level signal line, and low level signal input is connected with low level signal line;
The level of the clock signal that described first clock cable and described second clock holding wire export is contrary, and the level of the input signal of described first frame start signal input and described second frame start signal input is contrary.
Optionally, except last shift register cell, the reset signal input of all the other shift register cells is connected with the first signal output part of adjacent next shift register cell; The reset signal input of last shift register cell is connected with described first frame start signal input.
The present invention has following beneficial effect:
A latch is only adopted in shift register cell, circuit structure is simple, signal routing is few, make the lower power consumption of whole shift register cell, the gate drive apparatus area occupied of its cascade structure formation is simultaneously few, taking the display area of display floater can be reduced further, thus realize the high-res of display device and narrow frame.
Accompanying drawing explanation
Fig. 1 is a structural representation of shift register cell of the prior art;
Fig. 2 is the structural representation of the shift register cell of the embodiment of the present invention one;
Fig. 3 is the structural representation of the gate drive apparatus of the embodiment of the present invention one;
Fig. 4 is the working timing figure of the shift register cell of the embodiment of the present invention;
Fig. 5 is the structural representation of the shift register cell of the embodiment of the present invention two;
Fig. 6 is the structural representation of the gate drive apparatus of the embodiment of the present invention two;
Fig. 7 is the structural representation of the shift register cell of the embodiment of the present invention three;
Fig. 8 is the structural representation of the gate drive apparatus of the embodiment of the present invention three;
Fig. 9 is the structural representation of the shift register cell of the embodiment of the present invention four;
Figure 10 is the structural representation of the gate drive apparatus of the embodiment of the present invention four;
Figure 11 is a structural representation of the latch of the embodiment of the present invention;
Figure 12 is another structural representation of the latch of the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
Be illustrated in figure 2 the structural representation of the shift register cell of the embodiment of the present invention one, this shift register cell comprises: latch 201 and control circuit.For convenience of description, in following examples, all using the input of the P node in figure as latch 201, Q node is as the output of latch.
Wherein, control circuit is programmed or latch output signal for controlling latch 201, comprise: the first film transistor T1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, in the present embodiment, the first film transistor T1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are nmos pass transistor.
The grid of the first film transistor T1 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal input part Input1, and drain electrode is connected with the input P of latch 201.
Input signal due to the first signal input part Input1 may be high level, also may be low level, and thus the source electrode of the first film transistor T1 can exchange with drain electrode.When the input signal of the first signal input part Input1 is high level, what be connected with the first signal input part Input1 is the drain electrode of the first film transistor T1, and what be connected with the input P of latch 201 is the source electrode of the first film transistor T1.When the input signal of the first signal input part Input1 is low level, what be connected with the first signal input part Input1 is the source electrode of the first film transistor T1, and what be connected with the input P of latch 201 is the drain electrode of the first film transistor T1.
The grid of the second thin film transistor (TFT) T2 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal output part Output_Q, and drain electrode is connected with the source electrode of the 3rd thin film transistor (TFT) T3.
The grid of the 3rd thin film transistor (TFT) T3 is connected with secondary signal input Input2, and drain electrode is connected with high level signal input VDD, and source electrode is connected with the drain electrode of the second thin film transistor (TFT) T2.
Latch 201 comprises: end to end first phase inverter 2011 and the second phase inverter 2012, the input P of latch is connected with secondary signal output Output_QB and the first film transistor T1, and output Q is connected with the first signal output part Output_Q.
In the present embodiment, the first signal input part Input1 is contrary with the level of the input signal of secondary signal input Input2, and the first signal output part Output_Q is contrary with the level of the output signal of secondary signal output Output_QB.
In above-described embodiment, be described for nmos pass transistor for the first film transistor T1 and the second thin film transistor (TFT) T2, certain the first film transistor T1 and the second thin film transistor (TFT) T2 can be also PMOS transistor simultaneously simultaneously.
Be illustrated in figure 3 the structural representation of the gate drive apparatus of the embodiment of the present invention one, this gate drive apparatus comprises: the shift register cell being deposited on the multiple cascades on array base palte, the structure of shift register cell please refer to Fig. 2.In Fig. 3, Output_Q (n) identifies the output signal of n-th grade of shift register cell.
Below the annexation between each parts of the gate drive apparatus in Fig. 3 is described in detail:
Except first shift register cell, first signal input part Input1 of all the other shift register cells is connected with the secondary signal output Output_QB of an adjacent upper shift register cell, and secondary signal input Input2 is connected with the first signal output part Output_Q of an adjacent upper shift register cell;
First signal input part Input1 of first shift register cell is connected with the first frame start signal input STV, and secondary signal input Input2 is connected with the second frame start signal input STV_B;
Except last shift register cell, first signal output part Output_Q of all the other shift register cells is connected with the secondary signal input Input2 of adjacent next shift register cell, and secondary signal output Output_QB is connected with the first signal input part Input1 of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with the first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock holding wire 302;
The high level signal input VDD of each shift register cell is connected with high level signal line 303.
In the present embodiment, the level of the clock signal (CLK and CLKB) that the first clock cable 301 and second clock holding wire 302 export is contrary, and the level of the input signal (STV and STV_B) of the first frame start signal input 304 and the second frame start signal input 305 is contrary.
As can be seen from above-described embodiment, a latch is only adopted in shift register cell, circuit structure is simple, signal routing is few, make the lower power consumption of whole shift register cell, the gate drive apparatus area occupied of its cascade structure formation is simultaneously few, taking the display area of display floater can be reduced further, thus realize the high-res of display device and narrow frame.
Be illustrated in figure 4 the working timing figure of the shift register cell of the embodiment of the present invention, for the n-th shift register cell, the course of work of shift register cell in Fig. 3 be described.
The course of work of the shift register cell in Fig. 3 mainly comprised with the next stage:
1st stage: the output signal Output_Q (n-1) of upper level shift register cell (i.e. (n-1)th shift register cell) becomes high level from low level, namely the input signal Input2 of the n-th shift register cell is high level, now, CLK is low level, the first film transistor T1, the second thin film transistor (TFT) T2 turn off, and output Output_Q (n) of latch remains low level.
2nd stage: the output signal Output_Q (n-1) of upper level shift register cell is still high level, namely the input signal Input2 of the n-th shift register cell is high level, CLK becomes high level from low level, then the first film transistor T1, second thin film transistor (TFT) T2, 3rd thin film transistor (TFT) T3 conducting, input signal Input1 is low level, now, the input P of latch is pulled down to low level, Output_QB (n) is also low level, simultaneously, the output Q (i.e. Output_Q) of latch is pulled to high level, that is, latch is programmed to export high level.
3rd stage: the output signal Output_Q (n-1) of upper level shift register cell becomes low level, namely the input signal Input2 of the n-th shift register cell is low level, and CLK becomes low level from high level, the first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 all end, then the high level output of latch is latched and maintains, namely Output_Q (n) is maintained high level, and Output_QB (n) is maintained low level.
4th stage: the input signal Input2 of n-th grade of shift register cell becomes low level, 3rd thin film transistor (TFT) T3 ends, CLK becomes high level, the first film transistor T1 conducting, the reverse output signal Output_QB (n-1) of upper level shift register cell is high level simultaneously, namely the input signal Input1 of n-th grade of shift register cell is high level, then the input P of latch is pulled to high level, output Q (i.e. Output_Q (n)) is pulled down to low level, that is, latch is programmed to output low level.
5th stage: the reverse output signal Output_QB (n-1) of upper level shift register cell is always high level, namely the input signal of the n-th shift register cell be always low electric Input2 put down, Input1 is always high level, and the 3rd thin film transistor (TFT) T3 ends all the time; The first film transistor T1, second thin film transistor (TFT) T2 cycle conducting under CLK signal, wherein when the T1 conducting of the first film transistor, the input P of latch is pulled to high level by Input1, and output Q (i.e. Output_Q (n)) is low level; When the first film transistor T1 ends, the output Q (i.e. Output_Q (n)) of latch maintains low level.Namely this stage is output Q (i.e. Output_Q (n)) the output low level maintenance stage of latch.
After the 5th stage, Input2 signal is always low level, that is, 3rd thin film transistor (TFT) T3 is in closed condition always, and CLK can make the continuous switch of the second thin film transistor (TFT) T2, if be in high potential between the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, then can affect the output of latch.
In order to avoid the problems referred to above, be illustrated in figure 5 the structural representation of the shift register cell of the embodiment of the present invention two, on the basis of the shift register cell shown in Fig. 2, can also increase by one the 4th thin film transistor (TFT) T4 in control circuit, wherein, the grid of the 4th thin film transistor (TFT) T4 is connected with reset signal input Reset, and source electrode is connected with low level signal input VSS, and drain electrode is connected with the second thin film transistor (TFT) T2.
With the shift register cell in Fig. 2 unlike, in the present embodiment, the source electrode of the second thin film transistor (TFT) T2 and drain electrode can be exchanged.When the second thin film transistor (TFT) T2 and the equal conducting of the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 end, one end that second thin film transistor (TFT) T2 is connected with the first signal output part Output_Q is source electrode, the one end be connected with the 3rd thin film transistor (TFT) T3 is for drain, when the second thin film transistor (TFT) T2 and the equal conducting of the 4th thin film transistor (TFT) T4, the 3rd thin film transistor (TFT) T3 end, one end that second thin film transistor (TFT) T2 is connected with the first signal output part Output_Q is for drain, and the one end be connected with the 4th thin film transistor (TFT) T4 is source electrode.
Be illustrated in figure 6 the structural representation of the gate drive apparatus of the embodiment of the present invention two, this gate drive apparatus comprises: the shift register cell being deposited on the multiple cascades on array base palte, the structure of this shift register cell please refer to Fig. 5.
Below the annexation between each parts of the gate drive apparatus in Fig. 6 is described in detail:
Except first shift register cell, first signal input part Input1 of all the other shift register cells is connected with the secondary signal output Output_QB of an adjacent upper shift register cell, and secondary signal input Input2 is connected with the first signal output part Output_Q of an adjacent upper shift register cell;
First signal input part Input1 of first shift register cell is connected with the first frame start signal input STV, and secondary signal input Input2 is connected with the second frame start signal input STV_B;
Except last shift register cell, first signal output part Output_Q of all the other shift register cells is connected with the secondary signal input Input2 of adjacent next shift register cell, and secondary signal output Output_QB is connected with the first signal input part Input1 of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with the first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock holding wire 302;
The high level signal input VDD of each shift register cell is connected with high level signal line 303, and low level signal input VSS is connected with low level signal line 304;
Except last shift register cell, the reset signal input Reset of all the other shift register cells is connected with the first signal output part Output_Q of adjacent next shift register cell;
The reset signal input Reset of last shift register cell is connected with the first frame start signal input STV.
In the present embodiment, the level of the clock signal (CLK and CLKB) that the first clock cable 301 and second clock holding wire 302 export is contrary, and the level of the input signal (STV and STV_B) of the first frame start signal input 304 and the second frame start signal input 305 is contrary.
Be described in detail to the course of work of the shift register cell in Fig. 6 below, same, still for the n-th shift register cell, its work schedule as shown in Figure 4.
In Fig. 6, the course of work of shift register cell mainly comprised with the next stage:
1st stage: the output signal Output_Q (n-1) of upper level shift register cell (i.e. (n-1)th shift register cell) becomes high level from low level, namely the input signal Input2 of the n-th shift register cell is high level, now, CLK is low level, the first film transistor T1, the second thin film transistor (TFT) T2 turn off, and output Output_Q (n) of latch remains low level.
2nd stage: the output signal Output_Q (n-1) of upper level shift register cell is still high level, namely the input signal Input2 of the n-th shift register cell is high level, CLK becomes high level from low level, then the first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 conducting, Reset signal (i.e. the reverse output signal Output_QB (n+1) of next stage shift register cell) is low level, and the 4th thin film transistor (TFT) T4 ends; Input signal Input1 is low level, now, the input P of latch is pulled down to low level, Output_QB (n) is also low level, simultaneously, the output Q (i.e. Output_Q) of latch is pulled to high level, and that is, latch is programmed to export high level.
3rd stage: the output signal Output_Q (n-1) of upper level shift register cell becomes low level, namely the input signal Input2 of the n-th shift register cell is low level, and CLK becomes low level from high level, the first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 all end, then the high level output of latch is latched and maintains, namely Output_Q (n) is maintained high level, and Output_QB (n) is maintained low level.And now, under CLKB signal, Output_Q (n) and Output_QB (n) signal, next stage shift register cell entered for the 2nd stage, it exports Output_Q (n+1) and becomes high level, oppositely exports Output_QB (n+1) and becomes low level.
4th stage: the input signal Input2 of n-th grade of shift register cell becomes low level, 3rd thin film transistor (TFT) T3 ends, CLK becomes high level, the first film transistor T1 conducting, the output Output_Q (n+1) of next stage shift register cell is high level, then the 4th thin film transistor (TFT) T4 conducting, the reverse output signal Output_QB (n-1) of upper level shift register cell is high level simultaneously, namely the input signal Input1 of n-th grade of shift register cell is high level, then the input P of latch is pulled to high level, output Q (i.e. Output_Q (n)) is pulled down to low level, that is, latch is programmed to output low level.
5th stage: the reverse output signal Output_QB (n-1) of upper level shift register cell is always high level, namely the input signal Input2 of the n-th shift register cell is always low level, Input1 is always high level, and the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 end all the time; The first film transistor T1, second thin film transistor (TFT) T2 cycle conducting under CLK signal, wherein when the T1 conducting of the first film transistor, the input P of latch is pulled to high level by Input1, and output Q (i.e. Output_Q (n)) is low level; When the first film transistor T1 ends, the output Q (i.e. Output_Q (n)) of latch maintains low level.Namely this stage is output Q (i.e. Output_Q (n)) the output low level maintenance stage of latch.
In above-described embodiment, shift register cell has two signal input parts (the first signal input part Input1 and secondary signal input Input2), only can certainly adopt a signal input part.
Be illustrated in figure 7 the structural representation of the shift register cell of the embodiment of the present invention three, this shift register cell comprises: latch 201 and control circuit.
Wherein, control circuit is programmed or latch output signal for controlling latch 201, comprise: the first film transistor T1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, in the present embodiment, the first film transistor T1 and the second thin film transistor (TFT) T2 is nmos pass transistor simultaneously, and the 3rd thin film transistor (TFT) T3 is PMOS transistor.
The grid of the first film transistor T1 is connected with clock signal input terminal CLK, and source electrode is connected with signal input part Input, and drain electrode is connected with the input P of latch 201.
Input signal Input due to signal input part Input may be high level, also may be low level, and thus the source electrode of the first film transistor T1 can exchange with drain electrode.When Input signal is high level, what be connected with signal input part Input is the drain electrode of the first film transistor T1, and what be connected with the input P of latch 201 is the source electrode of the first film transistor T1; When Input signal is low level, what be connected with signal input part Input is the source electrode of the first film transistor T1, and what be connected with the input P of latch 201 is the drain electrode of the first film transistor T1.
The grid of the second thin film transistor (TFT) T2 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal output part Output_Q, and drain electrode is connected with the drain electrode of the 3rd thin film transistor (TFT) T3.
The grid of the 3rd thin film transistor (TFT) T3 is connected with signal input part Input, and source electrode is connected with high level signal input VDD, and drain electrode is connected with the drain electrode of the second thin film transistor (TFT) T2;
Latch 201 comprises: end to end first phase inverter 2011 and the second phase inverter 2012, the input P of latch is connected with secondary signal output Output_QB and the first film transistor T1, and output Q is connected with the first signal output part Output_Q.
In the present embodiment, the first signal output part Output_Q is contrary with the level of the output signal (Output_Q and Output_QB) of secondary signal output Output_QB.
In above-described embodiment, be described for nmos pass transistor for the first film transistor T1 and the second thin film transistor (TFT) T2, certain the first film transistor T1 and the second thin film transistor (TFT) T2 can be also PMOS transistor simultaneously simultaneously.
Be illustrated in figure 8 the structural representation of the gate drive apparatus of the embodiment of the present invention three, this gate drive apparatus comprises: the shift register cell being deposited on the multiple cascades on array base palte, the structure of this shift register cell please refer to Fig. 7.
Below the annexation between each parts of the gate drive apparatus in Fig. 8 is described in detail:
Except first shift register cell, the signal input part Input of all the other shift register cells is connected with the secondary signal output Output_QB of an adjacent upper shift register cell;
The signal input part Input of first shift register cell is connected with frame start signal input STV;
Except last shift register cell, the secondary signal output Output_QB of all the other shift register cells is connected with the signal input part Input of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with the first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock holding wire 302;
The high level signal input VDD of each shift register cell is connected with high level signal line 303.
In the present embodiment, the level of the clock signal (CLK and CLKB) that the first clock cable 301 and second clock holding wire 302 export is contrary.
Be illustrated in figure 9 the structural representation of the shift register cell of the embodiment of the present invention four, on the basis of the embodiment shown in Fig. 7, in control circuit, increase by one the 4th thin film transistor (TFT) T4, the grid of the 4th thin film transistor (TFT) T4 is connected with reset signal input Reset, source electrode is connected with low level signal input VSS, and drain electrode is connected with the drain electrode of the second thin film transistor (TFT) T2.
Shift register cell in Fig. 7 and Fig. 9, eliminates the sequential of an input signal, and the 3rd thin film transistor (TFT) T3 adopts PMOS transmission VDD also not have loss simultaneously.
Be the structural representation of the gate drive apparatus of the embodiment of the present invention four as shown in Figure 10, this gate drive apparatus comprises: the shift register cell being deposited on the multiple cascades on array base palte, the structure of this shift register cell please refer to Fig. 9.
Below the annexation between each parts of the gate drive apparatus in Figure 10 is described in detail:
Except first shift register cell, the signal input part Input of all the other shift register cells is connected with the secondary signal output Output_QB of an adjacent upper shift register cell;
The signal input part Input of first shift register cell is connected with frame start signal input STV;
Except last shift register cell, the secondary signal output Output_QB of all the other shift register cells is connected with the signal input part Input of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with the first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock holding wire 302;
The high level signal input VDD of each shift register cell is connected with high level signal line 303, and low level signal input VSS is connected with low level signal line 304;
Except last shift register cell, the reset signal input Reset of all the other shift register cells is connected with the first signal output part Output_Q of adjacent next shift register cell;
The reset signal input Reset of last shift register cell is connected with frame start signal input STV.
In the present embodiment, the level of the clock signal (CLK and CLKB) that the first clock cable 301 and second clock holding wire 302 export is contrary.
The first phase inverter in latch in above-described embodiment and the second phase inverter can be various structures, and citing is below described.
Be a structural representation of latch of the present invention as shown in figure 11, wherein, first phase inverter 2011 and the second phase inverter 2012 are made up of two thin film transistor (TFT)s respectively, first phase inverter 2011 comprises the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6, and the second phase inverter 2012 comprises the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8.In the present embodiment, the 5th thin film transistor (TFT) T5 is NMOS tube to the 8th thin film transistor (TFT) T8.
The grid of the 5th thin film transistor (TFT) T5 is all connected with high level signal input VDD with drain electrode, and source electrode is connected with the input P of latch;
The grid of the 6th thin film transistor (TFT) T6 is connected with the output Q of latch, and source electrode is connected with low level signal input VSS, and drain electrode is connected with the input P of latch;
The grid of the 7th thin film transistor (TFT) T7 is all connected with high level signal input VDD with drain electrode, and source electrode is connected with the output Q of latch;
The grid of the 8th thin film transistor (TFT) T8 is connected with the input P of latch, and source electrode is connected with low level signal input VSS, and drain electrode is connected with the output Q of latch.
Be another structural representation of latch of the present invention as shown in figure 12, wherein, first phase inverter 2011 and the second phase inverter 2012 are made up of three thin film transistor (TFT)s respectively, first phase inverter 2011 comprises: the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11 thin film transistor (TFT) T11, the second phase inverter 2012 comprises: the 12 thin film transistor (TFT) T12, the 13 thin film transistor (TFT) T13 and the 14 thin film transistor (TFT) T14.In the present embodiment, the 9th thin film transistor (TFT) T9 is NMOS tube to the 14 thin film transistor (TFT) T14.
The grid of the 9th thin film transistor (TFT) T9 is all connected with high level signal input VDD with drain electrode, and source electrode is connected with the grid of described tenth thin film transistor (TFT) T10;
The grid of the tenth thin film transistor (TFT) T10 is connected with the source electrode of the 9th thin film transistor (TFT) T9, and drain electrode is connected with high level signal input VDD, and source electrode is connected with the input P of latch;
The grid of the 11 thin film transistor (TFT) T11 is connected with the output Q of latch, and source electrode is connected with low level signal input VSS, and drain electrode is connected with the input P of latch;
The grid of the 12 thin film transistor (TFT) T12 is all connected with high level signal input VDD with drain electrode, and source electrode is connected with the grid of the 13 thin film transistor (TFT) T13;
The grid of the 13 thin film transistor (TFT) T13 is connected with the source electrode of the 12 thin film transistor (TFT) T12, and drain electrode is connected with high level signal input VDD, and source electrode is connected with the output Q of latch;
The grid of the 14 thin film transistor (TFT) T14 is connected with the input P of latch, and source electrode is connected with low level signal input VSS, and drain electrode is connected with the output Q of latch.
In above-described embodiment, the first phase inverter 2011 and the second phase inverter 2012 are all be made up of NMOS tube, certainly, also can be made up of PMOS or CMOS tube.
Embodiments of the invention also provide a kind of array base palte, comprise the gate drive apparatus in above-described embodiment.
In addition, embodiments of the invention also provide a kind of display floater, comprise above-mentioned array base palte.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1. a shift register cell, comprising:
Latch and control circuit;
Described latch comprises: end to end first phase inverter and the second phase inverter, and the input of described latch is connected with secondary signal output, and output is connected with the first signal output part;
Wherein, described first signal output part is contrary with the level of the output signal of described secondary signal output;
It is characterized in that, described control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with signal input part, and drain electrode is connected with the input of described latch;
Second thin film transistor (TFT), its grid is connected with described clock signal input terminal, and source electrode is connected with described first signal output part;
3rd thin film transistor (TFT), its grid is connected with described signal input part, and source electrode is connected with high level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT).
2. shift register cell as claimed in claim 1, is characterized in that, also comprise:
4th thin film transistor (TFT), its grid is connected with reset signal input, and source electrode is connected with low level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT).
3. shift register cell as claimed in claim 1, is characterized in that:
Described first phase inverter comprises:
5th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the input of described latch;
6th thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
7th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the output of described latch;
8th thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
4. shift register cell as claimed in claim 1, is characterized in that:
Described first phase inverter comprises:
9th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
Tenth thin film transistor (TFT), its grid is connected with the source electrode of described 9th thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the input of described latch;
11 thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
12 thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
13 thin film transistor (TFT), its grid is connected with the source electrode of described 12 thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the output of described latch;
14 thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
5. a shift register cell, comprising:
Latch and control circuit;
Described latch comprises: end to end first phase inverter and the second phase inverter, and the input of described latch is connected with secondary signal output, and output is connected with the first signal output part;
Described first signal output part is contrary with the level of the output signal of described secondary signal output;
It is characterized in that, described control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with the first signal input part, and drain electrode is connected with the input of described latch;
Second thin film transistor (TFT), its grid is connected with described clock signal input terminal, and source electrode is connected with described first signal output part;
3rd thin film transistor (TFT), its grid is connected with secondary signal input, and drain electrode is connected with high level signal input, and source electrode is connected with the drain electrode of described second thin film transistor (TFT);
Wherein, described first signal input part is contrary with the level of the input signal of described secondary signal input.
6. shift register cell as claimed in claim 5, is characterized in that, also comprise:
4th thin film transistor (TFT), its grid is connected with reset signal input, and source electrode is connected with low level signal input, and drain electrode is connected with the drain electrode of described second thin film transistor (TFT).
7. shift register cell as claimed in claim 5, is characterized in that:
Described first phase inverter comprises:
5th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the input of described latch;
6th thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
7th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode, and source electrode is connected with the output of described latch;
8th thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
8. shift register cell as claimed in claim 5, is characterized in that:
Described first phase inverter comprises:
9th thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
Tenth thin film transistor (TFT), its grid is connected with the source electrode of described 9th thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the input of described latch;
11 thin film transistor (TFT), its grid is connected with the output of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the input of described latch;
Described second phase inverter comprises:
12 thin film transistor (TFT), its grid is all connected with described high level signal input with drain electrode;
13 thin film transistor (TFT), its grid is connected with the source electrode of described 12 thin film transistor (TFT), and drain electrode is connected with described high level signal input, and source electrode is connected with the output of described latch;
14 thin film transistor (TFT), its grid is connected with the input of described latch, and source electrode is connected with low level signal input, and drain electrode is connected with the output of described latch.
9. a gate drive apparatus, is characterized in that, comprising: be deposited on the multiple shift register cells as described in any one of claim 1-4 on array base palte, wherein,
Except first shift register cell, the signal input part of all the other shift register cells is connected with the secondary signal output of an adjacent upper shift register cell;
The signal input part of first shift register cell is connected with frame start signal input;
Except last shift register cell, the secondary signal output of all the other shift register cells is connected with the signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with the first clock cable, and the clock signal input terminal of even number shift register cell is connected with second clock holding wire;
The high level signal input of each shift register cell is connected with high level signal line, and low level signal input is connected with low level signal line;
The level of the clock signal that described first clock cable and described second clock holding wire export is contrary.
10. gate drive apparatus as claimed in claim 9, is characterized in that:
Except last shift register cell, the reset signal input of all the other shift register cells is connected with the first signal output part of adjacent next shift register cell;
The reset signal input of last shift register cell is connected with described frame start signal input.
11. 1 kinds of gate drive apparatus, is characterized in that, are deposited on the multiple shift register cells as described in any one of claim 5-8 on array base palte, wherein,
Except first shift register cell, first signal input part of all the other shift register cells is connected with the secondary signal output of an adjacent upper shift register cell, and secondary signal input is connected with the first signal output part of an adjacent upper shift register cell;
First signal input part of first shift register cell is connected with the first frame start signal input, and secondary signal input is connected with the second frame start signal input;
Except last shift register cell, first signal output part of all the other shift register cells is connected with the secondary signal input of adjacent next shift register cell, and secondary signal output is connected with the first signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with the first clock cable, and the clock signal input terminal of even number shift register cell is connected with second clock holding wire;
The high level signal input of each shift register cell is connected with high level signal line, and low level signal input is connected with low level signal line;
The level of the clock signal that described first clock cable and described second clock holding wire export is contrary, and the level of the input signal of described first frame start signal input and described second frame start signal input is contrary.
12. gate drive apparatus as claimed in claim 11, is characterized in that: except last shift register cell, the reset signal input of all the other shift register cells is connected with the first signal output part of adjacent next shift register cell;
The reset signal input of last shift register cell is connected with described first frame start signal input.
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| CN102956214A (en) * | 2012-11-19 | 2013-03-06 | 京东方科技集团股份有限公司 | Common electrode driving unit, liquid crystal display panel and liquid crystal display device |
| CN103236272B (en) * | 2013-03-29 | 2016-03-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate drive apparatus and display device |
| CN103345911B (en) | 2013-06-26 | 2016-02-17 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display device |
| CN104361875B (en) * | 2014-12-02 | 2017-01-18 | 京东方科技集团股份有限公司 | Shifting register unit as well as driving method, grid driving circuit and display device |
| CN108122529B (en) * | 2018-01-25 | 2021-08-17 | 京东方科技集团股份有限公司 | Gate driving unit, driving method thereof and gate driving circuit |
| CN109872673B (en) | 2019-04-09 | 2022-05-20 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit and display device |
| CN112542140B (en) | 2020-12-16 | 2022-05-31 | 合肥京东方卓印科技有限公司 | Shift register, gate drive circuit and drive method |
| CN113409717B (en) * | 2021-05-13 | 2022-06-10 | 北京大学深圳研究生院 | Shift register unit circuit, gate drive circuit and display |
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| CN102012591A (en) * | 2009-09-04 | 2011-04-13 | 北京京东方光电科技有限公司 | Shift register unit and liquid crystal display gate drive device |
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