CN113409717B

CN113409717B - Shift register unit circuit, gate drive circuit and display

Info

Publication number: CN113409717B
Application number: CN202110520882.4A
Authority: CN
Inventors: 张盛东; 廖聪维; 邱赫梓; 安军军; 林清平; 严建花; 李建桦
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2021-05-13
Filing date: 2021-05-13
Publication date: 2022-06-10
Anticipated expiration: 2041-05-13
Also published as: CN113409717A

Abstract

The application provides a shift register unit circuit, which comprises a set transistor, a control electrode, a first electrode and a second electrode, wherein the control electrode is configured to receive a previous-stage output signal; a reset transistor, a control electrode of which is configured to receive the output signal of the next stage, a second electrode of which is coupled to the low level, and the reset transistor is of an N type; a first CMOS inverter having an output coupled to a first pole of the set transistor, an input coupled to the output and to a first pole of the reset transistor, a first control pole configured to receive a high level, and a second control pole coupled to a low level; and a drive transistor having a first pole coupled to the output and to the first pole of the reset transistor, a second pole configured to receive a first clock signal, and a control pole coupled to the output of the first CMOS inverter and to the first pole of the set transistor; the active level of the first clock signal does not overlap with the active level period of the previous stage output signal and the active level period of the next stage output signal.

Description

Shift register unit circuit, gate drive circuit and display

Technical Field

The present application relates to an integrated circuit and a method for manufacturing the same, and mainly relates to a shift register unit circuit, a gate driving circuit and a display.

Background

Whether for large-size television displays, small-size cell phone displays, or miniature display applications for AR/VR, the main direction of development for active matrix displays is higher frame rates and higher resolutions. New displays place higher demands on the technology of driving the backplane. By adopting the three-dimensional integrated circuit and the manufacturing method thereof, the display resolution is improved by integrating the three-dimensional pixel circuit and the peripheral driving circuit thereof, and the driving capability of the transistor is improved by longitudinally expanding under the same display area so as to improve the display frame rate, so that the method is an inevitable choice for developing the next generation of novel display.

For example, in a small-sized mobile phone, a Thin Film Transistor (TFT) is used as a conventional driving backplane. For higher resolution mobile phone display (above 500 PPI), the development of the conventional TFT driving backplane technology is severely restricted. Amorphous silicon (a-Si) TFTs have advantages in that they are low-temperature, low-cost to fabricate in a large area, but their application in high resolution display is limited by defects such as low mobility and poor stability in long-term operation. The Low Temperature Polysilicon (LTPS) TFT has the advantages of high mobility and stability, and particularly, the P-type LTPS TFT has a mature process and good stability, but has the problems of poor large-area uniformity and large leakage current. Metal oxide TFTs (e.g., IGZO TFTs are a typical metal oxide TFT) are well-established process for implementing N-type devices, which have the advantages of low leakage current and good large area uniformity, but have mobility and stability that do not catch up with LTPS TFTs.

More specifically, from the viewpoint of displaying pixel circuits, the demand of new displays such as AMOLED, micro-LED, etc. for TFT pixel circuit arrays has increased significantly. The traditional TFT backboard technology is difficult to meet the requirements of high resolution, high reliability, low power consumption and the like. For a high performance AMOLED pixel circuit, it requires low leakage current and small parasitic capacitance of the addressing TFT (switching TFT); the on current of the driving TFT is required to be large and the device characteristics to be stable.

In terms of the application of the TFT integrated gate driving circuit, in the LTPS TFT integrated display gate driving circuit, in order to avoid circuit function failure caused by a large leakage current of the LTPS TFT, a complicated circuit structure such as a series TFT and a large number of devices are generally adopted. Furthermore, the power consumption of LTPS TFT integrated circuits is generally higher due to higher leakage current, higher device count, and higher refresh frequency.

For the gate driving circuit integrated with IGZO TFTs, to improve the driving capability of the circuit, IGZO TFTs with a larger size are generally used. However, for larger sized metal oxide TFTs, the parasitic capacitance is also relatively large, and thus a more complicated circuit structure is usually required to suppress the voltage feedthrough effect caused by the parasitic capacitance. This in turn leads to an increase in the dynamic power consumption of the gate driver circuit. In addition, IGZO TFTs generally use a voltage bootstrap technique or the like to increase the driving capability of the circuit. The voltage bootstrap technology improves the driving capability of the circuit, and increases the voltage noise on the output node of the circuit and the probability of misoperation of the circuit.

In summary, the driving circuit or pixel circuit formed by a single type of TFT transistor (whether N-type TFT or P-type TFT) cannot satisfy the above requirements of low power consumption and strong driving capability at the same time.

Disclosure of Invention

In order to solve the problems of the prior art, the present application provides a shift register unit circuit, which includes a set transistor (Tst), a control electrode of which is configured to receive an output signal of a previous stage shift register unit circuit, a second electrode of which is coupled to a low level, the set transistor being an N-type field effect transistor; a reset transistor (Trst) with a control electrode configured to receive the output signal of the shift register unit circuit of the next stage and a second electrode coupled to a low level, wherein the reset transistor is an N-type field effect transistor; a first CMOS inverter having an output coupled to the first pole of the set transistor, an input coupled to the output of the shift register cell circuit and the first pole of the reset transistor, a first control pole configured to receive a high level, and a second control pole coupled to a low level; and a drive transistor (Td) having a first pole coupled to the output of the shift register cell circuit and to the first pole of the reset transistor, a second pole configured to receive a first clock signal (CLK 1), and a control pole coupled to the output of the first CMOS inverter and to the first pole of the set transistor; the effective level of the first clock signal does not overlap with the effective level time period of the output signal of the previous stage shift register unit circuit and the effective level time period of the output signal of the next stage shift register unit circuit.

In particular, the first CMOS inverter includes a first transistor (T1) having a second electrode coupled to a high level, a first electrode coupled to a control electrode of the driving transistor, a control electrode coupled to a first electrode of the driving transistor and an output terminal of the present stage shift register unit circuit, the first transistor being a P type field effect transistor, and a second transistor (T4) having a first electrode coupled to the control electrode of the driving transistor, a second electrode coupled to a low level, a control electrode coupled to the output terminal of the present stage shift register unit circuit, wherein the second transistor is an N type field effect transistor.

In particular, the first CMOS inverter comprises a second transistor (T4) having a first electrode coupled to the control electrode of the driving transistor, a second electrode coupled to a low level, and a control electrode coupled to the output terminal of the present stage shift register unit circuit, wherein the second transistor is an N-type field effect transistor; a third transistor (T1 a) having a second pole coupled to a high level and a control pole coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the third transistor being a P-type field effect transistor, a fourth transistor (T1 b) having a second pole coupled to the first pole of the third transistor, a first pole coupled to the control pole of the driving transistor and a control pole coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the fourth transistor being a P-type field effect transistor.

In particular, the first CMOS inverter includes a second transistor (T4) having a first electrode coupled to the control electrode of the driving transistor, a second electrode coupled to a low level, and a control electrode coupled to the output terminal of the present stage shift register unit circuit, wherein the second transistor is an N-type field effect transistor; a third transistor (T1 a) having a second pole coupled to a high level and a control pole coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the third transistor being a P-type field effect transistor, a fourth transistor (T1 b) having a second pole coupled to the first pole of the third transistor and a first pole coupled to the control pole of the driving transistor and a control pole coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the fourth transistor being a P-type field effect transistor, and a fifth transistor (T6') having a first pole coupled to the first pole of the third transistor and a second pole coupled to a low level and a control pole coupled to the output terminal of the present stage shift register unit circuit.

In particular, the first CMOS inverter includes a second transistor (T4) having a first electrode coupled to the control electrode of the driving transistor, a second electrode coupled to a low level, and a control electrode coupled to the output terminal of the present stage shift register unit circuit, wherein the second transistor is an N-type field effect transistor; a third transistor (T1 a) having a second pole configured to receive a second clock signal (CLK 3) and having a control electrode coupled to the first pole of the driving transistor and the output terminal of the present stage shift register cell circuit, the third transistor being a P-type field effect transistor, a fourth transistor (T1 b) having a second pole coupled to the first pole of the third transistor and having a first pole coupled to the control electrode of the driving transistor and having a control electrode coupled to the first pole of the driving transistor, the fourth transistor being a P-type field effect transistor, a sixth transistor (T6 ") having a first pole coupled to the first pole of the third transistor and having a second pole coupled to a low level and having a control electrode coupled to the output terminal of the present stage shift register cell circuit; wherein there is no overlap between the high-level phase of the first clock signal and the high-level phase of the second clock signal.

In particular, the circuit further comprises a second CMOS inverter having an input coupled to the first pole of the set transistor, an output coupled to the output of the shift register unit circuit of the present stage and the first pole of the reset transistor, a first control pole configured to receive the first clock signal, and a second control pole coupled to a low level.

In particular, the second CMOS inverter comprises the driving transistor (T2), a second pole of the driving transistor is configured to receive the first clock signal, a first pole of the driving transistor is coupled to the output end of the current stage of the shift register unit circuit, and a control pole of the driving transistor is coupled to the output end of the first CMOS inverter; a seventh transistor (T7), a first pole of which is coupled to the output terminal of the present stage shift register unit circuit, a second pole of which is coupled to the low level, and a control pole of which is coupled to the control pole of the driving transistor, wherein the seventh transistor is an N-type field effect transistor.

In particular, the N-type field effect transistor and the P-type field effect transistor are located on a common substrate; the first and/or second electrode of the N-type field effect transistor and the control electrode of the P-type field effect transistor belong to the same first metal layer.

Specifically, the N-type field effect transistor includes an IGZO TFT whose active layer includes a metal oxide semiconductor; the P-type field effect transistor comprises an LTPS TFT, the active layer of which comprises polysilicon.

The application also provides a gate driving circuit, which comprises the shift register unit circuit.

The application also provides a display, which comprises a pixel array, a data driving circuit and the grid driving circuit.

Drawings

Embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:

FIGS. 1a-g are process flow diagrams illustrating a method for fabricating a three-dimensional integrated circuit according to one embodiment of the present application;

FIG. 2 is a cross-sectional schematic diagram of an integrated circuit fabricated using three-dimensional integrated fabrication techniques, according to one embodiment of the present application;

FIG. 3 is a circuit diagram of a three-dimensional integrated pixel cell according to one embodiment of the present application;

FIG. 4(a) is a schematic circuit diagram of a three-dimensional integrated pixel cell according to one embodiment of the present application;

FIG. 4(b) is a timing diagram illustrating the operation of the circuit shown in FIG. 4 (a);

FIG. 5(a) is a schematic circuit diagram of a three-dimensional integrated pixel cell according to another embodiment of the present application;

FIG. 5(b) is a timing diagram illustrating operation of the circuit shown in FIG. 5 (a);

FIG. 6 is a schematic diagram of a shift register unit circuit in a gate driving circuit of a conventional NMOS logic based AMOLED display;

FIG. 7(a) is a schematic diagram of a three-dimensional integrated shift register cell architecture according to one embodiment of the present application;

FIG. 7(b) is a timing diagram illustrating operation of the architecture shown in FIG. 7 (a);

FIG. 8(a) is a schematic diagram of a three-dimensional integrated shift register cell architecture according to another embodiment of the present application;

FIG. 8(b) is a timing diagram illustrating operation of the architecture shown in FIG. 8 (a);

FIG. 9 is a schematic diagram of a three-dimensional integrated shift register cell circuit according to an embodiment of the present application;

FIG. 10 is a circuit diagram of a three-dimensional integrated shift register cell according to another embodiment of the present application;

FIG. 11 is a circuit diagram of a three-dimensional integrated shift register cell according to an embodiment of the present application;

FIG. 12(a) is a schematic diagram of a three-dimensional integrated shift register cell according to another embodiment of the present application;

FIG. 12(b) is a timing diagram illustrating exemplary operation of the circuit of FIG. 12 (a);

FIG. 13 is a schematic diagram of a three-dimensional integrated shift register cell circuit according to an embodiment of the present application;

FIG. 14 is a circuit diagram of a three-dimensional integrated shift register cell according to another embodiment of the present application;

fig. 15 shows a transfer characteristic curve of a three-dimensional integrated TFT device according to an embodiment of the present application.

FIG. 16 is a schematic diagram illustrating a transient response of the three-dimensional integrated shift register cell circuit of FIG. 14 according to one embodiment of the present application; and

fig. 17 is a schematic diagram of an architecture of a display device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In large-sized televisions and small-sized mobile phone displays, the transistors used are typically Thin Film Transistors (TFTs); in AR/VR display applications, a commonly used transistor is a field effect transistor on a monocrystalline silicon substrate.

The transistor in the present application may be a field effect transistor. The control electrode refers to a gate electrode of the field effect transistor, the first electrode can be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode can be a source electrode or a drain electrode of the field effect transistor. In an N-type transistor, the voltage of the drain should be greater than or equal to the voltage of the source, so the position of the source and the drain will vary with the bias state of the transistor.

The following description is given by taking a thin film transistor as an example, and the drain and the source of the transistor in the embodiment of the present application may vary according to the bias state of the transistor. However, the present application is not limited to the thin film transistor. Although there are great differences in the sizes of transistors driving the backplate, the voltage and current ranges, etc., due to the significant differences in the display application scenarios, the three-dimensional integrated circuit disclosed in the present application can also be implemented using complementary field effect transistor technology on a single crystalline silicon substrate, or thin film transistor technology on a flexible substrate, as well as other field effect transistor technologies. Further, the description of the embodiments of the present application is generally developed by taking AMOLED display as an example. However, due to the similarity of the basic display principle, the embodiment of the application can also be applied to other active array display occasions such as micro-LEDs and the like.

As a result of research by the inventors of the present application, it is considered that, for a pixel circuit of a display, an address TFT may be implemented by an N-type TFT (e.g., a metal oxide TFT), and a driving TFT may be implemented by a P-type device (e.g., an LTPS TFT). Such a combination can better balance pixel circuit programming speed and current/voltage retention capability. More importantly, the P-type TFT and the N-type TFT can also form CMOS logic, and the CMOS logic is beneficial to simplifying pixel circuits and driving circuits of the display, suppressing static power consumption, reducing the number of driving lines and the like.

In order to realize the design, a heterogeneous TFT-based three-dimensional integration technology (such as a P-type LTPS TFT and an N-type IGZO TFT, a P-type LTPS TFT and an N-type a-Si TFT) can be utilized to enable TFT devices, capacitors and related interconnection wires to be arranged in a three-dimensional space, so that the integration degree of a circuit is greatly increased, the resolution of a corresponding display is higher, and a frame is narrower.

However, it is still more challenging to design a more reasonable TFT three-dimensional integrated circuit based on the existing LTPS, IGZO or a-Si technologies to take advantage of the respective technologies.

FIGS. 1a-g are process flow diagrams illustrating a method of fabricating a circuit according to one embodiment of the present application.

As shown in fig. 1a, a first metal layer M1 is formed on a substrate and patterned M1 to form first/second electrodes of a first transistor and a lower plate of a first capacitor.

Fig. 1b shows that a first active layer LTPS is formed on the substrate and the first metal layer and patterned to form an active region of the first transistor between and over the first/second electrodes of the first transistor.

As shown in fig. 1c, a first dielectric layer GI is formed on the substrate, the first active layer and the lower plate of the first capacitor.

As shown in fig. 1d, a second metal layer M2 is formed on the first dielectric layer and patterned, a control electrode of the first transistor is formed over the first dielectric layer between the first/second electrodes of the first transistor, and a first/second electrode of the second transistor is formed over the first capacitor.

As shown in fig. 1e, a second active layer IGZO is formed on the second metal layer and the first dielectric layer and patterned, and an active region of the second transistor is formed between and over the first/second electrodes of the second transistor.

Forming a second dielectric layer 2-GI on the control electrode of the first transistor and on the first dielectric layer and the active region of the second transistor, as shown in fig. 1 f;

as shown in fig. 1g, a third metal layer M3 is formed on the second dielectric layer and patterned to form an upper plate of a second capacitor over the control electrode of the first transistor and a control electrode of the second transistor over the second dielectric layer between the first/second electrodes of the second transistor.

According to one embodiment, the first transistor may be a LTPS TFT, which may be formed using a high temperature process. The first active layer may be polysilicon. The second transistor may be a metal oxide TFT, such as an IGZO TFT or other type of metal oxide TFT, and the formation process may utilize a low temperature process, so as not to affect the first transistor that has been fabricated first. The second active layer may be IGZO, but of course, if the second transistor is fabricated using an a-Si process, the active layer may be polysilicon.

FIG. 2 is a cross-sectional schematic diagram of an integrated circuit fabricated using three-dimensional integrated fabrication techniques, according to one embodiment of the present application. The left side is the TFT transistors formed using LTPS technology and the right side is the TFT transistors formed using IGZO technology. Also, as shown in fig. 2, a capacitance C1 is formed at the upper left by the metal of the same layer as the gate electrode of the LTPS TFT and the gate electrode of the IGZO TFT; another capacitor C2 is formed at the lower right using the source-drain electrodes of the IGZO TFT and the source-drain electrodes of the LTPS TFT in the same layer of metal.

The manufacturing method and the corresponding TFT three-dimensional integrated circuit can be used for a display, a light detector or a memory and the like.

The TFT three-dimensional integrated TFT circuit shown in fig. 2 has several advantages as follows:

1) the TFT and the capacitor in the circuit are realized by adopting a longitudinal stacking structure, so that the occupied area of the TFT circuit is reduced, and the TFT and the capacitor are beneficial to realizing higher display resolution and improving the integration level of circuits in a peripheral driving circuit and a display array. For a pixel circuit, an integrated gate driving circuit, a power supply circuit at the periphery of a display and the like of an AMOLED display, a capacitor device is often adopted, and the area occupied by the capacitor is generally large. The functions of the capacitor in the TFT integrated circuit include: stabilizing the potential of the internal node of the circuit, feeding the signal voltage, suppressing the voltage feed-through effect, suppressing the voltage/charge loss due to the leakage current, and the like. In the three-dimensional integrated structure of the TFT, various MIM capacitors as shown in C1 and C2 of FIG. 2 and the parallel connection of the MIM capacitors can be realized.

2) The N-type TFT and the P-type TFT in the circuit can be realized by adopting a longitudinally stacked structure, which is beneficial to realizing a CMOS inverter circuit with a compact structure, and is further beneficial to simplifying the area and power consumption of the whole TFT circuit and improving the reliability.

Embodiments of the pixel circuit of the AMOLED display implemented by using the three-dimensional integrated TFT process will be specifically described below.

In the pixel circuit, an address transistor T_ＳA first pole configured to receive the DATA signal DATA, a control pole configured to receive the SCAN signal SCAN, and a second pole coupled to the driving transistor T_DThe control electrode of (1). Conventional N-type driving transistor T_DMay be configured to receive a high level VDD, a second pole (source) coupled to the anode of the OLED, and the cathode of the light emitting device may be coupled to a ground potential. Considering that the pixel circuit is capable of providing a constant light emitting current to the light emitting element OLED in a longer frame time, the driving transistor capacitance T can be set_DAnd a first electrode of the control electrode is provided with C_sSo as to play a role of voltage stabilization.

FIG. 3 is a circuit diagram of a three-dimensional integrated pixel cell according to one embodiment of the present application.

When the three-dimensional integration technology is adopted for realizing, the addressing transistor T of the pixel circuit_sNMOS (such as IGZO TFT) can be adopted, and the leakage current is extremely small, so that the data refresh rate can be greatly reduced to save the power consumption of the display; its driving transistor T_DPMOS (e.g., LTPS TFT) may be used to provide strong driving capability. In addition, the capacitance C of the pixel circuit_sCapacitance C in FIG. 3 may be implemented using, for example, the capacitance at C2 in FIG. 2_s。

FIG. 4(a) is a circuit diagram of a three-dimensional integrated pixel unit according to an embodiment of the present application, and FIG. 4(b) is a timing diagram of the operation of the circuit shown in FIG. 4 (a). The pixel circuit is still realized by three-dimensional stacked and integrated combination of an N-type TFT, a P-type TFT and a capacitor.

According to one embodiment, the address transistor TS1 may be an N-type TFT, a first pole of which may be configured to receive the DATA signal DATA, and a second pole of which may be coupled to the drive transistor T_DA control electrode configured to receive the present-level SCAN signal SCAN [ N ]]。

According to one embodiment, the capacitor C_S1May be coupled between the second pole of the address transistor TS1 and the control pole of the drive transistor TD.

According to an embodiment, the driving transistor TD may be a P-type TFT, a second pole of which may be configured to receive a high level, and a first pole of which may be coupled to the anode of the OLED.

According to one embodiment, a P-type TFT transistor TS2 may be disposed between the first pole of the driving transistor and the anode of the OLED, and the control pole thereof is configured to receive the present stage SCAN signal SCAN [ N ], and the first pole thereof is coupled to the anode of the OLED.

According to an embodiment, the pixel circuit may further include an N-type TFT transistor TS3 having a control electrode configured to receive the present-stage SCAN signal SCAN [ N ], a second electrode coupled to the second electrode of TS2, and a first electrode coupled to the control electrode of the driving transistor TD.

According to one embodiment, the pixel circuit may further include an N-type TFT transistor TS4 having a first pole coupled to the second pole of the address transistor TS1, a second pole configured to receive the reference signal VREF, and a control pole configured to receive the next stage SCAN signal SCAN [ N +1 ].

The increased capacitance C in FIG. 4(a) compared to the pixel circuit shown in FIG. 3_S1The switching transistors TS2, TS3, TS4 function to extract the electrical characteristics of the driving transistor TD and perform real-time compensation.

As shown in FIG. 4(b), the operation of the pixel circuit can be divided into

(1) Programming and compensation phases

Current stage SCAN signal SCAN [ N ]]At high level, the next stage SCAN signal SCAN [ N +1]]At low level, the N-type switching transistors TS1 and TS3 are turned on, and the P-type switching transistor TS2 is turned off. The power supply branch of the OLED is then disconnected at the capacitor C_S1Is written with the DATA signal DATA at the left end of the capacitor C_S1The right end of the gate line stores the threshold voltage and mobility information of the driving transistor. (DATA signal DATA ratio SCAN [ N ] in FIG. 4(b)]A little later in time because of parasitic capacitance/resistance on the DATA line, etc., so that a certain amount of settling time is required for the DATA signal to actually load onto the pixel). Thus, the capacitance C_S1The voltage difference between the two ends is V_CS1=Vdata-（VDD-|Vth|+ΔV_μ) Wherein Δ V_μThe voltage values reflecting the unevenness of mobility and the degradation information.

(2) Driving the light emitting stage

When the SCAN signal SCAN [ N ] of the current stage is at a low level and the SCAN signal SCAN [ N +1] of the next stage is at a high level, the N-type switching transistors TS1 and TS3 are turned off, the P-type switching transistor TS2 is turned on, and the N-type switching transistor TS4 is turned on. The drive transistor TD thus provides a constant drive current and the OLED enters a light emitting state. The conduction of TS4 causes the left terminal voltage of the capacitor CS1 to change from Vdata at stage (1) to VREF, which variable is (VREF-Vdata) at the left terminal voltage of CS 1. Since the capacitor CS1 has a charge storage function, the amount of VCS1 cannot be abruptly changed, and thus the right end voltage of CS1 becomes VDD- | Vth | + Δ V μ + (VREF-Vdata). Thus, the value of the overdrive voltage of the drive transistor TD is

VSG-|Vth|= VDD-[VDD-|Vth|+ΔVμ+(VREF-Vdata）]-|Vth|=Vdata-VREF-ΔVμ

Since the current of the OLED depends on the value of the overdrive voltage of the TD, it can be seen from the above derivation that the value of the overdrive voltage of the pixel circuit has no relation with the threshold voltage | Vth | of the TD, the power supply voltage VDD, and the like. Therefore, it can be said that the pixel circuit has a compensation effect on unevenness or drift of the threshold voltage of the TFT, a voltage drop effect of the power supply voltage, and the like.

In addition, at the same time, since the Vth extraction process has a certain relationship with the mobility, the mobility-related quantity Δ V μ remains in the final overdrive voltage expression in the above formula. The current flowing through the drive transistor can be represented by the product of the drive transistor mobility μ and the overdrive voltage of the drive transistor. Assuming that the mobility μ of the driving transistor increases, Δ V μ increases, and it can be understood from the above formula that the corresponding overdrive voltage decreases, and thus the current flowing through the driving transistor does not vary much. Assuming that the mobility μ of the driving transistor decreases, Δ V μ decreases, and the corresponding overdrive voltage increases as can be seen from the above formula, so the current flowing through the driving transistor still does not vary much. Therefore, the circuit also has a certain compensation effect on the mobility unevenness or the degradation of the TFT.

Therefore, in summary, the present pixel circuit has an advantage of more comprehensive compensation effect, which can compensate not only the threshold voltage shift or unevenness of the driving transistor but also the mobility, the IR drop of the power supply line, and the like. This application provides simpler pixel circuits and drive signals, which is advantageous for improving the resolution of the display array. The display pixel circuit only needs 5 TFTs and 1 capacitor, and only needs one type of scanning signal line, so that the display pixel circuit is favorable for realizing higher resolution for actual layout design. In addition, since data writing and threshold voltage extraction are performed in parallel across the capacitor CS1, only two TFTs are required for the OLED emission control branch. In the conventional AMOLED pixel circuit, since data writing and threshold voltage extraction are related to the source and gate of the driving transistor TD in the light emission control branch of the OLED, in order to avoid mutual interference of initialization, data writing, threshold voltage extraction, light emission control, and other processes, the light emission control branch of the OLED generally has 3 TFTs. Thus, the power supply voltage value VDD of the OLED in the present pixel circuit can be reduced to a smaller value. The OLED pixel circuit has positive significance for improving the energy conversion efficiency of the OLED pixel circuit and reducing the power consumption of the AMOLED display.

FIG. 5(a) is a circuit diagram of a three-dimensional integrated pixel unit according to another embodiment of the present application, and FIG. 5(b) is a timing diagram of the operation of the circuit shown in FIG. 5 (a). The basic structure of the pixel circuit is still realized by the combination of three-dimensionally integrated N-type TFT and P-type TFT and capacitor.

According to one embodiment, the address transistor TS1 may be an N-type TFT, a first pole of which may be configured to receive the DATA signal DATA, and a second pole of which may be coupled to a control pole of the driving transistor TD, a control pole of which is configured to receive the present-stage SCAN signal SCAN [ N ].

According to an embodiment, the capacitor Cs2 may be coupled between the second pole of the address transistor TS1 and the control pole of the drive transistor TD.

According to an embodiment, the driving transistor TD may be a P-type TFT, a second pole of which may be configured to receive a high level VDD, and a first pole of which may be coupled to the anode of the OLED.

According to an embodiment, a P-type TFT transistor TS2 may be disposed between the first electrode of the driving transistor and the anode of the OLED, and a control electrode thereof is configured to receive the present-stage SCAN signal SCAN [ N ], and the first electrode of TS2 is coupled to the anode of the OLED.

According to an embodiment, the pixel circuit may further include an N-type TFT transistor TS5 having a control electrode configured to receive the previous stage SCAN signal SCAN [ N-1], a second electrode coupled to the second electrode of TS2, and a first electrode coupled to the control electrode of the driving transistor TD.

The circuit of fig. 5(a) differs from the circuit of fig. 4(a) in that one switching TFT and one bias VREF line can be reduced by timing coordination of the scan signal and the data signal. The specific differences are as follows: 1) an overlap of half pulse time exists between the effective level stage of the scanning line SCAN [ N-1] of two adjacent rows of pixels and the effective level stage of SCAN [ N ]; 2) during the second half of the pulse of SCAN [ N ], the DATA voltage jumps to the VREF voltage, so that the pixel starts to emit light.

According to one embodiment, the DATA in fig. 5(b) represents the signal on the DATA line that is the DATA signal and the reference signal collocated, by transmitting the DATA signal and the reference signal at different times using the same DATA line. This reduces the number of signal driving lines and accordingly the number of switching transistors, thereby saving circuit area. As shown in fig. 5(b), intervals are inserted between each pulse, and a reference signal is transmitted on the data line during these intervals, and a data signal is transmitted on the data line during the other intervals. That is, after each data signal transmission is finished, the reference potential is returned, and then the next data signal is transmitted. When the reference signal VREF is, for example, the ground potential, power consumption at the time of a data signal transition can be reduced. Because work is required if one data signal is directly modulated to another data signal; however, if the first data signal jumps to the ground potential, no work is needed, and then the second data signal jumps to the other data signal from the ground potential, so that the power consumption can be saved.

Specifically, the working process of the circuit can be divided into:

(1) compensation phase

SCAN [ N-1] and SCAN [ N ] are both high, so TS1 and TS5 are turned on, and the reference signal VREF is transmitted on the DATA line DATA. Similar to the embodiment shown in FIG. 4, the left and right ends of capacitor CS2 are first programmed to VREF and VDD- | Vth | + Δ V μ, respectively. That is, the left and right ends of the capacitor CS2 store the reference voltage, threshold voltage information, and the like.

Before the end stage of the compensation stage (1), the voltage transmitted on the DATA line DATA becomes VDATA, and the voltage at the left end of the capacitor CS2 becomes VDATA; since TS5 remains on during the compensation phase (1), the voltage at the right end of capacitor CS2 remains VDD- | Vth | + Δ V μ.

(2) Programming phase

SCAN [ N-1] goes low and SCAN [ N ] remains high, so TS5 is opened and TS1 remains closed, at which time the transmit signal on DATA line DATA goes back to VREF. Similar to the embodiment shown in FIG. 4, the left and right ends of capacitor CS2 are programmed to VREF and VDD- | Vth | + Δ V μ + (VREF-VDATA), respectively, due to the charge conservation effect on capacitor CS 2.

(3) Driving the light emitting stage

Scan N goes low so TS1 is turned off, switching transistor TS2 is turned on, driving transistor TD is turned on and supplies a driving current to the OLED of the pixel, and the driving transistor TD keeps a state of driving the OLED to emit light until a state update is performed in a programming and compensation phase of a next frame. The overdrive voltage of the driving transistor TD may be expressed as:

VSG-|Vth|= VDD-[VDD-|Vth|+ΔVμ+(VREF-VDATA）]-|Vth|= VDATA-VREF-ΔVμ

since the current of the OLED mainly depends on the overdrive voltage of the driving transistor TD, it can be seen from the formula that the value of the overdrive voltage is independent of Vth and VDD, which means that the pixel circuit has a better compensation effect for possible shifts of Vth and VDD.

As can be seen from the above analysis, the main advantage of the pixel circuit illustrated in fig. 5(a) is the smaller number of transistors and driving signal lines. So that transistor TS1 functions as both the data voltage programming and the light emission phase. The same DATA line DATA transmits DATA signals or reference signals at different time periods, and a signal line specially provided for the reference signal is omitted. And the SCAN signal line SCAN N serves as both a data write address and a light emission control function, so that the function of the control line is maximized. Therefore, the resolution of the display array can be further improved with the pixel circuit as compared with the conventional pixel circuit.

Embodiments of a shift register unit circuit constituting a display gate driving circuit implemented using a three-dimensional integrated TFT process will be described below one by one.

Fig. 6 is a schematic diagram illustrating a shift register unit circuit in a gate driving circuit of a conventional NMOS logic-based AMOLED display. Wherein the driving transistor T2 is an N-type device, such as an IGZO TFT. Since the input signal GN-1 is a high level pulse, T2 also cuts the high level of CLK1 and propagates to GN. Therefore, in order to suppress the voltage loss of the NMOS when passing high, a voltage bootstrap needs to be introduced between the gate and the source of T2, i.e. the gate potential of T2 is increased with the increase of GN. Also, the voltage bootstrap problem causes a series of problems such as instability of the QN node and the GN node in the low level hold stage.

As can be seen from fig. 6, in the shift register unit circuit of the conventional AMOLED display gate driving circuit, QN point and PN point are 2 important internal nodes. There is a voltage competition relationship between the two internal nodes. Wherein, the QN point should be kept as a high level voltage in the pre-charging and light-emitting stage and as a low level voltage in the low level maintaining stage; the PN point should be a low level voltage in the precharge and emission phases and a high level voltage in the low level sustain phase.

In fact, these requirements are contradictory, for example, T4 and T5 are in a competitive relationship. The function of T4 is to pull PN to a low position in response to the high voltage of QN; the effect of T5 is to pull QN low in response to the high voltage of PN. Then, the high level voltage of PN inhibits the pull-up of QN at the initial timing of the precharge. Similarly, the high voltage of QN also suppresses the pull-up of PN at the beginning of the low hold phase. For the conventional shift register unit circuit, the competition relationship between the internal nodes PN and QN easily causes the function of the circuit to be invalid, which requires careful selection of the device size in the conventional shift register unit circuit.

Fig. 7(a) is a schematic diagram illustrating a shift register unit architecture in a three-dimensional integrated gate driving circuit according to an embodiment of the application. FIG. 7(b) is a timing diagram illustrating operation of the architecture shown in FIG. 7 (a). According to one embodiment, the shift register unit may include a set transistor Tst, a reset transistor Trst, a first inverter Inv1, and a driving transistor Td.

As illustrated in fig. 7(b), GN-1, GN, and GN +1 are outputs of the N-1 th stage, the nth stage (present stage register), and the N +1 th stage shift register unit, respectively, CLK1 is a clock signal required for the shift register circuit to operate normally, QN is an internal node of the shift register circuit, and VSS is a low-level voltage signal common to the shift registers of the respective stages. In the display array, the output signals GN-1, GN, and GN +1 of each row of the shift register have a scanning pulse duration Tp, a high-level pulse width time of CLK1 is Tp, and a low-level pulse width of the internal node QN is 2 × Tp. (p 1= p2= Tp in the figure)

According to one embodiment, the set transistor Tst may be an N-type TFT, a first pole of which may be coupled to the output terminal of the first inverter INV1, a second pole of which may be configured to receive the low potential VSS, and a control pole of which may be configured to receive the output GN-1 of the shift register unit of the previous stage.

According to one embodiment, the reset transistor Trst may be an N-type TFT, a first pole thereof may be coupled to an input terminal of the first inverter INV1 and the shift register unit output GN of the present stage, a second pole thereof may be configured to receive the low potential VSS, and a control pole thereof may be configured to receive the output GN +1 of the shift register unit of the subsequent stage.

According to one embodiment, the driving transistor Td may be a P-type transistor, a control electrode of which may be coupled to the output terminal of the first inverter Inv1 and a first electrode of the set transistor Tst, a first electrode (drain) of which may be coupled to the output terminal GN of the present stage circuit, and a second electrode (source) of which is configured to receive the first clock signal CLK 1.

According to one embodiment, when a high level pulse of the output signal GN-1 of the previous stage of shift register unit arrives, the potential of the internal node QN, i.e., the potential of the control electrode of the driving transistor Td is pulled low, the driving transistor Td is turned on, and when the CLK1 is at a high level, the driving transistor Td pulls up the potential of the output GN of the present stage of shift register unit. When a high-level pulse of the output signal GN +1 of the shift register unit of the next stage comes, the reset transistor Trst is turned on, and the potential of the output terminal GN is pulled to a low level.

In the present embodiment, the first inverter Inv1 functions to maintain the potential of the internal node QN at a low level when the potential of the GN point is at a high level (stage P2 in fig. 7 b). When the potential of the output GN point is pulled low (P3 stage of fig. 7 (b)), the potential of the internal node QN is pulled up, and the driving transistor Td is turned off before the high level of the clock signal CLK1 comes. As illustrated in fig. 7(a) and (b), the internal node QN of the shift register circuit is pulled down to a low level through the transistor Tst during the P1 phase, and is pulled down to a low level through the inverter Inv1 during the P2 phase. Due to the difference in the driving capability of the two pull-down paths, there will be a certain difference in the low level values of the internal node QN at the P1 and P2 stages, as shown in fig. 7(b)

Fig. 8(a) is a schematic diagram of a shift register unit architecture in a three-dimensional integrated gate driving circuit according to another embodiment of the present application. FIG. 8(b) is a timing diagram illustrating operation of the architecture shown in FIG. 8 (a).

As illustrated in fig. 8(b), GN-1, GN, and GN +1 are outputs of the N-1 th stage, the nth stage (present stage register), and the N +1 th stage shift register unit, respectively, CLK1 is a clock signal required for the shift register circuit to operate normally, QN is an internal node of the shift register circuit, and VSS is a low-level voltage signal common to the shift registers of the respective stages. In the display array, the output signals GN-1, GN, and GN +1 of each row of the shift register have a scanning pulse duration Tp, a high-level pulse width time of CLK1 is Tp, and a low-level pulse width of the internal node QN is 2 × Tp. (p 1= p2= Tp in the figure)

According to one embodiment, the shift register cell circuit may include a set transistor Tst, a reset transistor Trst, a first inverter Inv1, and a second inverter Inv 2.

According to one embodiment, the set transistor Tst may be an N-type TFT, a first pole of which may be coupled to an output terminal of the first inverter INV1 and an input terminal of the second inverter INV2, a second pole of which may be configured to receive the low potential VSS, and a control pole of which may be configured to receive the output GN-1 of the shift register unit of the previous stage.

According to an embodiment, the reset transistor Trst may be an N-type TFT, a first pole of which may be coupled to the output terminal of the second inverter INV2, the output terminal GN of the present stage shift register unit, and the input terminal of the first inverter INV1, a second pole of which may be configured to receive the low potential VSS, and a control pole of which may be configured to receive the output GN +1 of the shift register unit of the subsequent stage.

According to one embodiment, an output of the first inverter INV1 is coupled to an input of the second inverter INV 2; an output of the second inverter INV2 is coupled to an input of the first inverter INV 1. A first control terminal of the first inverter INV1 is configured to receive a high voltage VDD, a first control terminal of the second inverter INV2 is configured to receive the clock signal CLK1, and a second control terminal of both inverters is configured to receive a low voltage VSS.

According to one embodiment, when a high level pulse of the output signal GN-1 of the previous stage shift register unit arrives, the potential of the internal node QN (i.e., the potential of the input terminal of the second inverter INV 2) is pulled low, and the second inverter INV2 pulls up the potential of the output GN of the current stage shift register unit. Since the high-voltage terminal or the first control terminal of the second inverter Inv2 is configured to receive the clock signal CLK1, the potential of the output terminal GN is pulled to a high level when CLK1 jumps to a high level. When a high-level pulse of the output signal GN +1 of the shift register unit of the next stage arrives, the reset transistor Trst is turned on, and the potential of the output terminal GN of the shift register unit of the present stage is pulled to a low-level voltage.

In the present embodiment, the second inverter Inv2 functions to maintain the potential of the internal node QN at a low level all the time when the potential of the GN point is at a high level. When the potential of the output GN point is pulled low, the pull-up process of the internal node QN is accelerated, and the pull-up transistor of the second inverter Inv2 is turned off before the high level of the clock signal CLK1 arrives.

FIG. 9 is a circuit diagram of a three-dimensional integrated shift register cell according to an embodiment of the present application, which is a specific embodiment of the architecture shown in FIG. 7 (a).

According to one embodiment, the second pole of the input transistor T1 (P-type) is configured to receive the high level VDD, and the first pole is coupled to the control pole of the driving transistor T2 (P-type) (equivalent to Td in fig. 7 (a)) which is coupled to the first pole (drain) of the driving transistor T2. The first inverter may include a switching transistor T4 and an input transistor T1. The input terminals of the first inverter, that is, the output terminal GN of the shift register unit of this stage, the control electrodes of the transistor T4 and the transistor T1, are the node QN, the control electrode of the driving transistor T2 and the first electrode of the input transistor.

According to one embodiment, the second pole (source) of the driving transistor T2 is configured to receive the clock signal CLK1, and its first pole is coupled to the present stage shift register cell output GN.

According to one embodiment, the switching transistor T3 has a first electrode coupled to the control electrode of the driving transistor T2, a second electrode configured to receive the low level VSS, and a control electrode coupled to the output terminal GN-1 of the shift register unit of the previous stage.

According to one embodiment, the switching transistor T4 has a first electrode coupled to the control electrode of the driving transistor T2, a second electrode configured to receive the low level VSS, and a control electrode coupled to the output terminal GN of the present stage shift register unit.

According to one embodiment, the switching transistor T5 has a first electrode coupled to the second electrode of the driving transistor T2, a second electrode configured to receive the low level VSS, and a control electrode coupled to the output terminal GN +1 of the shift register unit of the next stage.

According to one embodiment, the driving transistor T2 and the input transistor T1 may both be P-type TFTs, such as LTPS TFTs, which may achieve stronger driving capability. The switching transistors T3, T4, T5 may all employ N-type TFTs, such as IGZO TFTs.

In the prior art, for a gate driving circuit built only by using N-type TFTs (such as IGZO TFTs or a-Si TFTs), in order to pursue strong driving capability, the gate potential of the driving transistor can only be raised along with the increase of the output potential by voltage bootstrap. As representative of P-type TFTs, LTPS TFTs have a mobility 10 times that of IGZO TFTs and 300 times that of a-Si TFTs. Therefore, when LTPS TFTs are used as the driving transistors of the shift register unit in the gate driving circuit, it is not necessary to use voltage bootstrap to improve the driving capability. This avoids noise from bootstrapping.

The opening of the driving transistor T2 is here realized by means of a GN-1 controlled T3. When CLK1 changes from low to high voltage, the conducting T2 transmits a high level pulse of CLK1 to the GN terminal. Since GN outputs a high level pulse, T1 is turned off. After GN +1 goes high, GN is pulled down to low; at the same time, T1 is turned on, T3 and T4 are turned off, and the gate of the driving transistor T2 is held at a high level potential.

According to the timing chart shown in fig. 7(b), the high level pulse of GN-1 leads the high level pulse of CLK 1; in other words, before the high level pulse of CLK1 comes, the gate potential of T2 is pulled low through T3, and T2 is turned on. When the high level of CLK1 arrives, the high level pulse is passed on to the GN node through the open T2.

T2 needs to be kept open during both the precharge phase (p1) and the output high pulse (p 2). Therefore, T3 and T4 are turned on during the P1 and P2 phases respectively to pull the gate of T2 to a low level potential, so that T2 remains on during the P1 and P2 phases.

And T5 functions to pull the output GN node to a low level voltage in response to a high level pulse signal of GN + 1. Since the potential at GN is low, T1 is turned on, and VDD is transferred to the gate of T2, T2 is turned off, which enters the low sustain phase: the gate voltage of T2 is maintained at the high level voltage VDD, and the output node GN is maintained at the low level.

Fig. 10 is a schematic circuit diagram of a three-dimensional integrated shift register unit according to another embodiment of the present application, which is another specific example of fig. 7 (a).

According to one embodiment, the input transistor T1a (P-type) has a second pole (source) configured to receive the high level VDD, a first pole coupled to the second pole of the input transistor T1b (P-type) and a control pole coupled to the first pole (drain) of the driving transistor T2 (P-type).

According to one embodiment, the input transistor T1b (P-type) has a first electrode coupled to the control electrode of the drive transistor T2, which is coupled to the control electrode of the input transistor T1 a.

According to one embodiment, the second pole (source) of the driving transistor T2 (equivalent to Td in fig. 7 (a)) is configured to receive the clock signal CLK1, and its first pole is coupled to the output GN of the present stage shift register unit.

According to one embodiment, a first pole of a switching transistor T3 (N-type) (corresponding to Tst in fig. 7 (a)) is coupled to a control pole of a driving transistor T2, a second pole thereof is configured to receive a low level VSS, and a control pole thereof is coupled to an output terminal GN-1 of a shift register unit of a previous stage.

According to one embodiment, a first pole of the switching transistor T6 (N-type) is coupled to a first pole of the input transistor T1a and a second pole of the input transistor T1b, the second pole thereof is configured to receive the low level VSS, and a control pole thereof is coupled to the output terminal GN-1 of the shift register unit of the previous stage.

According to one embodiment, a first pole of a switch transistor T4 (N-type) is coupled to a control pole of a driving transistor T2, a second pole thereof is configured to receive a low level VSS, and a control pole thereof is coupled to an output terminal GN of the present stage shift register unit.

According to one embodiment, a first pole of a switching transistor T5 (N-type) (corresponding to Trst in fig. 7 (a)) is coupled to a first pole of a driving transistor T2, a second pole thereof is configured to receive a low level VSS, and a control pole thereof is coupled to an output terminal GN +1 of a next stage shift register unit.

According to one embodiment, the driving transistor T2 and the input transistors T1a, T1b may both be P-type TFTs such as LTPS TFTs, which may achieve stronger driving capability. The switching transistors T3, T4, T5, and T6 may all employ N-type TFTs, such as IGZO TFTs.

In the present embodiment, the T4, T1a, and T1b transistors constitute a first CMOS inverter structure. When GN is high, the first inverter outputs low, that is, the transistor T4 is turned on, the control electrode of the transistor T2 is pulled down to low, so that the driving transistor T2 is maintained in a turned-on state, and the output port GN is still at high level.

It should be noted that when the PMOS transistor transmits a high level, the gate or the control electrode of the PMOS transistor is maintained at a low level, and there is no voltage loss problem. When the NMOS transistor transmits a high level, since the charging speed is gradually reduced as the output voltage increases, if a single NMOS logic is used, there are problems of loss of threshold voltage, slow driving speed, and the like. Therefore, the PMOS driving transistor in the present application can solve the above problems of the prior art using a single NMOS transistor to construct the gate driving circuit of the shift register unit.

When GN is low, the first inverter output is high because T1a and T1b are on, and transistor T2 remains off.

Compared with the shift register unit circuit embodiment in fig. 9, the difference here is that the stacked input structure is newly added, i.e., T1a, T1b and T6 constitute a new inverter pull-up structure. This stacked input architecture is advantageous for mitigating the race hazard problem of the high-level pulse input stage of GN-1. Corresponding to the turn-on of T6 (GN-1 is a high level pulse), T1a and T1b discharge in parallel. Thus, the gate of T2 is pulled low to a low level, which provides for the generation of a high level pulse at the output terminal GN. Transistors T3 and T6 are coupled to the first and second poles of T1b, respectively, for pull-down, which enhances input programmability.

By employing the stacked pull-up structure in this embodiment, when GN-1 is high, the intermediate node of T1a and T1b connected in series is pulled low through T6. T1b can then be turned off well at the input node and the QN point is pulled low at full amplitude. When the circuit enters the low sustain phase, GN-1 is low, T6 is turned off, T1a and T1b are kept on, and the gate potential of T2 is kept high. Since the stacked pull-up structure is composed of two P-type LTPS TFTs (T1 a and T1 b) connected in series, the LTPS TFT has a strong ability to suppress leakage current in an off state thereof, and has a driving ability stronger than that of the IGZO TFT, so that the voltage of the QN node is not easily pulled down in a low-level sustain stage. Therefore, the stack pull-up structure can balance between low leakage current and strong driving capability.

FIG. 11 is a schematic circuit diagram of a three-dimensional integrated shift register unit according to an embodiment of the present application, which is another example of FIG. 7 (a).

According to one embodiment, the input transistor T1a (P-type) has a second pole configured to receive the high level VDD, a first pole coupled to the second pole of the input transistor T1b, and a control pole coupled to the first pole of the driving transistor T2 (equivalent to Td). Here, the transistors T1a, T1b, T4, T6' constitute a first inverter.

According to one embodiment, the second pole of the driving transistor T2 (P-type) (equivalent to Td) is configured to receive the clock signal CLK1, and its first pole is coupled to the present stage shift register unit output GN.

According to one embodiment, a first pole of a switching transistor T3 (N-type) (corresponding to Tst) is coupled to a control pole of a driving transistor T2, a second pole thereof is configured to receive a low level VSS, and a control pole thereof is coupled to an output terminal GN-1 of a previous stage shift register unit.

According to one embodiment, a first pole of a switching transistor T6' (N-type) is coupled to a first pole of an input transistor T1a and to a second pole of an input transistor T1b, the second pole thereof being configured to receive a low level VSS, and a control pole thereof being coupled to an output GN of the present stage of shift register cells.

According to one embodiment, a first pole of a switching transistor T4 (N-type) is coupled to the control pole of the driving transistor T2, a second pole thereof is configured to receive the low level VSS, and a control pole thereof is coupled to the output GN of the present stage shift register unit.

According to one embodiment, a first pole of a switching transistor T5 (N-type) (corresponding to Trst) is coupled to a first pole of a driving transistor T2, a second pole thereof is configured to receive a low level VSS, and a control pole thereof is coupled to an output terminal GN +1 of a next stage shift register unit.

According to one embodiment, the driving transistor T2 and the input transistors T1a, T1b may both be P-type TFTs such as LTPS TFTs, which may achieve stronger driving capability. The switching transistors T3, T4, T5, and T6' may be N-type TFTs, such as IGZO TFTs.

In the shift register unit circuit of the present embodiment, the difference from the circuit in fig. 10 is that transistors for feedback pull-down are T4 and T6'. This is advantageous in stabilizing the gate potential of the driving transistor T2 during the high-level output phase. Due to the pull-down of the first and second poles of T4 and T6' respectively coupled to T1b, the voltage contention among the transistors T1a, T1b and T4 when the output GN of the shift register cell of this stage is high can be better avoided.

In the stacked input configuration of the present circuit, the intermediate nodes of T1a and T1b are pulled down to a low level through T6 ', while the gate/control of T6' is coupled to GN. In this embodiment, although in the precharge phase, the QN point cannot be pulled to the low level voltage at full amplitude; however, as GN begins to rise, the QN point is pulled down to the low level VSS through T4, while the turn-on of T6' causes T1b to be better turned off. In summary, therefore, the QN point can be pulled down to the low level voltage VSS at full amplitude during the high level pulse generation phase of GN, which maintains strong driving capability of the transistor T2.

FIG. 12(a) is a circuit diagram of a three-dimensional integrated shift register unit according to another embodiment of the present application, which is an embodiment of the architecture of FIG. 7(a), but the applied signals are different from those of FIG. 7 (b). Fig. 12(b) is an exemplary operation timing chart of the shift register unit circuit in the present embodiment.

In the present embodiment, the input terminals of the first inverter inv1 (constituted by the transistors T1a, T1b, T4 and T6 ″), i.e., the gates of the transistors T1a, T1b, T4 and T6 ″ (the gates of these 4 transistors are connected together as shown in fig. 12 (a)), are configured to be connected to the output GN terminal of the shift register circuit; the control terminal of the first inverter inv1, i.e., the source (second pole) of the transistor T1a, receives not the constant high level VDD but the clock signal CLK 3. With the shift register cell circuit configuration shown in fig. 7(a), since the control terminal of the inverter inv1 is configured to receive a high level VDD, QN should be pulled down to a low level voltage although GN-1 is high; however, since GN is low at the same time, QN is not completely pulled down by the pull-up path of the inverter Inv1, which causes a dc path and a contention hazard relationship in which QN logic is uncertain. Due to the misalignment of the active level pulses between the CLK3 and CLK 1' and the GN-1 signal, the race hazard, dc power consumption, etc. of the shift register structure shown in fig. 7(a) can be avoided more effectively.

In the basic shift register unit circuit structure (as shown in fig. 9), there is a competition risk between the pull-up process of T1 and the pull-down process of T3 during the precharge phase. In the present embodiment, the control terminal of the inverter INV1 is coupled to the clock signal CLK3 instead of the constant potential VDD. By reasonable selection of clock signals, for example, the duty ratios of the non-overlapping clocks CLK 1' and CLK3 are both 25% or less than 25%, and the active level period of CLK3 and the active level period of GN-1, GN +1 (for example, in this embodiment, since the addressing transistor TS1 of the OLED pixel circuit is an N-type device, the active level is a high level) do not overlap each other; then CLK3 is a low level voltage when GN-1 is a high level pulse. Therefore, during the pre-charging phase, both T1a and T1b can be completely turned off in the pull-up structure, which can further reduce the dc power consumption, so that the full-scale voltage at the point QN in the pre-charging phase is pulled down to VSS.

FIG. 13 is a circuit diagram of a three-dimensional integrated shift register cell according to an embodiment of the present application, which is an example of the architecture of FIG. 8 a. The first inverter INV1 includes T1 (P type) and T4 (N type); the second inverter INV2 includes T2 (P type) and T5 (N type).

Since the driving transistor T2 employs a P-type field effect transistor, the voltage loss problem of the NMOS passing high level is well avoided. The input transistor T3 controlled by GN-1 passes a low level, turns on the driving transistor T2, and passes a high level to the GN terminal.

The important node inside the circuit shown in fig. 13 is the QN point. When the output GN is at high level, the QN point is at low level voltage; while the output GN maintains the low level voltage, the QN point maintains the high level voltage. This requirement is then well met by the cross-coupled structure of T4 and T5: when the output GN is a high level pulse, T4 is turned on, and the QN point potential is pulled low; and when the output GN is in the low level sustain phase, T5 is turned on, and then GN is maintained at a low level. The P-type driving transistor T2 and the N-type device T5 form a first inverter; the P-type transistor T1 and the N-type transistor T4 constitute a second inverter. The triggering process of the two cross-coupled inverter logic is due to the T3 transistor being controlled by GN-1.

When GN-1 is low, the two cross-coupled inverters remain in the original potential state by virtue of positive feedback logic. When GN-1 changes to high level, the state of the first inverter is inverted, so that the state of the second inverter is also inverted, and high level output of GN is realized.

FIG. 14 is a circuit diagram of a three-dimensional integrated shift register cell according to another embodiment of the present application, which is an example of the architecture of FIG. 8 (a).

According to one embodiment, the second pole of the input transistor T1a (P-type) is configured to receive a high level VDD, the first pole is coupled to the second pole of the input transistor T1b (P-type), and the control pole is coupled to the first pole of the driving transistor T2.

According to one embodiment, the second pole of the driving transistor T2 (P-type) is configured to receive the clock signal CLK1, and its first pole is coupled to the present stage shift register cell output GN.

According to one embodiment, a switch transistor T3 (N-type) has a first pole coupled to the control pole of the driving transistor T2, a second pole configured to receive the low level VSS, and a control pole coupled to the output terminal GN-1 of the previous stage shift register unit.

According to one embodiment, a first pole of the switching transistor T5 (N-type) is coupled to a first pole of the driving transistor T2, a second pole thereof is configured to receive the low level VSS, and a control pole thereof is coupled to the output terminal GN +1 of the next stage shift register unit.

According to one embodiment, the switching transistor T7 (N-type) has a first pole coupled to the current stage shift register cell output GN, a second pole coupled to a low potential, and a control pole coupled to the control pole of the driving transistor T2.

According to one embodiment, the driving transistor T2 and the input transistors T1a, T1b may both be P-type TFTs such as LTPS TFTs, which may achieve stronger driving capability. The switching transistors T3, T4, T5, T6', and T7 may all employ N-type TFTs, such as IGZO TFTs.

In the present embodiment, the transistors T3 and T4 function as a precharge section, T2 functions as a drive transistor, T5 functions as a pull-down transistor, and T1a and T1b function as clock feedthrough suppression devices. T7 is a feedback structure for maintaining the output GN low. For the shift register unit circuit, the output terminal GN should be maintained at a low level most of the time. In the circuit of this embodiment, the feedback structure of T7 can achieve both the turn-off of T2 and the turn-on pull-down of T7 when the gate/control electrode of the driving transistor T2 is maintained at a high level.

In this embodiment, there are two inverters in series in this circuit: the first inverter INV1 is formed of T1a, T1b, T4 and T6', and functions to set the gate/control electrode of T2 to a high level when GN is a low level, and to set the gate/control electrode of T2 to a low level when GN is a high level. The second inverter INV2 is composed of T2 and T7, and when the gate/control electrode of T2 is high, the output is low; when the gate/control of T2 is very low, the output is high.

In the pulse output stage, QN is a low level voltage, and T7 remains in the off state; the added T7 then does not cause a loss of pulses in the output GN. In the low hold phase, QN is high, T7 remains open, and the output GN remains low.

It is noted that the added device T7 in this embodiment can better maintain the output node of the shift register circuit at a low level. The shift register unit circuits shown in fig. 9, 10, 11, and 12(a) to 13 can suppress the voltage feedthrough effect caused by the clock signal CLK1 well. On the other hand, the output node potential of a gate driving circuit including, for example, an array of shift-up register cells may also be affected by voltage jumps on data driving lines in a display array. Taking the AMOLED pixel array as an example, there are a large number of data driving lines in a direction perpendicular to the gate scan lines, and the voltage on the data lines jumps at a high frequency. In order to suppress the possible interference of the display array, the gate scan lines should have strong low-level sustain capability. The newly added transistor T7 in the present embodiment as shown in fig. 14 enables the shift register unit circuit of the present embodiment to have a strong capability of low level holding capability.

Fig. 15 shows transfer characteristics of a three-dimensional integrated TFT device according to an embodiment of the present application, i.e., Ids of two types of TFTs varies with VGS. As can be seen from the figure, when the value of VGS is more negative, the P-type LTPS TFT device is in a conducting state, and the corresponding Ids value is larger; when the value of VGS is relatively positive, the N-type IGZO TFT device is in a conducting state, and the corresponding Ids value is relatively large. The LTPS TFT and the IGZO TFT illustrated here are each L =4um, and W =4 um. It can be seen that the on-current of the P-type LTPS TFT is about 10 times that of the N-type IGZO TFT, so that the device size of the LTPS TFT is about 1/10 of the IGZO TFT under the same driving voltage to obtain the equivalent driving capability. The drive current of the LTPS TFT is more than 10 times of that of the IGZO TFT under the condition of equal W/L and drive voltage.

FIG. 16 is a schematic diagram illustrating a transient response of the three-dimensional integrated shift register cell circuit of FIG. 14 according to one embodiment of the present application.

In a gate driver circuit including shift register cells of successive stages, the gate driver circuit outputs signals of plural stages in correct logic in accordance with the activation of plural clock signals. Corresponding to the output of GN stage, in which stages (1) and (4) are low-level maintaining stages, the QN node is maintained at high level, and the output GN of the shift register unit of the present stage gate circuit is maintained at low level. In the phases (2) and (3), the QN node is at a low level, and the output terminal GN undergoes a pulse generation process from a low level to a high level; wherein (2) is a precharge phase and (3) is a scan continuation phase.

(1) Initial stage

The GN-1, GN, GN +1, etc. signals are all low, so T1a and T1b are turned on and the high level of VDD is transmitted to the gate node QN of transistor T2. The driving transistor T2 thus remains off. The transistor T7 is turned on, and the output GN is maintained at a low level potential. The remaining transistors are all in the off state.

(2) Pre-charge phase

GN-1 is high, and CLK1 and GN +1 are low. Therefore, T3 is turned on, and although T1a and T1b are still in conduction, T3 is selected to be larger in size and has stronger conduction capability, and the Q point is still pulled to be lower in potential. Therefore, the point Q is ready to be low voltage before CLK1 becomes high, which is ready for the later stage T2 to turn on.

(3) Pulse generation phase

CLK1 goes high and GN-1 goes low. Thus, T2 is turned on and the high level of CLK1 is transferred to the GN node. As GN goes high, T4 and T6' are turned on, and the drain voltages of pull-up structures T1a and T1b are pulled low. The QN point potential is then pulled to the low level VSS by the full amplitude. T2 remains on during the pulse generation phase, and its source-gate voltage remains at VGH-VSS. The voltage of GN can be pulled up to VGH faster.

(4) Low level hold phase

When the voltage at the QN point becomes low, the CLK1 takes a certain time to return to VDD, and therefore, a certain time is required to turn off the T2. When T2 has not been fully turned off, GN is partially pulled down by T2. After the potential at the point Q returns to VDD, T2 is turned off, and the second half GN is pulled down to VSS through T5.

In the later long low level maintaining stage, the signals of GN-1, GN +1, etc. are all low level voltages, so GN is maintained to be low level voltages, QN point is maintained to be high level voltages, the working state of each device of the gate driving unit circuit is basically the same as that in the initial stage, and will not be described again here.

The CMOS inverter is formed by the LTPS TFT and the IGZO TFT through a combined process, and the problems of high level loss on a driving transistor and competition of internal pull-up and pull-down paths in a grid driving circuit which can only be formed by N-type TFTs in the prior art are solved. Also, various embodiments better solving the above-described problems are provided by using both architectures of a single inverter and a double inverter.

Fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present application. The grid driving circuit comprises a shift register array formed by any one of the shift register unit circuits.

Display device 1700 includes a pixel array 1710, a data drive circuit 1720, and a gate drive circuit 1730. In particular, pixel array 1710 includes pixel devices arranged in rows and/or columns; the data driving circuit 1720 includes a plurality of data lines, and supplies data voltage information D to the pixel array 1710 through the plurality of data lines; the gate driving circuit 1730 is used to provide switching signals O < n > to the pixel array 1710 via a plurality of scan lines. Based on the above configuration, the gate driving circuit 1730 may sequentially turn on at least one row/column of the pixel array 1710 to enable the pixel array 1710 to read a data signal output by the data driving circuit 1720.

The application provides a three-dimensional integrated circuit, which comprises a first transistor, a second transistor, a first capacitor and a second capacitor, wherein the first transistor, the second transistor, the first capacitor and the second capacitor are positioned on a common substrate; the first transistor and the second transistor are manufactured by different processes, and a first electrode and a second electrode of the second transistor and a control electrode of the first transistor belong to a first metal layer; the lower pole plate of the first capacitor, the first electrode and the second electrode of the first transistor belong to a second metal layer, the upper pole plate of the first capacitor comprises the first electrode and the second electrode of the second transistor, and the gate oxide layer of the first transistor and the dielectric layer of the first capacitor belong to a first dielectric layer; the lower pole plate of the second capacitor comprises a control electrode of the first transistor, the upper pole plate of the second capacitor and the control electrode of the second transistor belong to a third metal layer, and the gate oxide layer of the second transistor and the dielectric layer of the second capacitor belong to a second dielectric layer.

In particular, the first transistor is a LTPS TFT, the active layer of which comprises polysilicon.

Specifically, the second transistor is an IGZO TFT, and an active layer thereof includes a metal oxide semiconductor.

In particular, the first electrode and the second electrode of the first transistor and/or the second transistor are made of different metal materials than the control electrode.

The application also provides a manufacturing method of the three-dimensional integrated circuit, which comprises the steps of forming a first metal layer on a substrate, and patterning the first metal layer to form a first electrode and a second electrode of a first transistor and a lower plate of a first capacitor; forming a first active layer on the substrate and the first metal layer, patterning the first active layer, and forming an active region of the first transistor between and over a first electrode and a second electrode of the first transistor; forming a first dielectric layer on the substrate, the first active layer and the lower plate of the first capacitor; forming a second metal layer on the first dielectric layer and patterning the second metal layer, forming a control electrode of the first transistor above the first dielectric layer between the first electrode and the second electrode of the first transistor, and forming a first electrode and a second electrode of the second transistor above the first capacitor; forming a second active layer on the second metal layer and the first dielectric layer, patterning the second active layer, and forming an active region of the second transistor between the first electrode and the second electrode and above the second electrode, wherein the second active layer is made of a different material than the first active layer; forming a second dielectric layer on the control electrode of the first transistor and on the first dielectric layer and the active region of the second transistor; and forming a third metal layer on the second dielectric layer, patterning the third metal layer, forming an upper electrode plate of a second capacitor above the control electrode of the first transistor, and forming a control electrode of the second transistor above the second dielectric layer between the first electrode and the second electrode of the second transistor.

In particular, the first active layer is LTPS.

In particular, the second active layer is IGZO.

The present application further provides a display comprising a pixel array, and gate and source driver circuits, wherein pixel cell circuits in the pixel array and the gate and source circuits comprise a three-dimensional integrated circuit as described in any of the preceding.

The present application further provides a photodetector comprising a detection array and a control circuit, wherein the pixel cell circuits in the detection array and the driving circuit comprise a three-dimensional integrated circuit as described in any of the foregoing.

The present application further provides a memory comprising a memory array and a control circuit, wherein the memory cell circuits in the memory array and the control circuit comprise the three-dimensional integrated circuit as described in any one of the preceding.

The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.

Claims

1. A shift register unit circuit comprises

A set transistor (Tst) with a control electrode configured to receive the output signal of the previous stage shift register unit circuit, and a second electrode coupled to a low level, wherein the set transistor is an N-type field effect transistor;

a reset transistor (Trst) with a control electrode configured to receive the output signal of the shift register unit circuit of the next stage and a second electrode coupled to a low level, wherein the reset transistor is an N-type field effect transistor;

a first CMOS inverter having an output coupled to the first pole of the set transistor, an input coupled to the output of the shift register cell circuit and the first pole of the reset transistor, a first control pole configured to receive a high level, and a second control pole coupled to a low level; and

a drive transistor (Td) having a first pole coupled to the output of the shift register cell circuit and to the first pole of the reset transistor, a second pole configured to receive a first clock signal (CLK 1), and a control pole coupled to the output of the first CMOS inverter and to the first pole of the set transistor;

the effective level of the first clock signal does not overlap with the effective level time period of the output signal of the previous stage shift register unit circuit and the effective level time period of the output signal of the next stage shift register unit circuit.

2. The circuit of claim 1, wherein the first CMOS inverter comprises

A first transistor (T1), a second pole of which is coupled to a high level, a first pole of which is coupled to the control pole of the driving transistor, a control pole of which is coupled to the first pole of the driving transistor and the output end of the shift register unit circuit of the present stage, the first transistor being a P-type field effect transistor;

a second transistor (T4), a first pole of which is coupled to the control pole of the driving transistor, a second pole of which is coupled to a low level, and a control pole of which is coupled to the output end of the present stage shift register unit circuit, wherein the second transistor is an N-type field effect transistor.

3. The circuit of claim 1, wherein the first CMOS inverter comprises

A second transistor (T4), a first pole of which is coupled to the control pole of the driving transistor, a second pole of which is coupled to a low level, and a control pole of which is coupled to the output end of the shift register unit circuit of the current stage, wherein the second transistor is an N-type field effect transistor;

a third transistor (T1 a), a second pole of which is coupled to a high level, a control pole of which is coupled to the first pole of the driving transistor and the output terminal of the shift register unit circuit of the present stage, the third transistor being a P-type field effect transistor;

a fourth transistor (T1 b), a second pole of which is coupled to the first pole of the third transistor, a first pole of which is coupled to the control pole of the driving transistor, a control pole of which is coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the fourth transistor being a P-type field effect transistor.

4. The circuit of claim 1, wherein the first CMOS inverter comprises

a fourth transistor (T1 b) having a second pole coupled to the first pole of the third transistor, a first pole coupled to the control pole of the driving transistor, and a control pole coupled to the first pole of the driving transistor and the output terminal of the present stage shift register unit circuit, the fourth transistor being a P-type field effect transistor;

and a fifth transistor (T6') having a first electrode coupled to the first electrode of the third transistor, a second electrode coupled to a low level, and a control electrode coupled to the output terminal of the shift register unit circuit of the present stage.

5. The circuit of claim 1, wherein the first CMOS inverter comprises

a third transistor (T1 a) having a second pole configured to receive a second clock signal (CLK 3) and a control pole coupled to the first pole of the driving transistor and the output terminal of the shift register unit circuit of the present stage, the third transistor being a P-type field effect transistor;

a fourth transistor (T1 b) having a second pole coupled to the first pole of the third transistor, a first pole coupled to the control pole of the drive transistor, and a control pole coupled to the first pole of the drive transistor, the fourth transistor being a P-type field effect transistor;

a sixth transistor (T6 '') having a first pole coupled to the first pole of the third transistor, a second pole coupled to a low level, and a control pole coupled to the output terminal of the present stage shift register unit circuit;

wherein there is no overlap between the high-level phase of the first clock signal and the high-level phase of the second clock signal.

6. The circuit of claim 1 or 4, further comprising

And the input end of the second CMOS inverter is coupled to the first pole of the set transistor, the output end of the second CMOS inverter is coupled to the output end of the shift register unit circuit of the current stage and the first pole of the reset transistor, the first control pole of the second CMOS inverter is configured to receive the first clock signal, and the second control pole of the second CMOS inverter is coupled to the low level.

7. The circuit of claim 6, wherein the second CMOS inverter comprises

The second pole of the driving transistor (T2) is configured to receive the first clock signal, the first pole of the driving transistor is coupled to the output end of the current stage shift register unit circuit, and the control pole of the driving transistor is coupled to the output end of the first CMOS inverter;

a seventh transistor (T7), a first pole of which is coupled to the output terminal of the present stage shift register unit circuit, a second pole of which is coupled to the low level, and a control pole of which is coupled to the control pole of the driving transistor, wherein the seventh transistor is an N-type field effect transistor.

8. The circuit of claim 7, wherein the N-type field effect transistor and the P-type field effect transistor are located on a common substrate; the first and/or second electrode of the N-type field effect transistor and the control electrode of the P-type field effect transistor belong to the same first metal layer.

9. The circuit of claim 8, wherein the N-type field effect transistor comprises an IGZO TFT, an active layer of which comprises a metal oxide semiconductor; the P-type field effect transistor comprises an LTPS TFT, the active layer of which comprises polysilicon.

10. A gate driver circuit comprising the shift register cell circuit as claimed in any one of claims 1 to 9.

11. A display comprising an array of pixels, a data driving circuit, and a gate driving circuit as claimed in claim 10.