CN102708777A - Shift register unit and gate drive device - Google Patents
Shift register unit and gate drive device Download PDFInfo
- Publication number
- CN102708777A CN102708777A CN2011103818615A CN201110381861A CN102708777A CN 102708777 A CN102708777 A CN 102708777A CN 2011103818615 A CN2011103818615 A CN 2011103818615A CN 201110381861 A CN201110381861 A CN 201110381861A CN 102708777 A CN102708777 A CN 102708777A
- Authority
- CN
- China
- Prior art keywords
- input end
- signal input
- film transistor
- shift register
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a shift register unit and a gate drive device. The shift register unit comprises a latch and a control circuit, wherein the control circuit comprises a first thin film transistor, a second thin film transistor and a third thin film transistor; the gate of the first thin film transistor is connected with a clock signal input end; the source of the first thin film transistor is connected with a signal input end; the drain of the first thin film transistor is connected with the input end of the latch; the gate of the second thin film transistor is connected with the clock signal input end; the source of the second thin film transistor is connected with a first signal output end; the gate of the third thin film transistor is connected with the signal input end; the source of the third thin film transistor is connected with a high-level signal input end; the drain of the third thin film transistor is connected with the drain of the second thin film transistor; the latch comprises a first phase inverter and a second phase inverter which are connected with each other end to end; the input end of the latch is connected with a second signal output end; the output end of the latch is connected with the first signal output end; and the levels of output signals of the first signal output end and the second signal output end are opposite. According to the shift register unit, the circuit is simple in structure, a small number of signal wires are arranged, the power consumption is low, and the area of a layout is small.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of shift register cell and gate drive apparatus.
Background technology
The gate drive apparatus of display is used to grid line drive signal is provided; The shift register cell that comprises a plurality of cascades in the gate drive apparatus; Be illustrated in figure 1 as a structural representation of shift register cell of the prior art, this shift register cell comprises: 2 latchs 101 and 4 transmission gates 102, one of them latch 101 are used for programming; Another latch 101 is used for latch output signal, and transmission gate 102 is used for control lock storage 101 programming or latch output signals.As can be seen from Figure 1, each latch 101 is formed (the Reset signal of the Reset of Sheffer stroke gate (resetting) signal input part input is a high level among the figure, thereby this Sheffer stroke gate also is equivalent to a phase inverter) by two phase inverters.CLK is a clock signal among the figure, and the D node is the input node of latch, and the Q node is the reverse output node of latch.
As can be seen from Figure 1, existing shift register cell needs two latchs, and its transistor that adopts is more, thereby makes shift register cell can produce bigger power consumption.
Summary of the invention
In view of this; The present invention provides a kind of shift register cell and gate drive apparatus; Circuit structure is simple, signal routing is few, makes the power consumption of whole shift register cell reduce, and the gate drive apparatus area occupied of its cascade structure formation is few simultaneously; Can further reduce the taking of the display area of display panel, thereby realize the high-res and the narrow frameization of display device.
For addressing the above problem, the present invention provides a kind of shift register cell, comprising:
Latch and control circuit;
Said control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with signal input part, and drain electrode is connected with the input end of said latch;
Second thin film transistor (TFT), its grid is connected with said clock signal input terminal, and source electrode is connected with first signal output part;
The 3rd thin film transistor (TFT), its grid is connected with said signal input part, and source electrode is connected with said high level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT);
Said latch comprises: end to end first phase inverter and second phase inverter, and the input end of said latch is connected with said the first film transistor drain and secondary signal output terminal, and output terminal is connected with said first signal output part;
Wherein, the output signal level of said first signal output part and said secondary signal output terminal is opposite.
Optional, said shift register cell also comprises:
The 4th thin film transistor (TFT), its grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT).
Optional, said first phase inverter comprises:
The 5th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the input end of said latch;
The 6th thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 7th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the output terminal of said latch;
The 8th thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
Optional, said first phase inverter comprises:
The 9th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The tenth thin film transistor (TFT), its grid is connected with the source electrode of said the 9th thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the input end of said latch;
The 11 thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 12 thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The 13 thin film transistor (TFT), its grid is connected with the source electrode of said the 12 thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the output terminal of said latch;
The 14 thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
The present invention also provides a kind of gate drive apparatus, comprising: be deposited on a plurality of above-mentioned shift register cell on the array base palte, wherein,
Except that first shift register cell, the signal input part of all the other shift register cells is connected with the secondary signal output terminal of an adjacent last shift register cell;
The signal input part of first shift register cell is connected with the frame start signal input end;
Except that last shift register cell, the secondary signal output terminal of all the other shift register cells is connected with the signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with first clock cable, and the clock signal input terminal of even number shift register cell is connected with the second clock signal wire;
The high level signal input end of each shift register cell is connected with the high level signal line, and the low level signal input end is connected with the low level signal line;
The level of the clock signal of said first clock cable and the output of said second clock signal wire is opposite.
Optional, except that last shift register cell, the reset signal input end of all the other shift register cells is connected with first signal output part of adjacent next shift register cell; The reset signal input end of last shift register cell is connected with said frame start signal input end.
The present invention also provides a kind of shift register cell, comprising:
Latch and control circuit;
Said control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with first signal input part, and drain electrode is connected with the input end of said latch;
Second thin film transistor (TFT), its grid is connected with said clock signal input terminal, and source electrode is connected with said first signal output part;
The 3rd thin film transistor (TFT), its grid is connected with the secondary signal input end, and drain electrode is connected with said high level signal input end, and source electrode is connected with the drain electrode of said second thin film transistor (TFT);
Said latch comprises: end to end first phase inverter and second phase inverter, and the input end of said latch is connected with said the first film transistor drain and secondary signal output terminal, and output terminal is connected with said first signal output part;
Wherein, the level of the input signal of said first signal input part and said secondary signal input end is opposite, and the output signal level of said first signal output part and said secondary signal output terminal is opposite.
Optional, said shift register cell also comprises:
The 4th thin film transistor (TFT), its grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT).
Optional, said first phase inverter comprises:
The 5th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the input end of said latch;
The 6th thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 7th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the output terminal of said latch;
The 8th thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
Optional, said first phase inverter comprises:
The 9th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The tenth thin film transistor (TFT), its grid is connected with the source electrode of said the 9th thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the input end of said latch;
The 11 thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 12 thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The 13 thin film transistor (TFT), its grid is connected with the source electrode of said the 12 thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the output terminal of said latch;
The 14 thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
Also a kind of gate drive apparatus of the present invention is deposited on a plurality of above-mentioned shift register cell on the array base palte, wherein,
Except that first shift register cell; First signal input part of all the other shift register cells is connected with the secondary signal output terminal of an adjacent last shift register cell, and the secondary signal input end is connected with first signal output part of an adjacent last shift register cell;
First signal input part of first shift register cell is connected with the first frame start signal input end, and the secondary signal input end is connected with the second frame start signal input end;
Except that last shift register cell; First signal output part of all the other shift register cells is connected with the secondary signal input end of adjacent next shift register cell, and the secondary signal output terminal is connected with first signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with first clock cable, and the clock signal input terminal of even number shift register cell is connected with the second clock signal wire;
The high level signal input end of each shift register cell is connected with the high level signal line, and the low level signal input end is connected with the low level signal line;
The level of the clock signal of said first clock cable and the output of said second clock signal wire is opposite, and the level of the input signal of said first frame start signal input end and the said second frame start signal input end is opposite.
Optional, except that last shift register cell, the reset signal input end of all the other shift register cells is connected with first signal output part of adjacent next shift register cell; The reset signal input end of last shift register cell is connected with the said first frame start signal input end.
The present invention has following beneficial effect:
Only adopt a latch in the shift register cell; Circuit structure is simple, signal routing is few; Make the power consumption of whole shift register cell reduce; Simultaneously the gate drive apparatus area occupied that forms of its cascade structure is few, can further reduce the taking of the display area of display panel, thereby realize the high-res and the narrow frameization of display device.
Description of drawings
Fig. 1 is a structural representation of shift register cell of the prior art;
Fig. 2 is the structural representation of the shift register cell of the embodiment of the invention one;
Fig. 3 is the structural representation of the gate drive apparatus of the embodiment of the invention one;
Fig. 4 is the working timing figure of the shift register cell of the embodiment of the invention;
Fig. 5 is the structural representation of the shift register cell of the embodiment of the invention two;
Fig. 6 is the structural representation of the gate drive apparatus of the embodiment of the invention two;
Fig. 7 is the structural representation of the shift register cell of the embodiment of the invention three;
Fig. 8 is the structural representation of the gate drive apparatus of the embodiment of the invention three;
Fig. 9 is the structural representation of the shift register cell of the embodiment of the invention four;
Figure 10 is the structural representation of the gate drive apparatus of the embodiment of the invention four;
Figure 11 is a structural representation of the latch of the embodiment of the invention;
Figure 12 is another structural representation of the latch of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.
Be illustrated in figure 2 as the structural representation of the shift register cell of the embodiment of the invention one, this shift register cell comprises: latch 201 and control circuit.Explanation for ease, in following examples, the P node in all will scheming is as the input end of latch 201, and the Q node is as the output terminal of latch.
Wherein, Control circuit is used for control lock storage 201 programming or latch output signals; Comprise: the first film transistor T 1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3; In the present embodiment, the first film transistor T 1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are nmos pass transistor.
The grid of the first film transistor T 1 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal input part Input1, and drain electrode is connected with the input end P of latch 201.
Because the input signal of the first signal input part Input1 possibly be a high level, also possibly be low level, thereby the source electrode of the first film transistor T 1 can exchange with drain electrode.When the input signal of the first signal input part Input1 was high level, what be connected with the first signal input part Input1 was the drain electrode of the first film transistor T 1, and what be connected with the input end P of latch 201 is the source electrode of the first film transistor T 1.When the input signal of the first signal input part Input1 was low level, what be connected with the first signal input part Input1 was the source electrode of the first film transistor T 1, and what be connected with the input end P of latch 201 is the drain electrode of the first film transistor T 1.
The grid of the second thin film transistor (TFT) T2 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal output part Output_Q, and drain electrode is connected with the source electrode of the 3rd thin film transistor (TFT) T3.
The grid of the 3rd thin film transistor (TFT) T3 is connected with secondary signal input end Input2, and drain electrode is connected with high level signal input end VDD, and source electrode is connected with the drain electrode of the second thin film transistor (TFT) T2.
In the present embodiment, the level of the input signal of the first signal input part Input1 and secondary signal input end Input2 is opposite, and the output signal level of the first signal output part Output_Q and secondary signal output terminal Output_QB is opposite.
In the foregoing description, be to be that nmos pass transistor is that example describes simultaneously with the first film transistor T 1 and the second thin film transistor (TFT) T2, the first film transistor T 1 and the second thin film transistor (TFT) T2 can be the PMOS transistor simultaneously also certainly.
Be illustrated in figure 3 as the structural representation of the gate drive apparatus of the embodiment of the invention one, this gate drive apparatus comprises: be deposited on the shift register cell of a plurality of cascades on the array base palte, the structure of shift register cell please refer to Fig. 2.The output signal of Output_Q among Fig. 3 (n) sign n level shift register cell.
Be elaborated in the face of the annexation between each parts of the gate drive apparatus among Fig. 3 down:
Except that first shift register cell; The first signal input part Input1 of all the other shift register cells is connected with the secondary signal output terminal Output_QB of an adjacent last shift register cell, and secondary signal input end Input2 is connected with the first signal output part Output_Q of an adjacent last shift register cell;
The first signal input part Input1 of first shift register cell is connected with the first frame start signal input end STV, and secondary signal input end Input2 is connected with the second frame start signal input end STV_B;
Except that last shift register cell; The first signal output part Output_Q of all the other shift register cells is connected with the secondary signal input end Input2 of adjacent next shift register cell, and secondary signal output terminal Output_QB is connected with the first signal input part Input1 of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock signal wire 302;
The high level signal input end VDD of each shift register cell is connected with high level signal line 303.
In the present embodiment; First clock cable 301 is opposite with the level of the clock signal (CLK and CLKB) of second clock signal wire 302 outputs, and the level of the input signal of the first frame start signal input end 304 and the second frame start signal input end 305 (STV and STV_B) is opposite.
Can find out from the foregoing description; Only adopt a latch in the shift register cell; Circuit structure is simple, signal routing is few, makes the power consumption of whole shift register cell reduce, and the gate drive apparatus area occupied of its cascade structure formation is few simultaneously; Can further reduce the taking of the display area of display panel, thereby realize the high-res and the narrow frameization of display device.
Being illustrated in figure 4 as the working timing figure of the shift register cell of the embodiment of the invention, is example with n shift register cell, and the course of work of shift register cell among Fig. 3 is described.
The course of work of the shift register cell among Fig. 3 mainly comprised with the next stage:
The 1st stage: the output signal Output_Q (n-1) of upper level shift register cell (i.e. n-1 shift register cell) becomes high level by low level; Promptly the input signal Input2 of n shift register cell is a high level; At this moment; CLK is a low level, and the first film transistor T 1, the second thin film transistor (TFT) T2 turn-off, and the output Output_Q (n) of latch remains low level.
The 2nd stage: the output signal Output_Q (n-1) of upper level shift register cell still is a high level, and promptly the input signal Input2 of n shift register cell is a high level, and CLK becomes high level by low level; Then the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 conducting, input signal Input1 is a low level, at this moment; The input end P of latch is pulled down to low level; Output_QB (n) also is a low level, and simultaneously, the output terminal Q of latch (being Output_Q) is pulled to high level; That is to say that latch is programmed to export high level.
The 3rd stage: the output signal Output_Q (n-1) of upper level shift register cell becomes low level; Promptly the input signal Input2 of n shift register cell is a low level; And CLK becomes low level by high level, and the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 all end, and then the output of the high level of latch is latched and kept; Be that Output_Q (n) is maintained high level, Output_QB (n) is maintained low level.
The 4th stage: the input signal Input2 of n level shift register cell becomes low level; The 3rd thin film transistor (TFT) T3 ends, and CLK becomes high level, 1 conducting of the first film transistor T; The reverse output signal Output_QB (n-1) of upper level shift register cell is a high level simultaneously; Promptly the input signal Input1 of n level shift register cell is a high level, and then the input end P of latch is pulled to high level, and output terminal Q (being Output_Q (n)) is pulled down to low level; That is to say that latch is programmed to output low level.
The 5th stage: the reverse output signal Output_QB (n-1) of upper level shift register cell is always high level; Promptly to be always low electric Input2 flat for the input signal of n shift register cell; Input1 is always high level, and the 3rd thin film transistor (TFT) T3 ends all the time; The first film transistor T 1, the second thin film transistor (TFT) T2 is in the conducting of following cycle of CLK signal, and wherein when 1 conducting of the first film transistor T, the input end P of latch is pulled to high level by Input1, and output terminal Q (being Output_Q (n)) is a low level; When the first film transistor T 1 ended, the output terminal Q of latch (being Output_Q (n)) kept low level.Promptly this stage is output terminal Q (being Output_Q (n)) the output low level maintenance stage of latch.
Because after the 5th stage; The Input2 signal is always low level; That is to say that the 3rd thin film transistor (TFT) T3 is in closed condition always, and CLK can make the continuous switch of the second thin film transistor (TFT) T2; If be in noble potential between the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, then can influence the output of latch.
For fear of the problems referred to above; Be illustrated in figure 5 as the structural representation of the shift register cell of the embodiment of the invention two, on the basis of shift register cell shown in Figure 2, can also in control circuit, increase by one the 4th thin film transistor (TFT) T4; Wherein, The grid of the 4th thin film transistor (TFT) T4 is connected with reset signal input end Reset, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the second thin film transistor (TFT) T2.
Different with the shift register cell among Fig. 2 is that in the present embodiment, the source electrode of the second thin film transistor (TFT) T2 can exchange with drain electrode.When the second thin film transistor (TFT) T2 and the equal conducting of the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 by the time; The end that the second thin film transistor (TFT) T2 is connected with the first signal output part Output_Q is a source electrode; An end that is connected with the 3rd thin film transistor (TFT) T3 is drain electrode; When the second thin film transistor (TFT) T2 and the equal conducting of the 4th thin film transistor (TFT) T4, the 3rd thin film transistor (TFT) T3 by the time; The end that the second thin film transistor (TFT) T2 is connected with the first signal output part Output_Q is drain electrode, and an end that is connected with the 4th thin film transistor (TFT) T4 is a source electrode.
Be illustrated in figure 6 as the structural representation of the gate drive apparatus of the embodiment of the invention two, this gate drive apparatus comprises: be deposited on the shift register cell of a plurality of cascades on the array base palte, the structure of this shift register cell please refer to Fig. 5.
Be elaborated in the face of the annexation between each parts of the gate drive apparatus among Fig. 6 down:
Except that first shift register cell; The first signal input part Input1 of all the other shift register cells is connected with the secondary signal output terminal Output_QB of an adjacent last shift register cell, and secondary signal input end Input2 is connected with the first signal output part Output_Q of an adjacent last shift register cell;
The first signal input part Input1 of first shift register cell is connected with the first frame start signal input end STV, and secondary signal input end Input2 is connected with the second frame start signal input end STV_B;
Except that last shift register cell; The first signal output part Output_Q of all the other shift register cells is connected with the secondary signal input end Input2 of adjacent next shift register cell, and secondary signal output terminal Output_QB is connected with the first signal input part Input1 of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock signal wire 302;
The high level signal input end VDD of each shift register cell is connected with high level signal line 303, and low level signal input end VSS is connected with low level signal line 304;
Except that last shift register cell, the reset signal input end Reset of all the other shift register cells is connected with the first signal output part Output_Q of adjacent next shift register cell;
The reset signal input end Reset of last shift register cell is connected with the first frame start signal input end STV.
In the present embodiment; First clock cable 301 is opposite with the level of the clock signal (CLK and CLKB) of second clock signal wire 302 outputs, and the level of the input signal of the first frame start signal input end 304 and the second frame start signal input end 305 (STV and STV_B) is opposite.
The course of work in the face of the shift register cell among Fig. 6 is elaborated down, and is same, is example with n shift register cell still, and its work schedule is as shown in Figure 4.
The course of work of shift register cell mainly comprised with the next stage among Fig. 6:
The 1st stage: the output signal Output_Q (n-1) of upper level shift register cell (i.e. n-1 shift register cell) becomes high level by low level; Promptly the input signal Input2 of n shift register cell is a high level; At this moment; CLK is a low level, and the first film transistor T 1, the second thin film transistor (TFT) T2 turn-off, and the output Output_Q (n) of latch remains low level.
The 2nd stage: the output signal Output_Q (n-1) of upper level shift register cell still is a high level; Promptly the input signal Input2 of n shift register cell is a high level; CLK becomes high level by low level; Then the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 conducting, Reset signal (being the reverse output signal Output_QB (n+1) of next stage shift register cell) is a low level, the 4th thin film transistor (TFT) T4 ends; Input signal Input1 is a low level, and at this moment, the input end P of latch is pulled down to low level; Output_QB (n) also is a low level, and simultaneously, the output terminal Q of latch (being Output_Q) is pulled to high level; That is to say that latch is programmed to export high level.
The 3rd stage: the output signal Output_Q (n-1) of upper level shift register cell becomes low level; Promptly the input signal Input2 of n shift register cell is a low level; And CLK becomes low level by high level, and the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 all end, and then the output of the high level of latch is latched and kept; Be that Output_Q (n) is maintained high level, Output_QB (n) is maintained low level.And this moment, under CLKB signal, Output_Q (n) and Output_QB (n) signal, the next stage shift register cell got into for the 2nd stage, and its output Output_Q (n+1) becomes high level, oppositely exports Output_QB (n+1) and becomes low level.
The 4th stage: the input signal Input2 of n level shift register cell becomes low level, and the 3rd thin film transistor (TFT) T3 ends, and CLK becomes high level; 1 conducting of the first film transistor T, the output Output_Q (n+1) of next stage shift register cell is a high level, then the 4th thin film transistor (TFT) T4 conducting; The reverse output signal Output_QB (n-1) of upper level shift register cell is a high level simultaneously; Promptly the input signal Input1 of n level shift register cell is a high level, and then the input end P of latch is pulled to high level, and output terminal Q (being Output_Q (n)) is pulled down to low level; That is to say that latch is programmed to output low level.
The 5th stage: the reverse output signal Output_QB (n-1) of upper level shift register cell is always high level; Promptly the input signal Input2 of n shift register cell is always low level; Input1 is always high level, and the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 end all the time; The first film transistor T 1, the second thin film transistor (TFT) T2 is in the conducting of following cycle of CLK signal, and wherein when 1 conducting of the first film transistor T, the input end P of latch is pulled to high level by Input1, and output terminal Q (being Output_Q (n)) is a low level; When the first film transistor T 1 ended, the output terminal Q of latch (being Output_Q (n)) kept low level.Promptly this stage is output terminal Q (being Output_Q (n)) the output low level maintenance stage of latch.
In the foregoing description, shift register cell has two signal input parts (the first signal input part Input1 and secondary signal input end Input2), can certainly only adopt a signal input part.
Be illustrated in figure 7 as the structural representation of the shift register cell of the embodiment of the invention three, this shift register cell comprises: latch 201 and control circuit.
Wherein, Control circuit is used for control lock storage 201 programming or latch output signals; Comprise: the first film transistor T 1, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3; In the present embodiment, the first film transistor T 1 and the second thin film transistor (TFT) T2 are nmos pass transistor simultaneously, and the 3rd thin film transistor (TFT) T3 is the PMOS transistor.
The grid of the first film transistor T 1 is connected with clock signal input terminal CLK, and source electrode is connected with signal input part Input, and drain electrode is connected with the input end P of latch 201.
Because the input signal Input of signal input part Input possibly be a high level, also possibly be low level, thereby the source electrode of the first film transistor T 1 can exchange with drain electrode.When the Input signal was high level, what be connected with signal input part Input was the drain electrode of the first film transistor T 1, and what be connected with the input end P of latch 201 is the source electrode of the first film transistor T 1; When the Input signal was low level, what be connected with signal input part Input was the source electrode of the first film transistor T 1, and what be connected with the input end P of latch 201 is the drain electrode of the first film transistor T 1.
The grid of the second thin film transistor (TFT) T2 is connected with clock signal input terminal CLK, and source electrode is connected with the first signal output part Output_Q, and drain electrode is connected with the drain electrode of the 3rd thin film transistor (TFT) T3.
The grid of the 3rd thin film transistor (TFT) T3 is connected with signal input part Input, and source electrode is connected with high level signal input end VDD, and drain electrode is connected with the drain electrode of the second thin film transistor (TFT) T2;
In the present embodiment, the level of the output signal (Output_Q and Output_QB) of the first signal output part Output_Q and secondary signal output terminal Output_QB is opposite.
In the foregoing description, be to be that nmos pass transistor is that example describes simultaneously with the first film transistor T 1 and the second thin film transistor (TFT) T2, the first film transistor T 1 and the second thin film transistor (TFT) T2 can be the PMOS transistor simultaneously also certainly.
Be illustrated in figure 8 as the structural representation of the gate drive apparatus of the embodiment of the invention three, this gate drive apparatus comprises: be deposited on the shift register cell of a plurality of cascades on the array base palte, the structure of this shift register cell please refer to Fig. 7.
Be elaborated in the face of the annexation between each parts of the gate drive apparatus among Fig. 8 down:
Except that first shift register cell, the signal input part Input of all the other shift register cells is connected with the secondary signal output terminal Output_QB of an adjacent last shift register cell;
The signal input part Input of first shift register cell is connected with frame start signal input end STV;
Except that last shift register cell, the secondary signal output terminal Output_QB of all the other shift register cells is connected with the signal input part Input of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock signal wire 302;
The high level signal input end VDD of each shift register cell is connected with high level signal line 303.
In the present embodiment, first clock cable 301 is opposite with the level of the clock signal (CLK and CLKB) of second clock signal wire 302 outputs.
Be illustrated in figure 9 as the structural representation of the shift register cell of the embodiment of the invention four; On the basis of embodiment shown in Figure 7; In control circuit, increase by one the 4th thin film transistor (TFT) T4; The grid of the 4th thin film transistor (TFT) T4 is connected with reset signal input end Reset, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the drain electrode of the second thin film transistor (TFT) T2.
Shift register cell among Fig. 7 and Fig. 9 has removed the sequential of an input signal, and the 3rd thin film transistor (TFT) T3 adopts PMOS pipe transmission VDD also not have loss simultaneously.
Shown in figure 10 is the structural representation of the gate drive apparatus of the embodiment of the invention four, and this gate drive apparatus comprises: be deposited on the shift register cell of a plurality of cascades on the array base palte, the structure of this shift register cell please refer to Fig. 9.
Be elaborated in the face of the annexation between each parts of the gate drive apparatus among Figure 10 down:
Except that first shift register cell, the signal input part Input of all the other shift register cells is connected with the secondary signal output terminal Output_QB of an adjacent last shift register cell;
The signal input part Input of first shift register cell is connected with frame start signal input end STV;
Except that last shift register cell, the secondary signal output terminal Output_QB of all the other shift register cells is connected with the signal input part Input of adjacent next shift register cell;
The clock signal input terminal CLK of odd number shift register cell is connected with first clock cable 301, and the clock signal input terminal CLK of even number shift register cell is connected with second clock signal wire 302;
The high level signal input end VDD of each shift register cell is connected with high level signal line 303, and low level signal input end VSS is connected with low level signal line 304;
Except that last shift register cell, the reset signal input end Reset of all the other shift register cells is connected with the first signal output part Output_Q of adjacent next shift register cell;
The reset signal input end Reset of last shift register cell is connected with frame start signal input end STV.
In the present embodiment, first clock cable 301 is opposite with the level of the clock signal (CLK and CLKB) of second clock signal wire 302 outputs.
First phase inverter in the latch in the foregoing description and second phase inverter can describe for multiple structure below for example.
Shown in figure 11 is a structural representation of latch of the present invention; Wherein, First phase inverter 2011 and second phase inverter 2012 are made up of two thin film transistor (TFT)s respectively; First phase inverter 2011 comprises the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6, and second phase inverter 2012 comprises the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8.In the present embodiment, the 5th thin film transistor (TFT) T5 to the eight thin film transistor (TFT) T8 are the NMOS pipe.
The grid of the 5th thin film transistor (TFT) T5 all is connected with high level signal input end VDD with drain electrode, and source electrode is connected with the input end P of latch;
The grid of the 6th thin film transistor (TFT) T6 is connected with the output terminal Q of latch, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the input end P of latch;
The grid of the 7th thin film transistor (TFT) T7 all is connected with high level signal input end VDD with drain electrode, and source electrode is connected with the output terminal Q of latch;
The grid of the 8th thin film transistor (TFT) T8 is connected with the input end P of latch, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the output terminal Q of latch.
Shown in figure 12 is another structural representation of latch of the present invention; Wherein, First phase inverter 2011 and second phase inverter 2012 are made up of three thin film transistor (TFT)s respectively; First phase inverter 2011 comprises: the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11 thin film transistor (TFT) T11, second phase inverter 2012 comprises: the 12 thin film transistor (TFT) T12, the 13 thin film transistor (TFT) T13 and the 14 thin film transistor (TFT) T14.In the present embodiment, the 9th thin film transistor (TFT) T9 to the 14 thin film transistor (TFT) T14 are the NMOS pipe.
The grid of the 9th thin film transistor (TFT) T9 all is connected with high level signal input end VDD with drain electrode, and source electrode is connected with the grid of said the tenth thin film transistor (TFT) T10;
The grid of the tenth thin film transistor (TFT) T10 is connected with the source electrode of the 9th thin film transistor (TFT) T9, and drain electrode is connected with high level signal input end VDD, and source electrode is connected with the input end P of latch;
The grid of the 11 thin film transistor (TFT) T11 is connected with the output terminal Q of latch, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the input end P of latch;
The grid of the 12 thin film transistor (TFT) T12 all is connected with high level signal input end VDD with drain electrode, and source electrode is connected with the grid of the 13 thin film transistor (TFT) T13;
The grid of the 13 thin film transistor (TFT) T13 is connected with the source electrode of the 12 thin film transistor (TFT) T12, and drain electrode is connected with high level signal input end VDD, and source electrode is connected with the output terminal Q of latch;
The grid of the 14 thin film transistor (TFT) T14 is connected with the input end P of latch, and source electrode is connected with low level signal input end VSS, and drain electrode is connected with the output terminal Q of latch.
In the foregoing description, first phase inverter 2011 and second phase inverter 2012 all are to be made up of the NMOS pipe, certainly, also can be made up of PMOS pipe or CMOS pipe.
Embodiments of the invention also provide a kind of array base palte, comprise the gate drive apparatus in the foregoing description.
In addition, embodiments of the invention also provide a kind of display panel, comprise above-mentioned array base palte.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (12)
1. a shift register cell is characterized in that, comprising:
Latch and control circuit;
Said control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with signal input part, and drain electrode is connected with the input end of said latch;
Second thin film transistor (TFT), its grid is connected with said clock signal input terminal, and source electrode is connected with first signal output part;
The 3rd thin film transistor (TFT), its grid is connected with said signal input part, and source electrode is connected with said high level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT);
Said latch comprises: end to end first phase inverter and second phase inverter, and the input end of said latch is connected with said the first film transistor drain and secondary signal output terminal, and output terminal is connected with said first signal output part;
Wherein, the output signal level of said first signal output part and said secondary signal output terminal is opposite.
2. shift register cell as claimed in claim 1 is characterized in that, also comprises:
The 4th thin film transistor (TFT), its grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT).
3. shift register cell as claimed in claim 1 is characterized in that:
Said first phase inverter comprises:
The 5th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the input end of said latch;
The 6th thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 7th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the output terminal of said latch;
The 8th thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
4. shift register cell as claimed in claim 1 is characterized in that:
Said first phase inverter comprises:
The 9th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The tenth thin film transistor (TFT), its grid is connected with the source electrode of said the 9th thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the input end of said latch;
The 11 thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 12 thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The 13 thin film transistor (TFT), its grid is connected with the source electrode of said the 12 thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the output terminal of said latch;
The 14 thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
5. a shift register cell is characterized in that, comprising:
Latch and control circuit;
Said control circuit comprises:
The first film transistor, its grid is connected with clock signal input terminal, and source electrode is connected with first signal input part, and drain electrode is connected with the input end of said latch;
Second thin film transistor (TFT), its grid is connected with said clock signal input terminal, and source electrode is connected with said first signal output part;
The 3rd thin film transistor (TFT), its grid is connected with the secondary signal input end, and drain electrode is connected with said high level signal input end, and source electrode is connected with the drain electrode of said second thin film transistor (TFT);
Said latch comprises: end to end first phase inverter and second phase inverter, and the input end of said latch is connected with said the first film transistor drain and secondary signal output terminal, and output terminal is connected with said first signal output part;
Wherein, the level of the input signal of said first signal input part and said secondary signal input end is opposite, and the output signal level of said first signal output part and said secondary signal output terminal is opposite.
6. shift register cell as claimed in claim 5 is characterized in that, also comprises:
The 4th thin film transistor (TFT), its grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end, and drain electrode is connected with the drain electrode of said second thin film transistor (TFT).
7. shift register cell as claimed in claim 5 is characterized in that:
Said first phase inverter comprises:
The 5th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the input end of said latch;
The 6th thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 7th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode, and source electrode is connected with the output terminal of said latch;
The 8th thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
8. shift register cell as claimed in claim 5 is characterized in that:
Said first phase inverter comprises:
The 9th thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The tenth thin film transistor (TFT), its grid is connected with the source electrode of said the 9th thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the input end of said latch;
The 11 thin film transistor (TFT), its grid is connected with the output terminal of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the input end of said latch;
Said second phase inverter comprises:
The 12 thin film transistor (TFT), its grid all is connected with said high level signal input end with drain electrode;
The 13 thin film transistor (TFT), its grid is connected with the source electrode of said the 12 thin film transistor (TFT), and drain electrode is connected with said high level signal input end, and source electrode is connected with the output terminal of said latch;
The 14 thin film transistor (TFT), its grid is connected with the input end of said latch, and source electrode is connected with the low level signal input end, and drain electrode is connected with the output terminal of said latch.
9. a gate drive apparatus is characterized in that, comprising: be deposited on a plurality of on the array base palte like each described shift register cell of claim 1-4, wherein,
Except that first shift register cell, the signal input part of all the other shift register cells is connected with the secondary signal output terminal of an adjacent last shift register cell;
The signal input part of first shift register cell is connected with the frame start signal input end;
Except that last shift register cell, the secondary signal output terminal of all the other shift register cells is connected with the signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with first clock cable, and the clock signal input terminal of even number shift register cell is connected with the second clock signal wire;
The high level signal input end of each shift register cell is connected with the high level signal line, and the low level signal input end is connected with the low level signal line;
The level of the clock signal of said first clock cable and the output of said second clock signal wire is opposite.
10. gate drive apparatus as claimed in claim 9 is characterized in that:
Except that last shift register cell, the reset signal input end of all the other shift register cells is connected with first signal output part of adjacent next shift register cell;
The reset signal input end of last shift register cell is connected with said frame start signal input end.
11. a gate drive apparatus is characterized in that, is deposited on a plurality of like each described shift register cell of claim 5-8 on the array base palte, wherein,
Except that first shift register cell; First signal input part of all the other shift register cells is connected with the secondary signal output terminal of an adjacent last shift register cell, and the secondary signal input end is connected with first signal output part of an adjacent last shift register cell;
First signal input part of first shift register cell is connected with the first frame start signal input end, and the secondary signal input end is connected with the second frame start signal input end;
Except that last shift register cell; First signal output part of all the other shift register cells is connected with the secondary signal input end of adjacent next shift register cell, and the secondary signal output terminal is connected with first signal input part of adjacent next shift register cell;
The clock signal input terminal of odd number shift register cell is connected with first clock cable, and the clock signal input terminal of even number shift register cell is connected with the second clock signal wire;
The high level signal input end of each shift register cell is connected with the high level signal line, and the low level signal input end is connected with the low level signal line;
The level of the clock signal of said first clock cable and the output of said second clock signal wire is opposite, and the level of the input signal of said first frame start signal input end and the said second frame start signal input end is opposite.
12. gate drive apparatus as claimed in claim 11 is characterized in that: except that last shift register cell, the reset signal input end of all the other shift register cells is connected with first signal output part of adjacent next shift register cell;
The reset signal input end of last shift register cell is connected with the said first frame start signal input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110381861.5A CN102708777B (en) | 2011-11-25 | 2011-11-25 | Shift register unit and gate drive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110381861.5A CN102708777B (en) | 2011-11-25 | 2011-11-25 | Shift register unit and gate drive device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102708777A true CN102708777A (en) | 2012-10-03 |
| CN102708777B CN102708777B (en) | 2015-03-25 |
Family
ID=46901486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110381861.5A Active CN102708777B (en) | 2011-11-25 | 2011-11-25 | Shift register unit and gate drive device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102708777B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956214A (en) * | 2012-11-19 | 2013-03-06 | 京东方科技集团股份有限公司 | Common electrode driving unit, liquid crystal display panel and liquid crystal display device |
| WO2014153813A1 (en) * | 2013-03-29 | 2014-10-02 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, grid driving apparatus and display apparatus |
| WO2014205897A1 (en) * | 2013-06-26 | 2014-12-31 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, and display device |
| CN104361875A (en) * | 2014-12-02 | 2015-02-18 | 京东方科技集团股份有限公司 | Shifting register unit as well as driving method, grid driving circuit and display device |
| CN108122529A (en) * | 2018-01-25 | 2018-06-05 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method and gate driving circuit |
| WO2020207217A1 (en) * | 2019-04-09 | 2020-10-15 | 京东方科技集团股份有限公司 | Gate driver unit, gate drive method, gate driver circuit, and display device |
| CN112542140A (en) * | 2020-12-16 | 2021-03-23 | 合肥京东方卓印科技有限公司 | Shift register, gate drive circuit and drive method |
| CN113409717A (en) * | 2021-05-13 | 2021-09-17 | 北京大学深圳研究生院 | Shift register unit circuit, gate drive circuit and display |
| CN113808653A (en) * | 2021-09-07 | 2021-12-17 | 深圳知微创新技术有限公司 | Shift register unit circuit and shift register |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681047A (en) * | 2004-02-06 | 2005-10-12 | 三星电子株式会社 | Shift register and display device therewith |
| KR20060097819A (en) * | 2005-03-07 | 2006-09-18 | 삼성전자주식회사 | Shift register and display device having the same |
| WO2010146753A1 (en) * | 2009-06-17 | 2010-12-23 | シャープ株式会社 | Shift resister, display-driving circuit, displaying panel, and displaying device |
| CN102012591A (en) * | 2009-09-04 | 2011-04-13 | 北京京东方光电科技有限公司 | Shift register unit and liquid crystal display gate drive device |
| CN102254503A (en) * | 2010-05-19 | 2011-11-23 | 北京京东方光电科技有限公司 | Shift register unit, grid driving device used for display and liquid crystal display |
-
2011
- 2011-11-25 CN CN201110381861.5A patent/CN102708777B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1681047A (en) * | 2004-02-06 | 2005-10-12 | 三星电子株式会社 | Shift register and display device therewith |
| KR20060097819A (en) * | 2005-03-07 | 2006-09-18 | 삼성전자주식회사 | Shift register and display device having the same |
| WO2010146753A1 (en) * | 2009-06-17 | 2010-12-23 | シャープ株式会社 | Shift resister, display-driving circuit, displaying panel, and displaying device |
| CN102012591A (en) * | 2009-09-04 | 2011-04-13 | 北京京东方光电科技有限公司 | Shift register unit and liquid crystal display gate drive device |
| CN102254503A (en) * | 2010-05-19 | 2011-11-23 | 北京京东方光电科技有限公司 | Shift register unit, grid driving device used for display and liquid crystal display |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956214A (en) * | 2012-11-19 | 2013-03-06 | 京东方科技集团股份有限公司 | Common electrode driving unit, liquid crystal display panel and liquid crystal display device |
| WO2014153813A1 (en) * | 2013-03-29 | 2014-10-02 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, grid driving apparatus and display apparatus |
| WO2014205897A1 (en) * | 2013-06-26 | 2014-12-31 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, and display device |
| US9613578B2 (en) | 2013-06-26 | 2017-04-04 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and display device |
| CN104361875A (en) * | 2014-12-02 | 2015-02-18 | 京东方科技集团股份有限公司 | Shifting register unit as well as driving method, grid driving circuit and display device |
| WO2016086566A1 (en) * | 2014-12-02 | 2016-06-09 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, gate drive circuit, and display device |
| US9799287B2 (en) | 2014-12-02 | 2017-10-24 | Boe Technology Group Co., Ltd. | Shift register unit and driving method thereof, gate driving circuit and display device |
| CN108122529B (en) * | 2018-01-25 | 2021-08-17 | 京东方科技集团股份有限公司 | Gate driving unit, driving method thereof and gate driving circuit |
| CN108122529A (en) * | 2018-01-25 | 2018-06-05 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method and gate driving circuit |
| US11232846B2 (en) | 2018-01-25 | 2022-01-25 | Boe Technology Group Co., Ltd. | Gate drive unit and driving method thereof and gate drive circuit |
| WO2020207217A1 (en) * | 2019-04-09 | 2020-10-15 | 京东方科技集团股份有限公司 | Gate driver unit, gate drive method, gate driver circuit, and display device |
| US11328642B2 (en) | 2019-04-09 | 2022-05-10 | Boe Technology Group Co., Ltd. | Gate driving unit, gate driving method, gate driving circuitry and display device |
| CN112542140A (en) * | 2020-12-16 | 2021-03-23 | 合肥京东方卓印科技有限公司 | Shift register, gate drive circuit and drive method |
| US11361715B1 (en) | 2020-12-16 | 2022-06-14 | Hefei Boe Joint Technology Co., Ltd. | Shift register unit, gate driving circuitry and method for driving the same |
| CN113409717A (en) * | 2021-05-13 | 2021-09-17 | 北京大学深圳研究生院 | Shift register unit circuit, gate drive circuit and display |
| CN113409717B (en) * | 2021-05-13 | 2022-06-10 | 北京大学深圳研究生院 | Shift register unit circuit, gate drive circuit and display |
| CN113808653A (en) * | 2021-09-07 | 2021-12-17 | 深圳知微创新技术有限公司 | Shift register unit circuit and shift register |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102708777B (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102708777B (en) | Shift register unit and gate drive device | |
| CN103236272B (en) | Shift register cell and driving method, gate drive apparatus and display device | |
| CN104269132B (en) | A kind of shifting deposit unit, display floater and display device | |
| CN104700814B (en) | Shifting register unit, gate driving device and display device | |
| CN105304011B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN106157867B (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN102479477B (en) | Shifting register unit and grid drive circuit as well as display device | |
| CN102945651B (en) | Shift register, grid driving circuit and display device | |
| CN105513524B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN100530337C (en) | Shift register circuit and image display device having same | |
| CN102930812B (en) | Shift register, grid line integrated drive electronics, array base palte and display | |
| CN102982777B (en) | The gate driver circuit of display device | |
| CN102708816B (en) | Shift register, grid driving device and display device | |
| CN104269134B (en) | A kind of gate drivers, display unit and grid drive method | |
| CN102222480B (en) | Shift register | |
| CN101546545B (en) | Clock signal generating signal and clock signal generating circuit | |
| CN104425035B (en) | Shift register cell, shift register and display device | |
| CN105118463B (en) | A kind of GOA circuits and liquid crystal display | |
| CN104332146A (en) | Shifting register unit, shifting register, gate drive circuit and display device | |
| CN104867439A (en) | Shift register unit and driving method thereof, gate drive circuit and display device | |
| CN103915074B (en) | A kind of shift register cell, gate drive apparatus and display panel | |
| CN104485065A (en) | Shifting register, driving method and gate driving circuit | |
| CN103474095B (en) | Shift register circuit and operation method thereof | |
| CN107393461A (en) | Gate driving circuit and its driving method and display device | |
| CN105825814A (en) | Grid-driven circuit, drive method thereof, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |