CN116566370A - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN116566370A CN116566370A CN202310844504.0A CN202310844504A CN116566370A CN 116566370 A CN116566370 A CN 116566370A CN 202310844504 A CN202310844504 A CN 202310844504A CN 116566370 A CN116566370 A CN 116566370A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to a power-on reset circuit, which is provided with an oscillating unit, a first adjusting unit, a second adjusting unit and a reset signal generating unit; an oscillation unit for generating an internal clock signal; the first adjusting unit is used for receiving an internal clock signal and generating a first group of adjusting signals according to the internal clock signal, wherein the first group of adjusting signals comprise a plurality of modulation delay signals; the second adjusting unit is used for receiving the external clock signal output by the external clock circuit and a modulation delay signal output by the first adjusting unit, and adjusting the external clock signal according to the modulation delay signal to generate a second group of adjusting signals, wherein the second group of adjusting signals comprises at least one adjusting delay signal; the reset signal generating unit is used for receiving at least two modulation delay signals output by the first adjusting unit and one adjustment delay signal output by the second adjusting unit, and generating a reset signal according to the received modulation delay signals and the adjustment delay signals.
Description
Technical Field
The application relates to the field of circuit testing, in particular to a power-on reset circuit.
Background
Typically, at an early power-up stage, when the supply voltage has not reached a stable desired state, many circuit components (e.g., semiconductor devices, etc.) and the voltage and logic state of the circuit nodes are unstable. In order to enable the circuitry to operate from a state desired by the designer after each Power-up, a Power On Reset (POR) circuit may be used to generate a Reset signal for a period of time after the Power supply is stable, so as to force the circuitry to be in an initial state desired by the designer, and after the validity period of the Reset signal is over, the circuitry starts to operate from the desired initial state. That is, it can perform a reset operation on other modules in the circuitry to eliminate unstable states of the circuitry at the beginning of power-up.
Circuitry often requires an accurate reset delay time to ensure that the operating state of the circuitry's internal circuitry is both stable and controllable. For example, the reset delay time refers to an instruction period during which a low state of the reset signal continues. However, the conventional power-on reset circuit is simple in implementation, has a problem that the reset delay time is difficult to adjust, and is difficult to meet the requirements of a circuit system.
Disclosure of Invention
In view of this, the present application provides a power-on reset circuit, which can flexibly and accurately adjust the reset delay time to provide an accurate reset signal, so that the performance is more reliable.
The application provides a power-on reset circuit, it includes: an oscillation unit for generating an internal clock signal; the first adjusting unit is electrically connected with the oscillating unit and is used for receiving an internal clock signal output by the oscillating unit and generating a first group of adjusting signals according to the internal clock signal, wherein the first group of adjusting signals comprise a plurality of modulation delay signals; the second adjusting unit is respectively and electrically connected with the external clock circuit and the first adjusting unit, and is used for receiving the external clock signal output by the external clock circuit and a modulation delay signal output by the first adjusting unit, adjusting the external clock signal according to the modulation delay signal to generate a second group of adjusting signals, wherein the second group of adjusting signals comprises at least one adjusting delay signal; the reset signal generating unit is respectively and electrically connected with the first adjusting unit and the second adjusting unit, and is used for receiving at least two modulation delay signals output by the first adjusting unit and one adjustment delay signal output by the second adjusting unit, and generating a reset signal according to the received modulation delay signals and the adjustment delay signals.
Optionally, the first adjusting unit includes a first frequency dividing subunit and a first delay subunit which are electrically connected, and the first group of adjusting signals further includes a plurality of first frequency dividing clock signals; the first frequency dividing subunit is used for performing frequency dividing processing on the internal clock signal for a plurality of times to generate a first frequency dividing clock signal in the first group of adjusting signals; the first delay subunit is configured to delay the first divided clock signal to generate a modulated delayed signal in the first set of adjustment signals.
Optionally, the second adjusting unit includes a second frequency dividing subunit and a second delay subunit that are electrically connected, where the second frequency dividing subunit and the second delay subunit are respectively electrically connected to the first delay subunit, and the second group of adjusting signals further includes a second frequency dividing clock signal; the second frequency dividing subunit is configured to receive a modulated delay signal output by the first delay subunit, so as to perform frequency dividing processing on the external clock signal, and generate the second frequency dividing clock signal; the second delay subunit is configured to receive a modulated delay signal output by the first delay subunit, to delay the second divided clock signal, and to generate an adjustment delay signal in the second set of adjustment signals.
Optionally, the reset signal generating unit includes an inverting module and a first multiplexer electrically connected to each other; the inverting module is used for inverting the modulation delay signal output by the first adjusting unit to obtain an inverted delay signal; the first multiplexer is used for receiving a regulating delay signal output by the second regulating unit, the inverted delay signal output by the inverting module and a modulation delay signal output by the first regulating unit so as to generate the reset signal in a coupling way.
Optionally, the device further includes a clock signal generating unit, where the clock signal generating unit is electrically connected to the first frequency dividing subunit, the first delay subunit and the second frequency dividing subunit, and the clock signal generating unit is configured to receive a first frequency dividing clock signal output by the first frequency dividing subunit, at least two modulation delay signals output by the first delay subunit, and a second frequency dividing clock signal output by the second frequency dividing subunit, and generate a modulation clock signal according to the received first frequency dividing clock signal, the modulation delay signal, and the second frequency dividing clock signal.
Optionally, the clock signal generating unit includes an and gate module and a second multiplexer electrically connected to each other; the AND gate module is used for receiving a first frequency division clock signal output by the first frequency division subunit and a modulation delay signal output by the first delay subunit so as to output an initial modulation clock signal; the second multiplexer is configured to receive the initial modulation clock signal, a modulation delay signal output by the first delay subunit, and a second frequency division clock signal output by the second frequency division subunit, so as to generate the modulation clock signal in a coupling manner.
Optionally, the first frequency dividing subunit includes a second target frequency dividing subunit and a first target frequency dividing subunit that are electrically connected, where the second target frequency dividing subunit and the first target frequency dividing subunit are configured to divide the internal clock signal multiple times to sequentially obtain two first frequency dividing clock signals, the second target frequency dividing subunit is a frequency divider with two frequency dividing, the first target frequency dividing subunit includes a plurality of D flip-flops that are electrically connected, a reset end of each D flip-flop is configured to be connected to a detection enable signal, a data input end of each D flip-flop is electrically connected to a complementary output end corresponding to the D flip-flop, a clock signal end of the first D flip-flop is configured to be connected to the first frequency dividing clock signal output by the second target frequency dividing subunit, and a data output end of two adjacent D flip-flops is electrically connected to the clock signal end.
Optionally, the first delay subunit includes a plurality of D flip-flops electrically connected, a reset end of each D flip-flop is used for accessing the detection enable signal, a clock signal end of each D flip-flop is electrically connected with the first frequency dividing subunit and is used for receiving a first frequency dividing clock signal output by the first frequency dividing subunit, a data input end of a first D flip-flop is used for accessing the detection enable signal, and data output ends of two adjacent D flip-flops are electrically connected with the data input end.
Optionally, the second frequency division subunit includes a plurality of D flip-flops electrically connected in turn, a reset end of each D flip-flop is electrically connected with the first delay subunit and is used for accessing a modulation delay signal, a data input end of each D flip-flop is electrically connected with a complementary output end corresponding to the data input end, a clock signal end of a first D flip-flop is used for accessing the external clock signal, and data output ends of two adjacent D flip-flops are electrically connected with the clock signal end.
Optionally, the second delay subunit includes a plurality of D flip-flops electrically connected, a reset end of each D flip-flop is electrically connected with the first delay subunit and is used for accessing a modulation delay signal, a clock signal end of each D flip-flop is electrically connected with the second frequency division subunit and is used for receiving the second frequency division clock signal output by the second frequency division subunit, a data input end of a first D flip-flop is used for accessing a control voltage signal, and a data output end and a data input end of two adjacent D flip-flops are electrically connected.
As described above, the power-on reset circuit provided by the invention has the following beneficial effects:
according to the power-on reset circuit, the first adjusting unit and the second adjusting unit are used for adjusting the internal clock signal and the external clock signal to obtain a plurality of delay signals, and the corresponding delay signals are selected to generate the reset signals, so that the reset delay time corresponding to the reset signals is flexibly and accurately adjusted, the requirements are met on the whole, and the performance is more reliable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a circuit structure of a power-on reset circuit according to an embodiment of the present application;
fig. 2 shows a schematic circuit structure of an oscillating unit according to an embodiment of the present application;
fig. 3 is a schematic block diagram of a circuit structure of a first adjusting circuit according to an embodiment of the present application;
Fig. 4 shows a schematic circuit structure of a first target frequency divider subunit according to an embodiment of the present application;
fig. 5 shows a schematic circuit structure of a first delay subunit according to an embodiment of the present application;
fig. 6 shows a schematic circuit structure of a power-on detection circuit according to an embodiment of the present application;
fig. 7 is a schematic block diagram showing a circuit configuration of a second adjusting unit according to an embodiment of the present application;
fig. 8 is a schematic block diagram of a circuit structure of a second frequency division subunit according to an embodiment of the present application;
FIG. 9 is a schematic block diagram of a circuit structure of a second delay sub-unit according to an embodiment of the present application;
fig. 10 is a schematic circuit diagram of a circuit for generating a control voltage signal according to an embodiment of the present application;
fig. 11 is a schematic circuit diagram showing a reset signal generating unit according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a circuit configuration of another power-on reset circuit according to an embodiment of the present disclosure;
fig. 13 is a schematic circuit diagram of a clock signal generating unit according to an embodiment of the present application;
FIG. 14 is a schematic diagram showing waveforms of an enable signal, a power supply voltage, an energizing voltage, a second divided clock signal, a third divided clock signal, a first delay signal, a second delay signal, a third delay signal, an initial modulation clock signal, a modulation clock signal, and a reset signal provided in an embodiment of the present application;
Fig. 15 shows a block diagram of a power-on reset system according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. Based on the examples in the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
Fig. 1 is a schematic block diagram of a circuit structure of a power-on reset circuit according to an embodiment of the present application. The present application provides a power-on reset circuit 100, which power-on reset circuit 100 may be applied to circuitry. The power supply VDD supplies power to the circuit system, and when the power supply VDD is powered on, the corresponding circuit modules in the circuit system need to be reset so as to ensure that the circuit system can work normally. The power-on reset circuit 100 can realize the reset of the circuit system after the power supply VDD starts to be powered on, has accurate reset delay time, meets the requirements of the circuit system, and ensures more reliable performance.
In the present embodiment, referring to fig. 1, a power-on reset circuit 100 may include an oscillation unit 10, a first adjustment unit 20, a second adjustment unit 30, and a reset signal generation unit 40. The oscillating unit 10 may generate an internal clock signal clk_ring and is electrically connected to the first adjusting unit 20. The first adjusting unit 20 adjusts the internal clock signal clk_ring from the oscillating unit 10 to generate a first set of adjusting signals. The second adjusting unit 30 may receive an external clock signal clk_ex from outside the power-on reset circuit 100 to adjust to generate a second set of adjustment signals. The first adjusting unit 20 and the second adjusting unit 30 are electrically connected with the reset signal generating unit 40, and part of the first group adjusting signals and part of the second group adjusting signals are coupled and processed by the reset signal generating unit 40 to generate reset signals. It will be appreciated that the reset delay time of the reset signal may be determined by the first set of adjustment signals and the second set of adjustment signals. In this case, the power-on reset circuit 100 can determine the reset delay time of the reset signal by adjusting the first set of adjustment signals and the second set of adjustment signals.
In particular, the first set of adjustment signals may comprise a number of modulated delay signals. The second adjusting unit 30 is configured to receive a modulated delayed signal output by the first adjusting unit 20, and adjust the external clock signal clk_ex according to the modulated delayed signal to generate a second set of adjusting signals. Wherein the second set of adjustment signals may include at least one adjustment delay signal. The reset signal generating unit 40 may receive the modulation delay signal output from the first adjusting unit 20 and the adjustment delay signal output from the second adjusting unit 30, and generate a reset signal according to the received modulation delay signal and adjustment delay signal. In this case, the generation of the reset signal is related to the received modulated delay signal and the adjusted delay signal. The delay time of the corresponding delay signals can be flexibly adjusted by adjusting the delay time of the corresponding delay signals by the first adjusting unit 20 and the second adjusting unit 30, so that the requirements of the circuit system are met as a whole.
In this embodiment, the oscillating unit 10 may be an oscillating circuit for generating the internal clock signal clk_ring. For example, the oscillating unit 10 may be a ring oscillating circuit. Fig. 2 shows a schematic circuit structure of an oscillating unit 10 according to an embodiment of the present application, and a specific circuit is shown in fig. 2. The oscillating unit 10 may include a constant current source, a plurality of switching transistors, a schmitt inverter, an inverter, a nand gate, and an output buffer unit BUF. Wherein, DVDD is power supply voltage DVDD. Q1, Q2, Q6 and Q7 are NMOS switching tubes, Q3, Q4 and Q5 are PMOS switching tubes, Q8 is a Schmidt inverter, Q9 is an inverter, Q10 is a NAND gate device, and Q11 is an output buffer unit BUF. In addition to the embodiment disclosed in fig. 2, the oscillating unit 10 may employ other oscillating circuits, such as a conventional ring oscillating circuit.
It will be appreciated that referring to fig. 2 and 3, the oscillating unit 10 may include a plurality of input ports, one of which is used for inputting the power supply voltage DVDD, and one of which is input as an enable terminal via the enable signal en_n to control the operation state of the oscillating unit 10. For example, when the power supply VDD supplies power, the power supply VDD is converted into the power supply voltage DVDD through a circuit to supply power to the power-on reset circuit 100, so that the oscillation unit 10 operates to generate the internal clock signal clk_ring. If the enable signal en_n is at a low level, the oscillating unit 10 can oscillate to generate the internal clock signal clk_ring after power is supplied; if the enable signal en_n is at the high level at this time, the oscillating unit 10 does not operate, i.e., the clock output associated with the oscillating unit 10 is 0. The waveforms of the power supply voltage VDD, the power supply voltage DVDD, and the enable signal en_n may be referred to fig. 14.
In some embodiments, several modulated delay signals of the first set of adjustment signals may be obtained by adjusting the internal clock signal clk_ring from the oscillating unit 10 via the first adjusting unit 20. Specifically, the first adjusting unit 20 may divide and delay the internal clock signal clk_ring to obtain a number of modulated delayed signals.
In the present embodiment, the first adjusting unit 20 may include a first frequency dividing subunit 21. The first frequency dividing subunit 21 may be electrically connected to the oscillating unit 10 to receive the internal clock signal clk_ring. The first frequency dividing subunit 21 may be configured to perform frequency dividing processing on the internal clock signal clk_ring to output a clock signal having an appropriate frequency. The frequency of the clock signal is not limited explicitly, and can be determined according to the reset delay time required by the circuit system, and the delay time of the modulation delay signal generated later is controlled by changing the frequency division ratio of the first frequency division subunit 21, so as to control the reset delay time.
The first adjustment unit 20 may comprise a first delay sub-unit 22. The first delay subunit 22 may be electrically connected to the first frequency dividing subunit 21 to receive the clock signal output by the first frequency dividing subunit 21; the first delay subunit 22 is configured to delay the clock signal to obtain a plurality of modulated delayed signals. It will be appreciated that the delay times corresponding to when the modulated delay signals are delay processed may be different. That is, the first delay subunit 22 may perform delay processing on the received clock signal a plurality of times to sequentially obtain a plurality of modulated delay signals.
However, the example of the present application is not limited thereto, and in other embodiments, the oscillating unit 10 may output an internal clock signal having an appropriate frequency, and the first adjusting unit 20 may directly delay-process the internal clock signal to obtain a number of modulation delay signals. In this case, the first delay subunit 22 may be electrically connected to the oscillating unit 10, for performing delay processing on the internal clock signal to obtain a plurality of modulated delay signals.
It will be appreciated that the first frequency dividing subunit 21 performs frequency dividing processing on the internal clock signal clk_ring output from the oscillating unit 10, and then obtains a frequency-divided clock signal (also referred to as a first frequency-divided clock signal). In this embodiment, the first divided clock signal may also be categorized in the first set of adjustment signals.
In some embodiments, the first set of adjustment signals may include a number of first divided clock signals. Specifically, the first frequency dividing subunit 21 may be configured to perform frequency dividing processing on the internal clock signal clk_ring multiple times to generate a first frequency-divided clock signal in the first group of adjustment signals. It is understood that the frequencies corresponding to the plurality of first divided clock signals may be different. In this case, the first divided clock signal having an appropriate frequency can be selected according to the need for the reset delay time.
Fig. 3 is a schematic block diagram of a circuit structure of a first adjusting circuit according to an embodiment of the present application.
In some embodiments, referring to fig. 3, the first frequency dividing subunit 21 may include a plurality of target frequency dividing subunits. The plurality of target frequency dividing subunits perform frequency dividing processing on the internal clock signal CLK_RING for a plurality of times to obtain a plurality of first frequency dividing clock signals. Each of the first divided clock signals may be a divided clock signal output by a corresponding target divided subunit.
Specifically, referring to fig. 3 and 4, the first frequency dividing subunit 21 may include a first target frequency dividing subunit 211 and a second target frequency dividing subunit 212 electrically connected. The second target frequency divider subunit 212 may be electrically connected to the oscillating unit 10 to receive the internal clock signal clk_ring. The second target frequency dividing subunit 212 performs frequency dividing processing on the internal clock signal clk_ring to obtain a first frequency divided clock signal clk_ring_d2. The first target frequency divider subunit 211 may receive the first frequency-divided clock signal clk_ring_d2 and perform frequency division processing on the first frequency-divided clock signal clk_ring_d2 to obtain a first frequency-divided clock signal clk_ring_dx.
That is, the second target frequency dividing subunit 212 and the first target frequency dividing subunit 211 are configured to divide the internal clock signal clk_ring multiple times to sequentially obtain two first divided clock signals (e.g., clk_ring_d2 and clk_ring_dx). The first divided clock signal clk_ring_d2 and the first divided clock signal clk_ring_dx may have different frequencies.
In some embodiments, second target frequency divider subunit 212 may be a divide-by-two frequency divider. Alternatively, the second target frequency divider subunit 212 may be a frequency divider with a preset frequency dividing ratio, so that the duty cycle of the first frequency dividing clock signal clk_ring_d2 is 50%.
In some embodiments, the first target frequency divider subunit 211 includes a plurality of D flip-flops electrically connected. The plurality of D flip-flops as in the first target frequency dividing subunit 211 are connected substantially in series to perform frequency dividing processing on the received clock signal. The frequency division ratio of the first target frequency division subunit 211 may be related to the number of D flip-flops, for example, the more D flip-flops connected, the larger the frequency division ratio. In the present embodiment, the frequency division ratio of the first target frequency dividing subunit 211 is controlled by controlling the number of D flip-flops. It is understood that the first target frequency dividing subunit 211 may output a plurality of first frequency dividing clock signals, and specifically, the data output terminal Q of each D flip-flop may be an output port of the first frequency dividing clock signal.
In some embodiments, referring to fig. 4, the D flip-flop may have a data input terminal D, a clock signal terminal Clk, a Reset terminal Reset, a data output terminal Q, and a complementary output terminal Qb.
The first target frequency dividing subunit 211 includes a plurality of cascaded D flip-flops. The Reset terminal Reset of each D flip-flop is used to access the sense enable signal vt_vdd. The data input end D of each D trigger is electrically connected with the corresponding complementary output end Qb. The clock signal terminal Clk of the first D flip-flop is used to access a clock signal. The data output terminals Q of two adjacent D flip-flops are electrically connected to the clock signal terminal Clk.
Specifically, the first target frequency divider subunit 211 includes N cascaded (e.g., serially connected) D flip-flops, where N is a positive integer. In the first target frequency dividing subunit 211, the Reset terminals Reset of the ith D flip-flop are all used for accessing the detection enable signal vt_vdd, the data input terminal D of the ith D flip-flop is electrically connected to the complementary output terminal Qb corresponding to the data input terminal D of the ith D flip-flop, the clock signal terminal Clk of the 1 st D flip-flop is used for accessing the first frequency dividing clock signal clk_ring_d2, and the data output terminal Q of the ith D flip-flop is electrically connected to the clock signal terminal Clk of the i+1th D flip-flop. Wherein i is a positive integer, and i < N.
In this embodiment, the detection enable signal vt_vdd may be generated by a power-up detection circuit. The power-on detection circuit is shown with reference to fig. 6, which will be described in detail later.
In some embodiments, the first delay subunit 22 may delay the received clock signal to obtain a number of modulated delay signals, for example, a modulated delay signal ring_chan_sel, a modulated delay signal ring_clk_sel, a modulated delay signal ring_sel, and the like.
In some embodiments, referring to fig. 5, the first delay sub-unit 22 includes a plurality of electrically connected D flip-flops. Such as a plurality of D flip-flops in the first delay sub-unit 22, are connected in substantially series to delay the received clock signal. The delay time of the modulated delay signal obtained by the first delay subunit 22 may be related to the number of D flip-flops, for example, the more D flip-flops connected in series, the longer the delay time corresponding to the modulated delay signal output by the last D flip-flop. The delay time may refer to a point in time when the level of the modulated delay signal is flipped. Referring to fig. 5 and 14, the modulated delay signal ring_chan_sel corresponds to more D flip-flops than the modulated delay signal ring_sel, and the modulated delay signal ring_chan_sel corresponds to a longer delay time. In this embodiment, the delay time of the generated modulated delay signal is controlled by controlling the number of connected D flip-flops. It will be appreciated that the first delay subunit 22 may output a plurality of modulated delay signals. The signal output by the data output terminal Q of each D flip-flop can be used as the modulation delay signal in this embodiment.
In some embodiments, referring to fig. 5, the first delay sub-unit 22 includes a plurality of cascaded (e.g., series) D flip-flops. The Reset terminal Reset of each D flip-flop is used to access the sense enable signal vt_vdd. The clock signal terminal Clk of each D flip-flop is used to access a clock signal. The data input D of the first D flip-flop is used for accessing the detection enable signal vt_vdd. The data output end Q of two adjacent D flip-flops is electrically connected with the data input end D.
Specifically, the first delay subunit 22 includes M cascaded D flip-flops, where M is a positive integer. In the first delay sub-unit 22, the Reset terminals Reset of the jth D flip-flop are each used to access the detection enable signal vt_vdd. The clock signal terminals Clk of the jth D flip-flop are electrically connected to the first frequency divider subunit 21 and are configured to receive a first frequency-divided clock signal (e.g., the first frequency-divided clock signal clk_ring_dx) output by the first frequency divider subunit 21. The data input D of the jth D flip-flop is used for accessing the detection enable signal vt_vdd. The data output terminal Q of the j-th D flip-flop is electrically connected to the data input terminal D of the j+1th D flip-flop. Wherein j is a positive integer, and j < M.
In some embodiments, referring to fig. 6, the power-on detection circuit includes a mirror circuit unit 110, a voltage distribution unit 120, a feedback adjustment unit 130, and a voltage output unit 140, which are electrically connected, and the feedback adjustment unit 130 may be electrically connected to the voltage distribution unit 120. The mirror circuit unit 110 and the voltage distribution unit 120 are electrically connected, and the mirror circuit unit 110 and the voltage division unit 120 can be electrically connected with a power supply so as to be convenient for accessing the power supply voltage VDD.
The mirror circuit unit 110 may include a first switching tube M1 and a second switching tube M2, where a first end of the first switching tube M1 may be connected to a power supply, a second end of the first switching tube M1 may be connected to a third end of the first switching tube M1, and the third end of the first switching tube M1 may be used as a first output end a of the mirror circuit unit 110 to output a first voltage control signal VA (i.e., an a node voltage). The first end of the second switching tube M2 may be connected to a power supply, the second end of the second switching tube M2 may be connected to the second end of the first switching tube M1, and the third end of the second switching tube M2 may be used as the second output end B of the mirror circuit unit 110 to output the second voltage control signal VB (i.e., node B voltage).
The mirror circuit unit 110 further includes a first pull-down resistor R1 and a second pull-down resistor R2, the third terminal of the first switching tube M1 is grounded through the first pull-down resistor R1, and the third terminal of the second switching tube M2 is grounded through the second pull-down resistor R2, in which case, by adjusting the first pull-down resistor R1 and the second pull-down resistor R2, the magnitudes of the first voltage control signal VA and the second voltage control signal VB can be changed. In the present embodiment, during the power-up process, as the power voltage VDD increases, the first switching tube M1 and the first pull-down resistor R1 establish the stable current I1, and the first voltage control signal VA increases to a stable voltage value. The first switching tube M1 and the second switching tube M2 generate stable current I2 in a mirror image mode, the current I2 and the second pull-down resistor R2 establish a stable second voltage control signal VB, and the second voltage control signal VB tends to be stable along with the rising of VDD (the current is an initial stable state).
The voltage distribution unit 120 includes a third switching tube M3 and a fourth switching tube M4, and the third switching tube M3 and the fourth switching tube M4 may be disposed in series. The first end of the third switching tube M3 is connected to the power source, the second end of the third switching tube M3 is connected to the first output end a to receive the first voltage control signal VA, and the third end of the third switching tube M3 may be used as an output end of the voltage distribution unit 120 to be connected to the voltage output unit 140. The second end of the fourth switching tube M4 is connected to the second output end B to receive the second voltage control signal VB, and the first end of the fourth switching tube M4 may be connected to the third end of the third switching tube M3, where the third end of the fourth switching tube M4 is grounded.
It is understood that the second end of the third switching tube M3 may be a control end of the third switching tube M3, and the on state of the third switching tube M3 may be adjusted by the control end. The third terminal of the third switching tube M3 may be an output terminal of the third switching tube M3. Likewise, the second end of the fourth switching tube M4 may be a control end of the fourth switching tube M4, and the on state of the fourth switching tube M4 may be adjusted by the control end. The third terminal of the fourth switching tube M4 may be an output terminal of the fourth switching tube M4.
The feedback adjustment unit 130 includes a fifth switching tube M5, and a first end of the fifth switching tube M5 is connected to the power supply through a pull-up resistor R3. The second end of the fifth switch tube M5 is electrically connected to the output end of the voltage distribution unit 120 to receive the divided voltage signal VC (i.e., the node C voltage).
The voltage output unit 140 is electrically connected to the voltage distribution unit 120, and is configured to convert the divided voltage signal VC and output a corresponding voltage detection signal vt_vdd. In this case, the voltage detection signal vt_vdd can better reflect the state of the current power supply voltage VDD, so that the detection of the power supply voltage VDD is facilitated.
In some embodiments, as shown in fig. 6, the voltage output unit 140 is an inverter. The voltage output unit 140 may be electrically connected to the output terminal of the voltage distribution unit 120. Specifically, the input end of the inverter may be electrically connected to the third end of the third switching tube M3. In this case, the inverter may invert the divided voltage signal VC output from the voltage distribution unit 120 to output the voltage detection signal vt_vdd, and the level state of the voltage detection signal vt_vdd may be substantially synchronized with the power supply voltage VDD, which may better reflect the state of the power supply voltage VDD.
In some embodiments, the first switching tube M1 may be a PMOS tube, the second switching tube M2 may be a PMOS tube, the third switching tube M3 may be a PMOS tube, the fourth switching tube M4 may be an NMOS tube, and the fifth switching tube M5 may be a PMOS tube.
Working principle of power-on detection circuit: when the power supply VDD is powered on, the first switching transistors M1 and R1 establish a stable current I1 as the voltage of the power supply VDD increases, and the voltage VA at the point a (i.e., the first voltage control signal) increases to a stable voltage value. The currents i2=i1, I2 and R2 generated by the mirror images of the first switching tube M1 and the second switching tube M2 establish a stable B-point voltage VB (i.e., the second voltage control signal). The second voltage control signal VB becomes stable (in this case, the initial stable state) as the power supply VDD increases.
Further, by setting the on threshold values of the third switching tube M3 and the fourth switching tube M4, the voltage value of the power supply VDD when the third switching tube M3 and the fourth switching tube M4 are turned on is set to be a required voltage threshold value, namely, the generated vt_vdd voltage is in a low level in the rising process of the power supply VDD, and the vt_vdd is converted to a high level after the power supply VDD exceeds a preset threshold VT, wherein the preset threshold VT can be determined jointly by the on threshold values of the third switching tube M3 and the fourth switching tube M4.
The power-on detection circuit further includes a feedback adjustment unit 130, i.e. a branch where the fifth switching tube M5 is located, where the feedback adjustment unit 130 can improve voltage stability of the detection enable signal vt_vdd, when the third switching tube M3 and the fourth switching tube M4 are turned on, the voltage division signal VC changes from "high" to "low" to make the fifth switching tube M5 be turned on, and the fifth switching tube M5 is turned on to pull the B-point voltage (i.e. the second voltage control signal VB), so as to further enhance conduction currents of the third switching tube M3 and the fourth switching tube M4, and accelerate an overall conversion process; when the power supply voltage VDD drops, since the fifth switching transistor M5 is in an on state, at this time, the second voltage control signal VB is higher than the original steady state, so that the disruption state stabilization requires a larger drop of the power supply VDD, for example, to drop below the stability threshold VOL, which may be determined by the third switching transistors M5 and R3, and which is smaller than the predetermined threshold VT. Therefore, the power-on detection circuit has a higher stable state, and can effectively reduce adverse effects caused by fluctuation of the power supply VDD, namely, the stable state is difficult to break when the power supply VDD fluctuates, for example, the break of the stable state can lead the detection enable signal VT_VDD to be reduced to a low level so as to improve the stability of the output detection enable signal VT_VDD. It will be appreciated that if the power supply VDD falls below the stability threshold VOL and is powered up again, it is necessary to rise to the predetermined threshold VT, and the vt_vdd voltage is restored to the "high" level.
In some embodiments, the first frequency-dividing subunit 21 may provide the first frequency-dividing clock signal with an appropriate frequency to the first delay subunit 22, and the first delay subunit 22 may access the detection enable signal vt_vdd to adjust the delay time in the generated modulation delay signal in coordination with the first frequency-dividing clock signal. For example, after a period of power-up of the power supply VDD, the detection enable signal vt_vdd is changed from low level to high level, if the frequency of the first divided clock signal received by the first delay subunit 22 is low, the rising edge frequency encountered by the clock signal terminal Clk of the D flip-flop becomes low in the same time range, so that the delay time of the modulation delay signal becomes long, that is, the time point of level inversion of the modulation delay signal is delayed backward, that is, it takes a longer time for the modulation delay signal to generate level inversion.
In some embodiments, the adjusted delay signal of the second set of adjusted signals may be obtained by adjusting an external clock signal clk_ex from outside the power-on reset circuit 100 via the second adjusting unit 30. Specifically, the second adjusting unit 30 may divide and delay the external clock signal clk_ex and the like to obtain the adjusted delay signal.
In this embodiment, the external clock signal clk_ex may be from an external clock circuit external to the power-on reset circuit 100, or may be from a crystal or MEMS oscillator external to the power-on reset circuit 100, which is not particularly limited in this application. For example, the power-on-reset circuit 100 of the present application may be applied in a MESM oscillator that includes a resonator, such as the power-on-reset circuit 100 disposed on a CMOS die in the MESM oscillator. The clock signal output from the resonator may be input to the second adjusting unit 30 as an external clock signal clk_ex.
In some embodiments, referring to fig. 7, the second adjusting unit 30 may include a third multiplexer 33, one input signal terminal of the third multiplexer 33 is used for receiving a clock signal clkin_ex generated by an external clock circuit, the other input signal terminal is used for receiving a clock signal clkin_xo generated by a crystal or a MEMS oscillator, and the clock signal output after being selected by the third multiplexer 33 is input to the second frequency dividing subunit 31 as the external clock signal clk_ex.
In some embodiments, referring to fig. 7, the second adjusting unit 30 may include a second frequency dividing subunit 31. The second frequency dividing subunit 31 may receive the external clock signal clk_ex. The second frequency dividing subunit 31 may be configured to perform frequency dividing processing on the external clock signal clk_ex to output a clock signal having an appropriate frequency. The frequency of the clock signal is not limited explicitly, and can be determined according to the reset delay time required by the circuit system, and the delay time of the subsequently generated adjustment delay signal is controlled by changing the frequency division ratio of the second frequency division subunit 31, so as to control the reset delay time.
The second adjustment unit 30 may comprise a second delay sub-unit 32. The second delay subunit 32 may be electrically connected to the second frequency dividing subunit 31 to receive the clock signal output by the second frequency dividing subunit 31; the second delay subunit 32 is configured to delay the clock signal to obtain at least one adjusted delay signal. It will be appreciated that the delay times corresponding to the respective adjusted delay signals when they are delay processed may be different. That is, the second delay sub-unit 32 may perform delay processing on the received clock signal a plurality of times to sequentially obtain a plurality of adjustment delay signals.
However, the examples of the present application are not limited thereto, and in other embodiments, the second delay subunit 32 may directly access an external clock signal having an appropriate frequency, and the second adjusting unit 30 may delay the external clock signal to obtain a plurality of adjusted delay signals. In this case, the second delay subunit 32 may be electrically connected to, for example, the third multiplexer 33 to access an external clock signal for delay processing the external clock signal to obtain a number of adjusted delay signals.
It will be appreciated that the second frequency dividing subunit 31 may obtain a frequency-divided clock signal (also referred to as a second frequency-divided clock signal) after performing the frequency division processing on the external clock signal clk_ex. In this embodiment, the second divided clock signal may also be categorized in the second set of adjustment signals.
In some embodiments, the second set of adjustment signals may include at least one second divided clock signal (e.g., the second divided clock signal CLK_EX_DX). Specifically, the second frequency dividing subunit 31 may be configured to perform frequency dividing processing on the external clock signal clk_ex to generate a second frequency-divided clock signal in the second group of adjustment signals. It is understood that if the number of the second divided clock signals is plural, frequencies corresponding to the second divided clock signals may be different. In this case, the second divided clock signal having an appropriate frequency can be selected according to the need for the reset delay time.
In some embodiments, the second frequency-dividing subunit 31 may be electrically connected to the first delay subunit 22 to receive a modulation delay signal (e.g. the modulation delay signal ring_chan_sel) output by the first delay subunit 22. The second frequency dividing subunit 31 may divide the external clock signal clk_ex according to the modulation delay signal and generate a second frequency-divided clock signal (e.g., the second frequency-divided clock signal clk_ex_dx).
In some embodiments, referring to fig. 8, the second frequency divider subunit 31 includes a plurality of D flip-flops electrically connected. The plurality of D flip-flops as in the second frequency dividing subunit 31 are connected substantially in series to perform frequency dividing processing on the received clock signal. The frequency division ratio of the second frequency division subunit 31 may be related to the number of D flip-flops, for example, the more D flip-flops connected, the larger the frequency division ratio. In the present embodiment, the frequency division ratio of the second frequency division subunit 31 is controlled by controlling the number of D flip-flops. It will be appreciated that the second frequency dividing subunit 31 may output a plurality of second frequency dividing clock signals, and specifically, the data output terminal Q of each D flip-flop may be an output port of the second frequency dividing clock signal.
In some embodiments, the second frequency dividing subunit 31 comprises a plurality of cascaded (e.g., series) D flip-flops. The Reset terminal Reset of each D flip-flop is coupled to a modulated delay signal (e.g., modulated delay signal RING chansel). The data input end D of each D trigger is electrically connected with the corresponding complementary output end Qb. The clock signal terminal Clk of the first D flip-flop is used to access the external clock signal clk_ex. The data output terminals Q of two adjacent D flip-flops are electrically connected to the clock signal terminal Clk.
Specifically, the second frequency divider subunit 31 includes K cascaded (e.g., serially connected) D flip-flops, where K is a positive integer. The Reset terminals Reset of the a-th D flip-flop are electrically connected to the first delay subunit 22 and are used for inputting a modulation delay signal (e.g. a modulation delay signal ring_chan_sel). The data input end D of the a-th D flip-flop is electrically connected with the corresponding complementary output end Qb. The clock signal terminal Clk of the 1 st D flip-flop is used for accessing the external clock signal clk_ex. The data output terminal Q of the a-th D flip-flop is electrically connected to the clock signal terminal Clk of the a+1th D flip-flop. Wherein a is a positive integer, and a < K.
In some embodiments, the second delay subunit 32 may delay the received clock signal to obtain at least one adjusted delay signal, for example, an adjusted delay signal sel_ex, etc.
In some embodiments, referring to fig. 9, the second delay sub-unit 32 includes a plurality of electrically connected D flip-flops. Such as a plurality of D flip-flops in the second delay sub-unit 32, are connected in substantially series to delay the received clock signal. The delay time of the adjusted delay signal obtained by the second delay subunit 32 may be related to the number of D flip-flops, for example, the more D flip-flops connected in series, the longer the delay time corresponding to the adjusted delay signal output by the last D flip-flop. The delay time may refer to a point in time at which the level inversion of the adjusted delay signal occurs. In this embodiment, the delay time of the generated adjustment delay signal is controlled by controlling the number of connection D flip-flops. It is understood that the second delay subunit 32 may output a plurality of adjustment delay signals. The signal output by the data output terminal Q of each D flip-flop can be used as the delay adjustment signal in this embodiment.
In some embodiments, the second delay subunit 32 may be electrically connected to the first delay subunit 22, so as to receive a modulated delay signal (e.g. the modulated delay signal ring_chan_sel) output by the first delay subunit 22. The second delay subunit 32 delays the received clock signal (e.g., the second divided clock signal clk_ex_dx) according to the modulated delay signal and generates the adjusted delay signal of the second set of adjusted signals.
In some embodiments, referring to fig. 9, the second delay sub-unit 32 includes a plurality of cascaded (e.g., series) D flip-flops. The Reset terminal Reset of each D flip-flop is used to access a modulated delay signal. The clock signal terminal Clk of each D flip-flop is used to access a clock signal. The data input D of the first D flip-flop is used for accessing the control voltage signal tih_dvdd. The data output end Q of two adjacent D flip-flops is electrically connected with the data input end D.
Specifically, the second delay subunit 32 includes T cascaded D flip-flops, where T is a positive integer. In the second delay sub-unit 32, the Reset terminals Reset of the b-th D flip-flop are electrically connected to the first delay sub-unit 22 and are used for accessing a modulation delay signal (e.g., a modulation delay signal ring_chan_sel). The clock signal terminals Clk of the b-th D flip-flop are electrically connected to the second frequency-dividing subunit 31 and are configured to receive the second frequency-dividing clock signal (e.g. the second frequency-dividing clock signal clk_ex_dx) output by the second frequency-dividing subunit 31. The data input D of the b-th D flip-flop is used for accessing the control voltage signal tih_dvdd. The data output terminal Q of the b-th D flip-flop is electrically connected to the data input terminal D of the b+1th D flip-flop. Wherein b is a positive integer, and b < T.
In the embodiment of the present application, the modulation delay signals accessed by the second frequency dividing subunit 31 and the second delay subunit 32 may be the same signal. In other embodiments, the modulated delayed signals accessed by the second frequency dividing subunit 31 and the second delay subunit 32 may be different signals.
In this embodiment, the control voltage signal tih_dvdd may be generated by a control voltage circuit. The control voltage circuit is shown with reference to fig. 10. The specific connection mode of the control voltage circuit is as follows: the drain electrode of the switch tube M6 is connected with the power supply voltage DVDD, the source electrode of the switch tube M6 outputs the control voltage signal TIH_DVDD, the source electrode and the grid electrode of the switch tube M7 are electrically connected with the grid electrode of the switch tube M6, and the drain electrode of the switch tube M7 is grounded. Wherein M6 is a PMOS switch tube, and M7 is an NMOS switch tube.
In some embodiments, the second frequency-dividing sub-unit 31 may provide the second frequency-dividing clock signal with an appropriate frequency to the second delay sub-unit 32, and the second delay sub-unit 32 may access a modulation delay signal (e.g. a modulation delay signal ring_chan_sel) to adjust the delay time in the generated adjustment delay signal in coordination with the second frequency-dividing clock signal. For example, after a period of power-up of the power supply VDD, the modulation delay signal ring_chan_sel changes from low level to high level, if the frequency of the second divided clock signal received by the second delay subunit 32 is low, the rising edge frequency encountered by the clock signal terminal Clk of the D flip-flop becomes low in the same time range, so that the delay time of the adjustment delay signal sel_ex becomes long, that is, the time point of the level inversion of the adjustment delay signal sel_ex is delayed backward, that is, it takes a longer time for the adjustment delay signal sel_ex to undergo level inversion.
In some embodiments, referring to fig. 11, the reset signal generating unit 40 may receive the modulation delay signal output by the first adjusting unit 20 and the adjustment delay signal output by the second adjusting unit 30 to perform processing so as to generate the reset signal rst_por in a coupling manner.
In some embodiments, referring to fig. 11, the reset signal generating unit 40 includes an inverting module 41 and a first multiplexer 42 electrically connected.
The inverting module 41 is configured to invert a modulated delayed signal output by the first adjusting unit 20 to obtain an inverted delayed signal.
The first multiplexer 42 is configured to receive a modulated delay signal output by the second adjusting unit 30, an inverted delay signal output by the inverting module 41, and a modulated delay signal output by the first adjusting unit 20, and generate the reset signal rst_por in a coupled manner.
In this embodiment, the modulation delay signal received by the inverting module 41 may be different from the modulation delay signal received by the first multiplexer 42. That is, the reset signal generating unit 40 may receive at least two modulation delay signals output from the first adjusting unit 20 to perform the coupling process. In another embodiment, the modulated delayed signal received by the inverting module 41 may be the same as the modulated delayed signal received by the first multiplexer 42.
Specifically, referring to fig. 11, the inverting module 41 may be electrically connected to the first adjusting unit 20 to receive a modulation delay signal (e.g. a modulation delay signal ring_sel) output by the first adjusting unit 20; the inverting module 41 inverts the modulated delayed signal to obtain an inverted delayed signal (also referred to as an inverted delayed signal). The first multiplexer 42 may be electrically connected to the inverting module 41, the first adjusting unit 20, and the second adjusting unit 30, respectively, to receive the inverted delay signal outputted from the inverting module 41, a modulated delay signal (e.g. the modulated delay signal ring_chan_sel) outputted from the first adjusting unit 20, and an adjusted delay signal (e.g. the adjusted delay signal sel_ex) outputted from the second adjusting unit 30. The first multiplexer 42 processes the received inverse delay signal, the modulated delay signal, and the adjusted delay signal and is coupled to generate the reset signal rst_por. The modulation delay signal (e.g., the modulation delay signal ring_chan_sel) output from the first adjusting unit 20 is used as a control signal of the first multiplexer 42, i.e., is input to a selection terminal of the first multiplexer 42. The inverse delay signal and the adjustment delay signal are input to the input signal terminals of the first multiplexer 42, respectively.
The corresponding circuit module in the circuit system of the present application may receive the reset signal rst_por output by the power-on reset circuit 100, so as to perform a reset action. For example, referring to fig. 14, during power up of the power supply VDD, the reset signal rst_por is at t 0 The corresponding circuit module can execute reset from high to low at any time so as to enable the working state of the circuit module to be in a stable and controllable state; reset signal RST_POR at t 1 The corresponding circuit module realizes the reset by 'low' to 'high' at the moment, namely the power-on reset is completed. In an embodiment of the present application, the corresponding circuit module may be a digital circuit module in a circuit system.
It will be appreciated that referring to fig. 14, the corresponding reset delay time (i.e., t 0 From time to t 1 Time of day) may be determined jointly by the modulated delay signal and the adjusted delay signal received by the reset signal generation unit 40. For example, referring to fig. 11 and 14, the reset start time t of the reset signal rst_por 0 And reset cutoff time t 1 Can be determined by the modulation delay signal RING_SEL, the modulation delay signal RING_CHANSEL and the adjustment delay signal SEL_EXAnd (5) setting.
In some embodiments, referring to fig. 12, the power-on reset circuit 100 may include a clock signal generation unit 50. The clock signal generating unit 50 is electrically connected to the first adjusting unit 20 and the second adjusting unit 30, respectively, to receive a part of the first set of adjusting signals and a part of the second set of adjusting signals for coupling to generate the modulated clock signal clk_por. The corresponding circuit blocks in the circuitry may receive the modulated clock signal clk_por and the reset signal rst_por to effect the reset and reset. It will be appreciated that the corresponding circuit block, while receiving the reset signal rst_por, needs to receive a clock signal to activate the reset or unset function of the circuit. The clock generation module 50 may generate the modulated clock signal clk_por as a clock signal required for the corresponding circuit module. Thus, the modulated clock signal clk_por can control the reset delay time more precisely in cooperation with the reset signal rst_por.
Specifically, the clock signal generating unit 50 is electrically connected to the first target frequency dividing subunit 21, the first delay subunit 22, and the second frequency dividing subunit 32, respectively, to receive a first frequency dividing clock signal (e.g. the first frequency dividing clock signal clk_ring_d2) output by the first frequency dividing subunit 21, a modulation delay signal output by the first delay subunit 22, and a second frequency dividing clock signal (e.g. the second frequency dividing clock signal clk_ex_dx) output by the second frequency dividing subunit. The number of the modulation delay signals received by the clock signal generating unit 50 is at least two (e.g., the modulation delay signal ring_sel and the modulation delay signal ring_clk_sel). The clock signal generating unit 50 generates a modulated clock signal clk_por according to the received first divided clock signal, modulated delay signal, and second divided clock signal, so that the corresponding circuit blocks are reset according to the modulated clock signal clk_por and the reset signal rst_por.
In some embodiments, referring to fig. 13, the clock signal generation unit 50 includes an and gate module 51 and a second multiplexer 52.
The and gate module 51 is electrically connected to the first frequency-dividing subunit 21 and the first delay subunit 22, respectively, for receiving a first frequency-dividing clock signal (e.g. the first frequency-dividing clock signal clk_ring_d2) output by the first frequency-dividing subunit 21 and a modulation delay signal (e.g. the modulation delay signal ring_sel) output by the first delay subunit 22. The and-gate module 51 performs a coupling process (e.g., an and operation) on the received first divided clock signal and the modulation delay signal to generate an initial modulation clock signal clk_ring_d2o.
The second multiplexer 52 is electrically connected to the and gate module 51, the first delay subunit 22 and the second frequency dividing subunit 31, respectively, for receiving the initial modulation clock signal clk_ring_d2o outputted from the and gate module 51, the second frequency dividing clock signal (e.g. the second frequency dividing clock signal clk_ex_dx) outputted from the second frequency dividing subunit 31, and a modulation delay signal (e.g. the modulation delay signal ring_clk_sel) outputted from the first adjusting unit 20. The second multiplexer 52 performs a coupling process on the received initial modulation clock signal clk_ring_d2o, the second divided clock signal, and the modulation delay signal to generate the modulation clock signal clk_por by coupling.
The modulation delay signal (e.g., the modulation delay signal ring_clk_sel) output from the first adjusting unit 20 is used as the control signal of the second multiplexer 52, i.e., is input to the selection terminal of the second multiplexer 52. The initial modulation clock signal clk_ring_d2o and the second divided clock signal may be input to the input signal terminals of the second multiplexer 52, respectively.
In some embodiments, the modulated clock signal CLK_POR may be at t 0 The time is generated to realize the reset of the corresponding circuit block when the reset signal rst_por is set to "low" from "high".
The reset circuit 100 is applied to a circuit system, so that after the power-on reset of the corresponding circuit module in the circuit system is completed, the enable signal en_n is adjusted to control the working state of the oscillating unit 10. For example, reset signal RST_POR is at t 1 When the moment is changed from low to high, the corresponding circuit module realizes reset, namely the power-on reset is completed, and at t 1 After the moment, the controllable enable signal en_n is set to a "high" level, in which case the oscillating unit 10 is not operated, i.e. the clock output associated with the oscillating unit 10 is 0, while the output of the first delay sub-unit 22 may continue to be maintainedHolding; the second frequency dividing subunit 31 is also not operated, i.e. the clock output associated with the external clock signal is 0, while the output of the second delay subunit 32 can be maintained. Thus, the modulated clock signal clk_por is output to 0, and the reset signal rst_por is maintained at a "high" level, so that power consumption can be effectively reduced while the reset signal rst_por is maintained.
In addition, as shown in fig. 15, a power-on reset system 200 is further provided, where the power-on reset system 200 includes a power-on reset circuit 100 and a digital circuit 300, the digital circuit 300 is electrically connected to the power-on reset circuit 100, the power-on reset circuit 100 is configured to generate a reset signal, and the digital circuit 300 is configured to receive the reset signal generated by the power-on reset circuit 100 to perform a reset action.
The division of the various units in the power-on-reset circuit 100 is for illustration only, and in other embodiments, the power-on-reset circuit 100 may be divided into different units as needed to perform all or part of the functions of the power-on-reset circuit 100.
That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, the term "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. A power-on reset circuit, comprising:
an oscillation unit for generating an internal clock signal;
the first adjusting unit is electrically connected with the oscillating unit and is used for receiving an internal clock signal output by the oscillating unit and generating a first group of adjusting signals according to the internal clock signal, wherein the first group of adjusting signals comprise a plurality of modulation delay signals;
The second adjusting unit is respectively and electrically connected with the external clock circuit and the first adjusting unit, and is used for receiving the external clock signal output by the external clock circuit and a modulation delay signal output by the first adjusting unit, adjusting the external clock signal according to the modulation delay signal to generate a second group of adjusting signals, wherein the second group of adjusting signals comprises at least one adjusting delay signal;
the reset signal generating unit is respectively and electrically connected with the first adjusting unit and the second adjusting unit, and is used for receiving at least two modulation delay signals output by the first adjusting unit and one adjustment delay signal output by the second adjusting unit, and generating a reset signal according to the received modulation delay signals and the adjustment delay signals.
2. The power-on reset circuit of claim 1, wherein the first adjustment unit comprises a first frequency-dividing subunit and a first delay subunit electrically connected, the first set of adjustment signals further comprising a plurality of first frequency-dividing clock signals;
the first frequency dividing subunit is used for performing frequency dividing processing on the internal clock signal for a plurality of times to generate a first frequency dividing clock signal in the first group of adjusting signals;
The first delay subunit is configured to delay the first divided clock signal to generate a modulated delayed signal in the first set of adjustment signals.
3. The power-on reset circuit of claim 2, wherein the second adjustment unit comprises a second frequency dividing subunit and a second delay subunit electrically connected, the second frequency dividing subunit and the second delay subunit being electrically connected to the first delay subunit respectively, the second set of adjustment signals further comprising a second frequency dividing clock signal;
the second frequency dividing subunit is configured to receive a modulated delay signal output by the first delay subunit, so as to perform frequency dividing processing on the external clock signal, and generate the second frequency dividing clock signal;
the second delay subunit is configured to receive a modulated delay signal output by the first delay subunit, to delay the second divided clock signal, and to generate an adjustment delay signal in the second set of adjustment signals.
4. The power-on reset circuit of claim 1, wherein the reset signal generation unit comprises an inverting module and a first multiplexer electrically connected;
The inverting module is used for inverting the modulation delay signal output by the first adjusting unit to obtain an inverted delay signal;
the first multiplexer is used for receiving a regulating delay signal output by the second regulating unit, the inverted delay signal output by the inverting module and a modulation delay signal output by the first regulating unit so as to generate the reset signal in a coupling way.
5. The power-on reset circuit of claim 3, further comprising a clock signal generation unit electrically connected to the first frequency divider subunit, the first delay subunit, and the second frequency divider subunit, respectively,
the clock signal generating unit is used for receiving a first frequency division clock signal output by the first frequency division subunit, at least two modulation delay signals output by the first delay subunit and a second frequency division clock signal output by the second frequency division subunit, and generating a modulation clock signal according to the received first frequency division clock signal, the modulation delay signals and the second frequency division clock signal.
6. The power-on reset circuit of claim 5, wherein the clock signal generation unit comprises an and gate module and a second multiplexer electrically connected;
The AND gate module is used for receiving a first frequency division clock signal output by the first frequency division subunit and a modulation delay signal output by the first delay subunit so as to output an initial modulation clock signal;
the second multiplexer is configured to receive the initial modulation clock signal, a modulation delay signal output by the first delay subunit, and a second frequency division clock signal output by the second frequency division subunit, so as to generate the modulation clock signal in a coupling manner.
7. The power-on reset circuit of claim 2, wherein the first frequency dividing subunit comprises a second target frequency dividing subunit and a first target frequency dividing subunit which are electrically connected, wherein the second target frequency dividing subunit and the first target frequency dividing subunit are used for dividing the internal clock signal for a plurality of times so as to sequentially obtain two first frequency dividing clock signals;
the second target frequency dividing subunit is a frequency divider for dividing by two;
the first target frequency dividing subunit comprises a plurality of D triggers which are electrically connected, the reset end of each D trigger is used for being connected with a detection enabling signal, the data input end of each D trigger is electrically connected with the corresponding complementary output end of the D trigger, the clock signal end of the first D trigger is used for being connected with the first frequency dividing clock signal output by the second target frequency dividing subunit, and the data output ends of two adjacent D triggers are electrically connected with the clock signal end.
8. The power-on reset circuit of claim 2, wherein the first delay sub-unit includes a plurality of D flip-flops electrically connected, a reset terminal of each D flip-flop is used for accessing the detection enable signal, a clock signal terminal of each D flip-flop is electrically connected with the first frequency dividing sub-unit and is used for receiving a first frequency dividing clock signal outputted by the first frequency dividing sub-unit, a data input terminal of a first D flip-flop is used for accessing the detection enable signal, and data output terminals of two adjacent D flip-flops are electrically connected with the data input terminal.
9. The power-on reset circuit of claim 3, wherein the second frequency dividing subunit comprises a plurality of D flip-flops electrically connected in sequence, a reset end of each D flip-flop is electrically connected with the first delay subunit and is used for accessing a modulation delay signal, a data input end of each D flip-flop is electrically connected with a complementary output end corresponding to the D flip-flop, a clock signal end of a first D flip-flop is used for accessing the external clock signal, and data output ends of two adjacent D flip-flops are electrically connected with the clock signal end.
10. The power-on reset circuit of claim 3, wherein the second delay sub-unit comprises a plurality of D flip-flops electrically connected, a reset terminal of each D flip-flop is electrically connected with the first delay sub-unit and is used for accessing a modulation delay signal, a clock signal terminal of each D flip-flop is electrically connected with the second frequency division sub-unit and is used for receiving a second frequency division clock signal output by the second frequency division sub-unit, a data input terminal of a first D flip-flop is used for accessing a control voltage signal, and a data output terminal of two adjacent D flip-flops is electrically connected with the data input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310844504.0A CN116566370B (en) | 2023-07-11 | 2023-07-11 | Power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310844504.0A CN116566370B (en) | 2023-07-11 | 2023-07-11 | Power-on reset circuit |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050189970A1 (en) * | 2004-02-26 | 2005-09-01 | Yoshihiro Nakatake | Semiconductor integrated circuit having a power-on reset circuit in a semiconductor memory device |
| JP2005323269A (en) * | 2004-05-11 | 2005-11-17 | Toyota Motor Corp | Reset control circuit |
| JP2010268258A (en) * | 2009-05-15 | 2010-11-25 | Mitsumi Electric Co Ltd | Reset circuit and semiconductor integrated circuit for reset |
| CN108777899A (en) * | 2018-06-26 | 2018-11-09 | 宗仁科技(平潭)有限公司 | Control circuit and lighting system for generating multichannel means of chaotic signals |
| CN110212902A (en) * | 2019-06-28 | 2019-09-06 | 成都信息工程大学 | A kind of electrification reset circuit |
| CN211930610U (en) * | 2020-01-31 | 2020-11-13 | 杭州士兰微电子股份有限公司 | Power-on reset circuit |
| CN115622505A (en) * | 2022-10-08 | 2023-01-17 | 荣湃半导体（上海）有限公司 | Signal modulation circuit and digital signal transmission system |
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2023
- 2023-07-11 CN CN202310844504.0A patent/CN116566370B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050189970A1 (en) * | 2004-02-26 | 2005-09-01 | Yoshihiro Nakatake | Semiconductor integrated circuit having a power-on reset circuit in a semiconductor memory device |
| JP2005323269A (en) * | 2004-05-11 | 2005-11-17 | Toyota Motor Corp | Reset control circuit |
| JP2010268258A (en) * | 2009-05-15 | 2010-11-25 | Mitsumi Electric Co Ltd | Reset circuit and semiconductor integrated circuit for reset |
| CN108777899A (en) * | 2018-06-26 | 2018-11-09 | 宗仁科技(平潭)有限公司 | Control circuit and lighting system for generating multichannel means of chaotic signals |
| CN110212902A (en) * | 2019-06-28 | 2019-09-06 | 成都信息工程大学 | A kind of electrification reset circuit |
| CN211930610U (en) * | 2020-01-31 | 2020-11-13 | 杭州士兰微电子股份有限公司 | Power-on reset circuit |
| CN115622505A (en) * | 2022-10-08 | 2023-01-17 | 荣湃半导体（上海）有限公司 | Signal modulation circuit and digital signal transmission system |
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| CN116566370B (en) | 2024-01-30 |
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