CN115622505A - Signal modulation circuit and digital signal transmission system - Google Patents
Signal modulation circuit and digital signal transmission system Download PDFInfo
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- CN115622505A CN115622505A CN202211222558.5A CN202211222558A CN115622505A CN 115622505 A CN115622505 A CN 115622505A CN 202211222558 A CN202211222558 A CN 202211222558A CN 115622505 A CN115622505 A CN 115622505A
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Abstract
The invention relates to the technical field of signal modulation circuits, in particular to a signal modulation circuit and a digital signal transmission system, which comprise a delay module, a clock modulation module and an AND gate module which are sequentially arranged along a signal transmission direction; the delay module is used for generating a delay signal according to the original signal received by the signal modulation circuit; the clock modulation module is used for generating an intermediate modulation signal according to the delay signal; the AND gate module is respectively connected with the delay module and the clock modulation module, and is used for generating a transmitting modulation signal according to the delay signal and the intermediate modulation signal. Has the advantages that: by introducing the delay module, the problem that the high-level narrow pulse width is smaller than the bandwidth of a signal transmission system in the prior art cannot occur in the finally output modulation signal by adding delay in the signal before generating the clock signal, so that the problem of pulse width distortion is avoided.
Description
Technical Field
The invention relates to the technical field of signal modulation circuits, in particular to a signal modulation circuit and a digital signal transmission system.
Background
A signal modulation circuit is a signal processing circuit applied to a communication system. In a communication system, the influence of factors such as a transmission medium and a transmission mode is limited, and a relatively low-frequency original signal is generally required to be processed by a signal modulation circuit to obtain a modulated signal, so that signal loss caused in a transmission process is reduced.
In the prior art, there are many schemes for signal modulation circuits in digital communication systems. As shown in fig. 1, fig. 1 is a typical signal modulation circuit, which has an oscillation generator Q1 and an and gate Q2, wherein the oscillation generator Q1 is driven by an input signal to transmit a specific clock signal CLK as an output, and the and gate Q2 determines an output modulation signal MOD according to the input signal and the clock signal CLK. The signal is modulated by setting the oscillation generator Q1 with a high oscillation frequency, and then transmitted to the receiving side through the signal transmission system of the subsequent stage.
However, in practical implementation, the inventor finds that, in the case of the signal modulation circuit shown in fig. 2, when the falling edge of the input signal is at t1, the output pulse width tp1 of the output modulated signal is smaller than the bandwidth te of the entire signal transmission system, and at this time, the last falling edge of the modulated signal MOD may be lost by the output signal SIG of the signal transmission system, which causes an error in the OUT output signal demodulated by the receiving side. In response to this problem, a narrow pulse width widening technique exists in the prior art, which is used to widen the narrow pulse width of the last falling edge to the size of the bandwidth te in the signal transmission system, so that the signal transmission system can respond normally. However, this scheme may cause the width of the signal to vary, causing pulse width distortion problems.
Disclosure of Invention
In view of the above problems in the prior art, a signal modulation circuit is provided; in another aspect, a digital signal transmission system using the signal modulation circuit is also provided.
The specific technical scheme is as follows:
a signal modulation circuit comprises a delay module, a clock modulation module and an AND gate module which are sequentially arranged along a signal transmission direction;
the delay module is used for generating a delay signal according to the original signal received by the signal modulation circuit;
the clock modulation module is used for generating an intermediate modulation signal according to the delay signal;
the AND gate module is respectively connected with the delay module and the clock modulation module, and is used for generating a transmitting modulation signal according to the delay signal and the intermediate modulation signal.
In another aspect, the clock modulation module includes:
the input end of the clock generation module is a first input end of the clock modulation module;
the clock generation module generates a clock signal according to the delay signal;
a first input end of the decision circuit is connected to an output end of the clock generation module, a second input end of the decision circuit is a second input end of the clock modulation module, and the second input end of the clock modulation module is used for receiving the original signal;
the decision circuit generates the intermediate modulation signal from the original signal and the clock signal.
On the other hand, the clock generation module comprises an oscillator, and an enable pin of the oscillator is connected with an input end of the clock generation module to generate the clock signal under the control of the delay signal;
the width of the low-level pulse width of the clock signal is less than half of the phase difference between the delayed signal and the original signal.
In another aspect, the decision circuit includes:
a first input end of the inverting module is connected with a first input end of the judging circuit, and a second input end of the inverting module is connected with a second input end of the judging circuit;
the setting end of the RS trigger is connected with the first output end of the reversing module, the resetting end of the RS trigger is connected with the second output end of the reversing module, and the output end of the RS trigger is connected with the output end of the judging circuit.
In another aspect, the reversing module includes:
the input end of the first phase inverter is connected with the first input end of the inversion module, and the output end of the first phase inverter is connected with the first output end of the inversion module;
and the input end of the second phase inverter is connected with the first input end of the reversing module, and the output end of the second phase inverter is connected with the second output end of the reversing module.
On the other hand, the RS trigger comprises a first AND gate and a second AND gate;
the first input end of the first AND gate is connected with the first input end of the RS trigger, the output end of the first AND gate is the output end of the RS trigger, and the output end of the first AND gate is connected with the first input end of the second AND gate;
and the second input end of the second AND gate is connected with the second input end of the RS trigger, and the output end of the second AND gate is connected with the second input end of the first AND gate.
A digital signal transmission system for implementing the signal modulation circuit, comprising:
the transmitting module is provided with the signal modulation circuit and receives an original signal and generates a transmitting modulation signal through the signal modulation circuit;
the receiving module is connected to the transmitting module through a signal transmission system so as to receive the transmitting modulation signal;
the receiving module is provided with a signal demodulation circuit which demodulates the transmitting modulation signal to obtain a demodulation signal corresponding to the original signal.
On the other hand, the bandwidth of the signal transmission system is less than half the delay time period in the signal modulation circuit.
The technical scheme has the following advantages or beneficial effects: by introducing the delay module, the problem that the high-level narrow pulse width is smaller than the bandwidth of a signal transmission system in the prior art cannot occur in the finally output modulation signal by adding the delay into the signal before generating the clock signal, so that the problem that the signal transmission system in the prior art can cause triggering errors due to the narrow pulse width is avoided.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a schematic diagram of a prior art signal modulation circuit;
FIG. 2 is a timing diagram of a prior art signaling system;
FIG. 3 is a functional block diagram of an embodiment of the present invention;
FIG. 4 is a signal diagram illustrating an embodiment of the present invention;
FIG. 5 is a signal diagram illustrating another embodiment of the present invention;
FIG. 6 is a signal diagram illustrating another embodiment of the present invention;
FIG. 7 is a signal diagram illustrating another embodiment of the present invention;
fig. 8 is a schematic diagram of a digital signal transmission system according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention comprises the following steps:
a signal modulation circuit, as shown in FIG. 3, includes a Delay module Delay, a clock modulation module and an AND gate module sequentially arranged along a signal transmission direction;
the Delay module Delay is used for generating a Delay signal IN _ Delay according to the original signal IN received by the signal modulation circuit;
the clock modulation module mo is used for generating an intermediate modulation signal CLK _ O according to the delay signal IN _ delay;
the and gate module and2 is respectively connected to the Delay module Delay and the clock modulation module mo, and the and gate module and2 is configured to generate the transmission modulation signal MOD according to the Delay signal IN _ Delay and the intermediate modulation signal CLK _ O.
Specifically, in the embodiment, a Delay module Delay is arranged in the signal modulation circuit to add Delay to the signal and control the Delay duration to be not less than the bandwidth of the signal transmission system, so that the width of the last 1 pulse width of the output signal is greater than the bandwidth of the signal transmission system, and the problem of the error of the signal transmission system is avoided.
In the implementation process, as shown in fig. 4, in order to make the width of the last 1 pulse width of the output signal MOD larger than the bandwidth te of the signal transmission system, the controllable delay time length is larger than te, so that the last 1 pulse width of the transmission modulation signal MOD output by the and gate module and2 does not fall into the window of the bandwidth te, and further the signal SIG output by the signal transmission system does not make an error.
In one embodiment, the clock modulation module mo further includes a second input terminal, and the second input terminal of the clock modulation module mo is connected to the input terminal of the signal modulation circuit;
the clock modulation module mo further includes:
the input end of the clock generation module OSC is a first input end of the clock modulation module mo;
the clock generation module OSC generates a clock signal CLK according to the delay signal IN _ delay;
a first input end of the decision circuit dec is connected to an output end of the clock generation module OSC, and a second input end of the decision circuit dec is a second input end of the clock modulation module mo;
the decision circuit dec generates an intermediate modulation signal CLK _ O from the original signal IN and the clock signal CLK.
Specifically, IN this embodiment, a clock generation module OSC and a decision circuit dec are respectively disposed IN the clock modulation module mo, wherein the clock generation module is configured to modulate the delay signal IN _ delay to convert the delay signal into a clock signal CLK with a higher frequency, and then the decision circuit dec decides the clock signal CLK according to the input original signal IN and locks the decision circuit dec through the original signal IN, so that the 0 narrow pulse width generated by the clock signal is not output to the modulation signal, thereby avoiding the influence of the 0 narrow pulse width signal on the signal transmission system.
Specifically, after the Delay module Delay is introduced, although the problem that the 1 pulse width of the transmission modulation signal MOD causes an error IN the signal transmission system is avoided, as shown IN fig. 5, if the falling edge of IN falls IN the last 0 pulse width of CLK, a 0 narrow pulse width tp0< te is caused, the transmission signal system loses the last one, the SIG circuit does not have an error state that the output is 1 all the time, but pulse width distortion of the size of te + tp0 is introduced.
To solve this problem, in this embodiment, a 0 decision circuit is introduced to eliminate the pulse width distortion, which is specifically as follows:
IN one embodiment, the clock generation module OSC includes an oscillator, an enable pin of which is connected to an input terminal of the clock generation module to generate the clock signal CLK under the control of the delay signal IN _ delay;
the bandwidth te of the signal transmission system is less than half the phase difference between the delayed signal IN _ delay and the original signal IN.
Specifically, for the problem of transmission error caused by the narrow pulse width formed after the modulation signal is added with the high frequency component or the problem of pulse width distortion caused by the narrow pulse widening technique IN the signal transmission system IN the prior art, IN this embodiment, the delay length of the delay signal IN _ delay is set to be twice the bandwidth te of the signal transmission system, that is, 2te, so that the output of the modulation signal is not affected by the narrow pulse width IN the finally output signal, and the problem of transmission error is avoided.
Specifically, taking fig. 6 as an example, IN this embodiment, the falling edge of the original signal IN is IN the modulation 0 pulse width of the clock signal CLK.
IN this embodiment, when the original signal IN is input to 0, the delayed signal IN _ delay is 0, the clock signal CLK outputs 1, the intermediate modulation signal CLK _ O outputs 1, the setting signal CLKB _ O outputs 0, and the transmission modulation signal MOD outputs 0;
when the original signal IN input is toggled to 1, the set signal CLKB _ O toggles to 1. At this time, the delay time length 2te has not been reached, the output of the delay signal IN _ delay is still 0, the output of the middle modulation signal CLK _ O is 1, and the output of the transmission modulation signal MOD is 0, that is, there is no output.
When the original signal IN keeps the input at 1 and reaches the delay time duration 2te, the output of the delay signal IN _ delay is inverted to 1, so that the clock generation module OSC starts oscillating, and outputs the clock signal CLK with the pulse width of 0 having a specific frequency after a certain time. At this time, since the set signal CLKB _ O keeps being output as 1 by the original signal IN, the intermediate modulation signal CLK _ O starts outputting the intermediate modulation signal CLK _ O corresponding to the clock signal CLK according to the input inverted clock signal CLKB.
Meanwhile, while the output of the delay signal IN _ delay is inverted to 1 and the 0 pulse width of the clock signal CLK is not yet output, the and gate module and2 receives the delay signal IN _ delay whose output is 1 and the intermediate modulation signal CLK _ O whose output is 1, and the transmission modulation signal MOD is inverted to 1, indicating that the transmission side starts transmitting the transmission modulation signal MOD. Then, the corresponding transmission modulation signal MOD is output starting following the 0 pulse width part in the intermediate modulation signal CLK _ O.
When the input of the original signal IN is finished and the signal is turned to 0, because the setting signal CLKB _ O is turned to 0 along with the original signal, the output of the middle modulation signal CLK _ O is locked to 1 at this time, and the output of the emission modulation signal MOD is 0, the clock signal CLK output IN any time period thereafter does not affect the output of the middle modulation signal CLK _ O no matter any position of the falling edge IN the delay time length 2te, so that the blocking of the narrow pulse width of 0 is realized, and the influence of the narrow pulse width of 0 to a subsequent signal transmission system is avoided.
IN another embodiment as shown IN fig. 7, the falling edge of the delayed signal IN _ delay is IN the modulation 0 pulse width of the clock signal CLK.
IN this embodiment, when the original signal IN is input to 0, the delay signal IN _ delay is 0, the clock signal CLK outputs 1, the intermediate modulation signal CLK _ O outputs 1, the setting signal CLKB _ O outputs 0, and the emission modulation signal MOD outputs 0;
when the original signal IN input toggles to 1, the set signal CLKB _ O toggles to 1. At this time, if the delay time length 2te has not been reached, the output of the delay signal IN _ delay is still 0, the output of the intermediate modulation signal CLK _ O is 1, and the output of the transmission modulation signal MOD is 0, that is, there is no output.
When the original signal IN keeps the input at 1 and reaches the delay time duration 2te, the output of the delay signal IN _ delay is inverted to 1, so that the clock generation module OSC starts oscillating, and outputs the clock signal CLK with the pulse width of 0 having a specific frequency after a certain time. At this time, since the set signal CLKB _ O keeps being output as 1 by the original signal IN, the intermediate modulation signal CLK _ O starts outputting the intermediate modulation signal CLK _ O corresponding to the clock signal CLK according to the input inverted clock signal CLKB.
Meanwhile, while the output of the delay signal IN _ delay is inverted to 1 and the 0 pulse width of the clock signal CLK is not yet output, the and gate module and2 receives the delay signal IN _ delay whose output is 1 and the intermediate modulation signal CLK _ O whose output is 1, and the transmission modulation signal MOD is inverted to 1, indicating that the transmission side starts transmitting the transmission modulation signal MOD. Then, the corresponding transmission modulation signal MOD is output starting following the 0 pulse width part in the intermediate modulation signal CLK _ O.
When the original signal IN is inverted to 0 after being input, if the output of the clock signal CLK is 0 at this time, the output of the intermediate modulation signal CLK _ O is 0, and due to the characteristics of the RS flip-flop, the output of the setting signal CLKB _ O is maintained at 1 until the output of the clock signal CLK is 1, and is inverted to 0, and the intermediate modulation signal CLK _ O is locked to 1.
That is, when the falling edge of the original signal IN is at 0 pulse width of the clock signal CLK, the intermediate modulation signal CLK _ O outputs a complete 0 pulse width and becomes 1. Finally, the minimum 0 pulse width output by the emission modulation signal MOD is te, the minimum 1 pulse width is te + tp0, and when tp0 is close to 0, the minimum 1 pulse width is te. The bandwidth te of the signal transmission system is obviously met, and transmission errors cannot occur in the transmission process.
Further, after filtering all 0 pulse widths of the signal by a demodulation circuit on the receiving side behind the signal transmission system, comparing the signal with the original signal IN, it can be found that the width is the same as the original signal IN, and the pulse width distortion is 0.
In one embodiment, the decision circuit dec includes:
a first input end of the reverse module inv is connected with a first input end of the decision circuit dec, and a second input end of the reverse module inv is connected with a second input end of the decision circuit dec;
the setting end of the RS trigger RS is connected with the first output end of the reverse module inv, the resetting end of the RS trigger RS is connected with the second output end of the reverse module inv, and the output end of the RS trigger RS is connected with the output end of the decision circuit dec.
Specifically, for the problem that the pulse width distortion may be caused in the transmission process of the signal modulation circuit in the prior art, in this embodiment, the RS flip-flop RS is set in the decision circuit dec to determine the locking condition of the intermediate modulation signal CLK _ O according to the reverse input signal INB, so as to achieve better interception and processing of the 0-narrow pulse width, and further avoid the problem of error of the signal transmission system.
In one embodiment, the reversing module inv comprises:
the input end of the first phase inverter inv1 is connected with the first input end of the inversion module inv, and the output end of the first phase inverter inv1 is connected with the first output end of the inversion module inv;
an input end of the second inverter inv2 is connected with a first input end of the inverting module inv, and an output end of the second inverter inv2 is connected with a second output end of the inverting module inv.
In one embodiment, the RS flip-flop RS includes a first and gate nand2_1 and a second and gate nand2_2;
a first input end of the first AND gate nand2_1 is connected with a first input end of the RS trigger RS, an output end of the first AND gate nand2_1 is an output end of the RS trigger RS, and an output end of the first AND gate nand2_1 is connected with a first input end of the second AND gate nand2_2;
the second input terminal of the second and gate nand2_2 is connected to the second input terminal of the RS flip-flop RS, and the output terminal of the second and gate nand2_2 is connected to the second input terminal of the first and gate nand2_ 1.
A digital signal transmission system for implementing the signal modulation circuit described above, as shown in fig. 7, includes:
the device comprises a transmitting module A1, wherein a signal modulation circuit A11 is arranged in the transmitting module A1, and the transmitting module A1 receives an original signal and generates a transmitting modulation signal through the signal modulation circuit A11;
the receiving module A3 is connected to the transmitting module A1 through a signal transmission system A2 so as to receive the transmitting modulation signal;
the receiving module A3 is provided therein with a signal demodulation circuit a31, and the signal demodulation circuit a31 demodulates the transmission modulated signal to obtain a demodulated signal corresponding to the original signal.
In one embodiment, the bandwidth of the signal transmission system A2 is less than half the delay time duration in the signal modulation circuit a 11.
Specifically, for a digital signal transmission system in the prior art, when a digital signal is transmitted, a transmission system error is easily caused due to a narrow pulse width at the end of a high-frequency signal, or a problem of pulse width distortion is caused due to the introduction of a narrow pulse width widening technology, in this embodiment, a signal modulation circuit a11 is arranged to process the signal, and a delay time in the signal modulation circuit a11 is controlled to be twice or more than that of the signal transmission system, so that the signal modulation circuit a11 can modulate the signal without introducing pulse width distortion, and a problem of transmission error of a signal transmission system A2 at a later stage is avoided.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A signal modulation circuit is characterized by comprising a delay module, a clock modulation module and an AND gate module which are sequentially arranged along a signal transmission direction;
the delay module is used for generating a delay signal according to the original signal received by the signal modulation circuit;
the clock modulation module is used for generating an intermediate modulation signal according to the delay signal;
the AND gate module is respectively connected with the delay module and the clock modulation module, and is used for generating a transmitting modulation signal according to the delay signal and the intermediate modulation signal.
2. The signal modulation circuit of claim 1, wherein the clock modulation module comprises:
the input end of the clock generation module is a first input end of the clock modulation module;
the clock generation module generates a clock signal according to the delay signal;
a first input end of the decision circuit is connected to an output end of the clock generation module, a second input end of the decision circuit is a second input end of the clock modulation module, and the second input end of the clock modulation module is used for receiving the original signal;
the decision circuit generates the intermediate modulation signal from the original signal and the clock signal.
3. The signal modulation circuit according to claim 2, wherein the clock generation module comprises an oscillator, and an enable pin of the oscillator is connected to an input terminal of the clock generation module to generate the clock signal under the control of the delay signal.
4. The signal modulation circuit of claim 2, wherein the decision circuit comprises:
a first input end of the inverting module is connected with a first input end of the judging circuit, and a second input end of the inverting module is connected with a second input end of the judging circuit;
the setting end of the RS trigger is connected with the first output end of the reverse module, the resetting end of the RS trigger is connected with the second output end of the reverse module, and the output end of the RS trigger is connected with the output end of the judgment circuit.
5. The signal modulation circuit of claim 4, wherein the inverting module comprises:
the input end of the first phase inverter is connected with the first input end of the inversion module, and the output end of the first phase inverter is connected with the first output end of the inversion module;
and the input end of the second phase inverter is connected with the first input end of the inversion module, and the output end of the second phase inverter is connected with the second output end of the inversion module.
6. The signal modulation circuit of claim 4, wherein the RS flip-flop comprises a first AND gate and a second AND gate;
the first input end of the first AND gate is connected with the first input end of the RS trigger, the output end of the first AND gate is the output end of the RS trigger, and the output end of the first AND gate is connected with the first input end of the second AND gate;
and the second input end of the second AND gate is connected with the second input end of the RS trigger, and the output end of the second AND gate is connected with the second input end of the first AND gate.
7. A digital signal transmission system for implementing the signal modulation circuit of any one of claims 1-6, comprising:
the transmitting module is provided with the signal modulation circuit and receives an original signal and generates a transmitting modulation signal through the signal modulation circuit;
the receiving module is connected to the transmitting module through a signal transmission system so as to receive the transmitting modulation signal;
the receiving module is provided with a signal demodulation circuit which demodulates the transmitting modulation signal to obtain a demodulation signal corresponding to the original signal.
8. The digital signal transmission system of claim 7, wherein the bandwidth of the signal transmission system is less than half the time delay duration in the signal modulation circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
| CN116566370B (en) * | 2023-07-11 | 2024-01-30 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
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