RU2284668C1 - Start-stop communication system - Google Patents

Abstract

FIELD: electric and radio communications engineering, possible use in wired, radio, radio-relay and space communication systems.

SUBSTANCE: in the system, depending on value of modulus two sum of n information symbols at output of pseudo-random series generator, used for modulation of signal at output of transmitting side of system are two different - with different starting phases - pseudo-random series. At receiving side of system, composition of which includes pseudo-random series generator, analogical to pseudo-random series generator on transmitting side, and depending on correlation with first or second pseudo-random series, original modulus two sum is determined and compared to one that have been actually received. On basis of comparison results further processing of information is either permitted or not permitted.

EFFECT: increased probability of correct receipt of messages.

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Description

The invention relates to electrical and radio communications and can be used in wired, radio, radio relay and space communication systems.

A well-known start-stop communication system (Z.M. Kanevsky, V.I. Ledovskikh "Transfer of discrete messages on channels with feedback with interruptions", Elektrosvyaz, 1970, No. 8, p.6-8), in which before sending a message is transmitted " sounding key ", which is an amplitude-manipulated signal consisting of several elements. However, this system is designed specifically for channels with interruptions (freezing channels), has low noise immunity in the general case, and a high level of probability of false alarm.

Closest to the technical nature of the proposed is a start-stop communication system, given in [1], adopted as a prototype.

The functional diagram of the prototype device is shown in figure 1, where indicated

on the transmitting side:

1 - source of information;

2 - shift register;

3 - multiplexer;

4 - relatively phase manipulator;

5 - transmitter;

6 - the first clock generator;

7 - pseudo-random sequence generator;

8 - multiplier;

9 - binary counter;

10 - carrier frequency generator;

11 - key;

on the receiving side:

12 - receiver;

13 - matched filter;

14 - sync block;

15 - demodulator;

16 - storage unit;

17 - second clock generator;

18 - delay line;

19 - communication line.

The prototype device contains on the transmitting side a series-connected information source 1, a shift register 2, a multiplexer 3, a relative phase manipulator 4 and a transmitter 5. In addition, a first clock generator 6, a pseudo-random sequence generator 7, a multiplier 8 and a binary counter 9 are connected in series ; serially connected carrier frequency generator 10 and key 11, the output of which is connected to the signal input relative to the phase manipulator 4. The input of the clock pulse generator 6 is connected to the clock output of the information source 1, the second output of the generator 6 is connected to the clock input of the shift register 2, and the third output of the generator 6 - with the second inputs of the pseudo-random sequence generator 7 and the multiplier 8, the output of which is also connected to the control inputs of the block 4 and the key 11. Moreover, the first output of the generator 6 is connected to the nym input binary counter 9 which outputs are connected to the control bus of the multiplexer 3 inputs.

On the receiving side, it contains a receiver 12 connected in series, a matched filter 13, a sync block 14, a demodulator 15 and a storage unit 16, the output of which is the output of the device, and a second clock generator 17, the input of which is connected to the output of the sync block 14, the first output is connected to the second input the storage unit 16, and the second output with the corresponding inputs of the demodulator 15 and the storage unit 16. In addition, the output of the matched filter 13 through the delay line 18 is connected to the third input of the demodulator 15. The transmitting and riemnaya side are connected via communication lines 19. (Here the device 14 - combined sync block units 14, 15, 16, 17, 18 and 19 of the prototype device [1]).

Start-stop communication system operates as follows.

At a random moment in time, at the output of information source 1, n information symbols (“0” or “1”) of duration τ are created.

When t = 0, n clock pulses are formed at the second output of clock generator 6, which are equal to the number of pseudorandom sequence elements (PSP) that write information symbols in shift register 2, a short pulse is created at its first output, on the leading edge of which the generator is initially set pseudo-random sequence 7 and setting all the bits of the binary counter 9 to a single state, and on the third output, a meander consisting of (n + 1 + S) pulses of duration τ / 2 (where S is the number of PSP level moves from positive to negative to positive value), which in block 8 is multiplied with a pseudo-random sequence of the same length coming from the output of the generator 7.

The positive part of the resulting signal coming from the output of block 8 is used to control the operation of blocks 9, 4 and key 11. At the moment of the leading edge of its first pulse, block 9 is set to zero, key 11 is opened, which allows carrier frequency oscillations to block 4 , and from the output of the multiplexer 3 to the input of block 4 receives a zero signal. As a result of this, oscillations of the carrier frequency with an arbitrary initial phase during the time interval τ / 2 are formed at the output of block 4. Upon receipt of the second positive edge of the signal in the counter 9, a binary number equal to one is set, and the multiplexer 3 reads from the shift register 2 the value of the first information symbol. In this case, the initial phase of the carrier frequency at the output of block 4 remains the same if the first character has a value of unity, and changes to the opposite - otherwise. Thus, at the output of block 4, a relatively phase-shifted signal of duration T is created in which the first radio pulse does not carry information, but serves as a reference for the second radio information pulse.

On the receiving side, relative to the phase-shifted signal after general filtering in the receiver 12 and matched in the filter 13 for a single radio pulse of duration τ / 2, it is supplied to the sync block 14, at the output of which a short pulse is generated at a time corresponding to the end of the signal when receiving T.

In block 15, demodulation of the filter 13 coming from the output and delayed in the delay line 18 by the time T of the signal is carried out. If neighboring radio pulses have the same initial phases, then the symbol "1" is formed at its output, otherwise - "0". The start of operation of block 15 determines the pulse coming from the sync block 14, and the moments of comparison of the phases of the adjacent radio pulses determine the leading edges of the pulses coming from the second output of the generator 17. The decision is made to receive symbols and fix them in the memory block 16 on the trailing edges of these pulses. from block 16 to the output of the system is carried out by pulses from the first output of the generator 17.

The disadvantage of the prototype device is the low probability of correctly receiving the message.

To eliminate this drawback, a device containing on the transmitting side a series-connected information source, a shift register, a multiplexer and a transmitter, in addition, a first clock pulse generator (GTI), a series-connected pseudo-random sequence generator (GPS), a multiplier and a binary counter; serially connected carrier frequency generator (LFO) and a key whose output is connected to the signal input relative to the phase manipulator (OFM), the input of the first GTI is connected to the clock output of the information source, the second output of the first GTI is connected to the clock input of the shift register, and its third output is connected to the second inputs of the GPS and multiplier, the output of which is also connected to the control inputs of the OFM and the key, and the first output of the first GTI is connected to the installation input of the binary counter, the outputs of which are connected to the control bus multiplexer inputs; on the receiving side: a receiver connected in series, a matched filter and a sync block, a demodulator and a storage unit connected in series, the output of which is the output of the device, and a second GTI, the first output of the second GTI connected to the second input of the storage unit, its second output connected to the corresponding inputs of the demodulator and the storage unit, in addition, the output of the matched filter through the delay line is connected to the third input of the demodulator, while the transmitting and receiving sides are connected via of the communication line, the third GPS input was introduced on the transmitting side, the first adder modulo two and the first and second “I” circuits, the first inputs of which are combined and connected to the first output of the first GTI, and the second one are connected, respectively, to the direct and inverse the outputs of the first adder are two modulo, and the outputs of the first and second “I” circuits are connected one at a time to the first and third GPS inputs, and the inputs of the first adder are two modulo connected by a bus to the outputs (bus) of the shift register; on the receiving side, the second input of the second GTI, the control outputs (bus) of the storage unit, the OR circuit and the pulse shaper, the second synchro block, the second adder modulo two, the third I circuit and the RS-trigger, the first inputs of the second modulo two adders are connected by a bus to the control outputs of the storage unit, and the last one is connected to the RS-trigger output, the first and second inputs of the third “I” circuit are connected one at a time to the outputs of the second adder modulo two and a pulse shaper, the first and the second inputs of the second GTI, the OR circuit, and the RS flip-flop are connected respectively to the outputs of the first and second sync blocks, the input of the second sync block is connected to the output of the matched filter, and the output of the OR circuit is also connected to the first input of the demodulator; the output of the third circuit "AND" is an additional output of the device.

Figure 2 presents the functional diagram of the proposed device.

It contains on the transmitting side a series-connected information source 1, a shift register 2, a multiplexer 3, OFM 4 and a transmitter 5. In addition, a first GTI 6, a first I circuit 7, GPS 8, a multiplier 9 and a binary counter 10 are connected in series; a series-connected LFO 11 and a key 12, the output of which is connected to the signal input OFM 4, the first adder modulo two 13 and the second circuit "I" 14. The input of the first GTI 6 is connected to the clock output of the information source 1, the second output of the GTI 6 is connected to the clock input shift register 2, the third output of the GTI 6 is connected to the second inputs of the GPSSP 8 and the multiplier 9, and the first is also connected to the first input of the second circuit "I" 14 and the installation input of the binary counter 10, the outputs of which are connected by a bus to the control inputs of the multiplexer 3. Moreover, the output multiplier 9 s it is also one with the control inputs of OFM 4 and key 12, the output of the second “I” circuit 14 is connected to the third input of GPS 8, the inputs of the first adder modulo two 13 are connected by a bus to the outputs (output bus) of shift register 2, and its direct and inverse outputs connected one at a time to the second inputs of the first 7 and second 14 of the "And" circuits.

At the receiving side, it contains a receiver 15 connected in series, a matched filter 16, a first synchro block 17, an OR circuit 18, a demodulator 19, a memory block 20, a second adder modulo two 21 and a third I circuit 22, a second synchro block 23, and a second GTI 24, the first output of which is connected to the second input of the storage unit 20, and the second to the corresponding inputs of the demodulator 19 and the storage unit 20, a delay line 25 connected by the output to the third input of the demodulator 19, an RS-trigger 25, the output of which is connected to the last input of the second adder there are two 21 modules and a pulse shaper 27, the output of which is connected to the second input of the third AND circuit 22, and the input is connected to the output of the OR circuit 18, with the first and second inputs of the OR circuit 18, the second GTI 24 and RS flip-flops 26 are connected respectively to the outputs of the first and second sync blocks 17 and 23, and the output of the matched filter 16 is also connected to the inputs of the second sync block 23 and delay line 25; the output of the device is the output of the storage unit 20, an additional output is the output of the third AND circuit 22. The transmitting and receiving sides of the device are connected via a communication line 28.

Start-stop communication system operates as follows. At a random moment in time, at the output of information source 1, n information symbols (“0” or “1”) of duration τ are created. When t = 0, n clock pulses are generated at the second output of clock generator 6, which record information symbols in shift register 2, the outputs of n bits of which are connected by bus to the information inputs of multiplexer 3 and the inputs of the first adder modulo two 13. At the first output of generator 6 through the time interval τ / 2 after the last clock pulse, a short pulse is created. If the sum of all information symbols modulo two has a value of "1", then this pulse is supplied through the circuit "And" 7 to the first input of the GPS 8, where the latter is installed on its leading edge in the first initial state, if the sum is "0 ", Then the output pulse of block 6 enters through the second circuit" And "14 to the third input of the GPS 8 and it is set to another initial state. On the same leading edge, the initial installation of all bits of the binary counter 10 is in a single state. At the third output of block 6, a meander of duration T is formed, consisting of (n + 1 + S) pulses of duration τ / 2, which in block 9 is multiplied with the first (or second) pseudorandom sequence of the same length coming from the output of GPS 8.

The positive part of the resulting signal coming from the output of the multiplier 9 is used to control the operation of blocks 4, 10 and key 12. At the moment of the leading edge of its first pulse, block 10 is set to zero, a key 12 is opened, which allows carrier frequency oscillations to block 4 , and from the output of the multiplexer 3 to the input of block 4 receives a zero signal. As a result of this, oscillations of the carrier frequency with an arbitrary initial phase during the time interval τ / 2 act at the output of the latter. When a second positive edge arrives, counter 10 sets a binary number equal to one, and multiplexer 3 reads the value of the first information symbol from the shift register. In this case, the initial phase of the carrier frequency at the output of block 4 remains the same if the first symbol has a value of unity, and changes to the opposite otherwise. Those. at the output of block 4, a relatively phase-shifted signal is generated in which the first radio pulse does not carry information, but serves as a reference for the second radio information pulse.

Thus, the difference here from the prototype device is only in that, depending on the value of the modulo two n information symbols, the first or second (different from the first) pseudo-random sequence is formed at the output of the GPS 8.

On the receiving side, a relatively phase-shifted signal after common filtering in the receiver 15 and matched in the filter 16 for a single radio pulse of duration τ / 2 is processed in sync blocks 17 and 23, the first of which is optimal for the first pseudorandom sequence and the second for another pseudorandom sequence different from the first . Depending on the sum modulo two n information symbols at the time T at the output of one of the sync blocks, a short clock pulse is generated, which through the "OR" circuit 18 enters the first input of the demodulator 19 and the input of the pulse former 27, and at the second input of the GTI 24 or another sequence of short pulses.

In block 19, demodulation of the filter 16 coming from the output and delayed in the delay line 25 by the time T of the signal is carried out. The pulse at the first input of block 19 determines the beginning of its operation, and the leading edges of the pulses coming from the second output of the GTI 24 determine the phases of the comparison of phases of neighboring radio pulses. If neighboring radio pulses have the same initial phases, then the symbol "1" is formed at its output, otherwise - "0". On the trailing edges of these pulses, a decision is made on the reception of symbols and their fixation in the storage unit 20. Reading information from block 20 through its output to the input of the information receiver (for example, a digital computer; not shown in Fig. 2) is carried out by pulses from the first output GTI 24. In the adder 21, the modulo two information symbols received in block 20 are added and the output signal of block 24. If, for example, the sum value turns out to be 1, then in the absence of interference in the communication channel, the signal l 1, and at the output of block 21 - logical 0. In this case, a short pulse acting at the output of the driver 27, corresponding in time to the trailing edge of the last pulse at the second output of the GTI 24, will not pass through the circuit 22 and at its output (additional output of the device) a logic 0 signal will be enabled, allowing the reception of a message in the information receiver. If, in the presence of interference in the received message, errors of odd multiplicity occur, then a positive signal will appear at the output of block 21, and a positive pulse will appear at the output of block 22, which prohibits receiving a message in the information receiver.

Thus, the use of the proposed device can increase the likelihood of correct reception of the message.

As pseudo-random sequences in the system, for example, M-sequences can be used [2]. To generate a certain of them, the scheme of Fig.3.17 can be used. You can get another sequence by connecting other taps of the shift register to the adder.

Information sources

1. RF patent No. 2168867, H 04 L 25/00.

2. Varakin L.E. Communication systems with noise-like signals. - M .: Radio and communications, 1985, p. 49-56.

Claims (1)

A start-stop communication system containing on the transmitting side a series-connected information source, a shift register, a multiplexer, a relative phase manipulator (OFM) and a transmitter, in addition, a first clock pulse generator (GTI), a pseudo-random sequence generator (GPS), a multiplier and binary counter, serially connected carrier frequency generator (LFO) and a key whose output is connected to the signal input of the OFM, the input of the first GTI is connected to the clock output of the inform source In this case, the second output of the first GTI is connected to the clock input of the shift register, and its third output is connected to the second inputs of the GPS and the multiplier, the output of which is also connected to the control inputs of the OFM and the key, and the first output of the first GTI is connected to the installation input of the binary counter, the outputs of which connected by a bus to the control inputs of the multiplexer, on the receiving side - series-connected receiver, matched filter and sync block, series-connected demodulator and memory block, the output of which is I am the output of the device and the second GTI, the first output of the second GTI connected to the second input of the storage unit, its second output connected to the corresponding inputs of the demodulator and storage unit, the output of the matched filter through the delay line connected to the third input of the demodulator, while the transmitting and receiving sides connected by a communication line, characterized in that on the transmitting side introduced the first adder modulo two and the first and second circuits "And", the first inputs of which are combined and connected to the first output ne first GTI, and the second are connected respectively to the direct and inverse outputs of the first adder modulo two, and the outputs of the first and second “I” circuits are connected respectively to the first and third inputs of the GPS, and the inputs of the first adder modulo two are connected by a bus to the output register shift bus , on the receiving side, an OR circuit and a pulse shaper, a second sync block, a second adder modulo two, a third I circuit and an RS flip-flop are introduced, and the first input of the second adder modulo two is connected by bus to the counter with the external outputs of the storage unit, and the second with the output of the RS trigger, the first and second inputs of the third “I” circuit are connected respectively to the outputs of the second adder modulo two and a pulse shaper, the outputs of the first and second sync blocks are connected respectively to the first and second inputs of the second GTI , OR circuits and RS-flip-flops, the input of the second sync block is connected to the output of the matched filter, and the output of the OR circuit is also connected to the first input of the demodulator, the output of the third AND circuit is an additional output of the device.

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