CN102404071B - Encoding modulation method and device of synchronous training symbol blocks - Google Patents
Encoding modulation method and device of synchronous training symbol blocks Download PDFInfo
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
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- H—ELECTRICITY
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Abstract
The invention relates to encoding modulation method and device of synchronous training symbol blocks. The method comprises a sequence generating step for generating a seemingly optimal self-correlation binary sequence of which the period is p, a code block generating step for differentially encoding the seemingly optimal self-correlation binary sequence at an interval of M bits, wherein first M differentially encoded bits are preset bits, and a linear modulating step for linearly modulating a sequence obtained by differential encoding to two points a, b on a complex number plane as a synchronous code sequence, and a=-b. The encoding modulation method and device of synchronous training symbol blocks disclosed by the invention aim to simplify an encoding modulation method and can simplify an encoding modulation progress.
Description
Technical field
The present invention relates to the communication technology, especially a kind of synchronous training symbol piece code modulating method and device.
Background technology
In current wireless and wired communication system, single carrier symbol linear is modulated due to its maturity, simplicity and the high-rate characteristics under some channel, still adopted by different communication standard protocols still in occupation of the important communication system market share, and in different communication and telecommunication field.For example, at ground cable digital TV, satellite digital TV, microwave relay link, (defending) star ground (face) TDMA (time division multiple access) packet communications etc. are many continuously or in Packet data service, all adopt this single carrier, linear modulation (containing QPSK, QAM, or with QPSK, the QAM of differential coding) emission system.The main feature that this system transmits is to make a start to send with single symbol order, and as shown in Figure 1, each symbol is modulated onto on a fixing single carrier, and this carrier signal is sent out.
In current sorts of systems, depending on the difference of business demand, sorts of systems has been used different synchronous method.In many synchronous method, the method that uses training sequence because of its flexibly, reliable, can complete synchronous (or coarse synchronization) under compared with low signal-to-noise ratio and noisy channels condition and be widely used, such as among the gsm system of TDMA, just use synchronous training sequence to complete synchronously.The feature difference of different synchronous training sequences, the multiple synchronization parameter being coupled by the impact of channel and noise can be separated cleverly through well-designed synchronous training sequence, thereby make each synchronization parameter (timing error, frame position is judged, frequency deviation is estimated with skew estimation etc.) can substantially separate, be convenient to each synchronization parameter and independently detect and correct.
Known from the above mentioned, the form of synchronous training sequence and Design of Signal are the key issues relying in the synchro system of training sequence, a synchronous training symbol sequence through good design, can help receiving terminal to complete more easily synchronous overall tasks, or the Fast Coarse that can complete most parameters is caught, be convenient to follow-up synchronization loop Fast Convergent.
Current without (having) line communication system in, the training sequence that generally adopts some to know, such as leading (Preamble) sequence in OFDM (OFDM) system, in synchronizing channel in WCDMA synchronous-frequency expansion sequence, but obtain the method more complicated of these synchronous training sequences, and there are some common shortcomings, such as, after having specified synchronizing symbol, the maximum timing and frequency offset that system can be corrected is just determined, the in the situation that of king-sized frequency departure, the timing of synchronizing sequence and frequency deviation correction function are by cisco unity malfunction.
Such as, in some satellite tdma system, use double-periodic synchronizing symbol, each cycle length is N, now if frequency departure is larger (such as reached character rate 20%～30%), use so traditional correlation technique, relevant peaks may there will not be, be difficult to carry out accurate sign synchronization and frame synchronization, even and there is relevant peaks, utilize the characteristic of bi-period structure, also can only estimate the frequency deviation of 1/2N, exceed this frequency departure, Frequency Estimation will go wrong.Can normally work for system, be necessary maximum frequency deviation to carry out rigid restriction, this has just proposed very high requirement to the device such as crystal oscillator and digital oscillator of sending and receiving end.
In addition, if the maximum frequency deviation that system may occur changes (such as becoming large), or the maximum permissible frequency deviation that communication standard specifies changes (such as becoming large), and the synchronizing symbol having designed is difficult to adjust to adapt to this variation again.
For this reason, need a kind of coding of design simple synchronization training symbol.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of synchronous training symbol piece code modulating method and device, to simplify coded modulation process.
For solving above technical problem, the present invention also provides a kind of synchronous training symbol piece code modulating method, and the method comprises:
Sequence generates step, the seemingly best auto-correlation binary sequence that generating period is p;
Code block generates step, and by this differential coding that is spaced apart M bit like best auto-correlation binary sequence, wherein front M differential coding bit is preset bit;
Linear modulation step, two the some as of the sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
Further, described sequence generation step specifically comprises: according to formula
to c=0,1,2,3... (p+2L-2), (p+2L-1) carries out Montgomery Algorithm successively, obtains successively this p+2L bit like best auto-correlation binary sequence, and wherein, p and L are for setting in advance.
Further, described code block generation step specifically comprises: a preset M bit in M level shift register;
By the one-level that moves to left of bit in M level shift register, the bit moving to left out enters synchronous code block register, and carries out XOR with the described next bit like best auto-correlation binary sequence successively, XOR result is sent into the right-hand member of M level shift register; Circulation is carried out this step p+2L time, until c=p+2L-1 finally obtains M+p+2L synchronous code block bit.
Further, M makes a start to set in advance according to the maximum frequency deviation value of pre-detection, and the frequency deviation value of pre-detection is larger, and M value is less.
Further, p sets in advance according to signal to noise ratio environment and channel condition, and L arranges according to receiving end detection window half strip length.
Further, the method for linear modulation is Quadrature Phase Shift Keying (QPSK), quadrature amplitude modulation (QAM), the QPSK with differential coding or the QAM with differential coding.
For solving above technical problem, the present invention also provides a kind of synchronous training symbol piece coded modulation device, and this device comprises:
Sequence generating unit, for according to ordered series of numbers a
nn generating period is the seemingly best auto-correlation binary sequence of p;
Code block generation unit, is connected with described sequence generating unit, for a preset M bit is spaced apart to the differential coding of M with this together with best auto-correlation binary sequence, and described M preset bit and differential coding result is formed to synchronous code block;
Linear modulation unit, is connected with described sequence generating unit, two the some as of the sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
Further, described sequence generating unit specifically comprises: counter and the Montgomery Algorithm device being connected with this counter, described counter for since 0 progressively cumulative 1 until p+2L-1, and export count value c to Montgomery Algorithm device;
Described Montgomery Algorithm device, for according to formula
each c value to counter output is carried out Montgomery Algorithm, obtains successively described p+2L the bit like best auto-correlation binary sequence.
Further, described differential coding unit comprises:
Shift register, its number of bits is M, for a preset M bit, and successively the bit of high order end is exported to synchronous code block register and XOR device;
XOR device, for the bit of described shift register high order end is carried out to XOR with sequence generating unit generates like the next bit of best auto-correlation binary sequence successively, and will obtain XOR result and input the low order end of described shift register;
Synchronous code block register, for depositing the bit of described shift register input, finally obtains p+2L+M bit.
Further, M makes a start to set in advance according to the maximum frequency deviation value of pre-detection, and the frequency deviation value of pre-detection is larger, and M value is less.
Further, p sets in advance according to signal to noise ratio environment and channel condition, and L is according to being the half strip length setting of receiving end detection window.
The code modulating method of the synchronous training symbol piece of the present invention code modulating method, device is easy to realize, can effectively simplify coded modulation process, can be in Frame independent insertion can flexible configuration synchronizing symbol piece, also applicable to low signal-to-noise ratio, there is the system environments that has super large frequency deviation compared with noisy channels, sending and receiving end carrier wave.
Brief description of the drawings
Fig. 1 is single carrier continuous symbol linear modulation schematic diagram;
Fig. 2 is the schematic diagram of the synchronous training symbol piece of the present invention code modulating method;
Fig. 3 is synchronizing symbol piece schematic diagram of the present invention;
Fig. 4 is the placement location schematic diagram of M preset bit in M level shift register;
Fig. 5 is a kind of reference circuit schematic diagram of preset M bit;
Fig. 6 is the two QPSK schematic diagrames sending out agreement of transmitting-receiving;
Fig. 7 is the embodiment schematic diagram of synchronous training symbol piece code modulating method;
Fig. 8 is the embodiment schematic diagram of synchronous training symbol piece coded modulation device.
Embodiment
As shown in Figure 2, the synchronous training symbol piece of the present invention code modulating method comprises the steps:
Step 201: the seemingly best auto-correlation binary sequence that generating period is p;
The seemingly optimal period auto-correlation binary sequence (also referred to as almost desirable auto-correlation binary sequence) that prime field (GF (p)) the upper cycle is p, these sequences are difference set or the almost difference set sequences on GF (p), its method has a variety of, preferably, can adopt the method for Montgomery Algorithm to realize.
Item number N and the period p of ordered series of numbers can arrange flexibly.Wherein, period p can be according to different signal to noise ratio environment and channel condition setting.Item number N arranges according to p and receiving end detection window half strip length L, N=p+2L.
Preferably, step 201 comprises the following steps:
201a) make a start a counter c is set, this counter is progressively added up to 1 since 0, be added to p+2L-1 always;
201b), for the value (since 0 until p+2L-1) of each counter, transmitting terminal will the value of being calculated as follows
obtain a bit;
The seemingly best auto-correlation binary sequence that it is p that all Montgomery Algorithm results are arranged in order the composition cycle, also, the binary sequence that this cycle is p is (almost) difference set sequence on finite field gf (p).
Step 202: by this differential coding that is spaced apart M bit like best auto-correlation binary sequence, wherein front M differential coding bit is preset bit;
Differential coding can be realized by XOR.Particularly, this step comprises:
A 202a) preset M bit in M level shift register;
Make a start with one arbitrarily Pseudo-random bit generator PSBG produce M preset bit, or produce M preset bit with the M a predetermining bit, (bit) shift register that this M bit is admitted to a long M level as shown in Figure 4;
Preferably, adopt the XOR result of another shift register as the preset bit of M level shift register, thereby constantly automatically produce new preset bit, illustrate: as shown in Figure 5, preset 11 bits in 11 grades of shift registers, as initial condition is set to (1 011001100 0) from left to right, the bit of low order end bit and the individual deposit unit of n (as the 9th) is carried out to XOR, when a new bit of shift register XOR generation each time, just sent into the right-hand member of M bit shift register and the high order end of shift register by the left side that causes from the right side of order, the simultaneously shift register one-level that moves right.
202b) bit in M level shift register is moved to left one-level, the bit moving to left out enters synchronous code block register, and carry out XOR with the next bit (being also current Montgomery Algorithm result) of binary sequence, and then XOR result is sent into the right-hand member of M level shift register successively;
This step can be described as: the leftmost bit of Montgomery Algorithm result and shift register is carried out to XOR; The shift register bit one-level that moves to left, the bit moving to left out enters synchronous code block register, and XOR result is sent into shift register right-hand member.
Understandably, the description of this step lay particular emphasis on XOR and move to left after the result that changes of the bit position that causes, and the sequencing of not operation.
It should be noted that Montgomery Algorithm, move to left, the frequency of the operation such as XOR is consistent.
202c) circulation execution step 202b) p+2L, until c=p+2L-1 finally obtains M+p+2L synchronous code block bit.
Visible, in counters throughout 0,1,2 ..., after this p+2L of p+2L-1 value, Montgomery Algorithm has also carried out p+2L operation, obtained p+2L XOR result, and the preset bit of M and p+2L XOR result in M level shift register is all admitted to synchronous code block register, finally obtains M+p+2L synchronous code block bit.
Step 203: two the some as of the sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
A=-b, also these 2 in complex number plane about origin symmetry.
The method of linear modulation can be QPSK (Quadrature Phase Shift Keying, Quadrature Phase Shift Keying), QAM (Quadrature Amplitude Modulation, quadrature amplitude modulation), or QPSK with differential coding, QAM.
Taking QPSK as example, this is made a start this M+p+2L bit through a modulation mapping, be mapped to one arbitrarily on any one diagonal of QPSK (4 phase phase-shift keying) planisphere, that is, if suppose that the modulation constellation of this QPSK is in complex number plane
, e
(π+φ) i,
four points, the φ is here planisphere initial phase ([0 arbitrarily, 2 π] arbitrarily, jointly arranged by receiving-transmitting sides), so for any synchronous code block bit x (x value is 0 or 1), use two following formula any one (two the sending out of transmitting-receiving appointed), modulate:
or
After ovennodulation, the synchronizing symbol piece finally obtaining as shown in Figure 3, is made up of M+2L+p modulation symbol, when transmission, according to order from left to right, M+2L+p symbol is all sent.
These synchronizing symbols form an autonomous block, can be inserted into very easily Frame Anywhere.
Coded modulation process is as shown in Figure 6 particularly:
In the drawings, c is a counter, since 0, until p+2L-1 carries out one to each value of counter and asks Montgomery Algorithm; The leftmost bit of the shift register that 0 or 1 bit generating and length are M is carried out XOR, carrying out subsequently XOR bit afterwards sends into from M level shift register low order end, and the now M level shift register bit that moves to left, leftmost bit enters synchronous code block register, and synchronous code block register total length is M+p+2L.Before coding starts, M level shift register quilt is random or pseudo-random bits is preset.Final effect is that front M bit of synchronous code block register is exactly aforementioned M bit shift register initial condition position, and the XOR output valve x of the M+1 bit of synchronous code block while being c=0, XOR output valve x when the M+2 bit of synchronous code block is c=1, by that analogy ....Synchronous code block, after sending into linear modulator, is modulated onto in complex number plane on 2 about origin symmetry.
The present invention program can be applicable to different system environmentss by the flexible setting of M, L and p, as arranged flexibly according to signal to noise ratio environment and channel condition, receiving end detection window length and frequency deviation region etc.
Particularly, receiving-transmitting sides, according to prior agreement (or the negotiation in when start, or negotiation in communication process), is appointed same configurable parameter p jointly, L, and M, is retained in system separately separately; In this embodiment, p, L, these three parameters of M are all configurable, also formed the core of the present invention's " configurable " concept.
Below each configurable parameter is described:
1) parameter M
May there is larger frequency deviation with making a start because of device difference, Doppler effect etc. in receiving end, for different maximum frequency deviations, just need to there is different capturing frequency deviation scopes, also need in addition frequency offset estimation accuracy enough high, the present invention can make the present invention program go for different frequency deviations by configuration M, and enough anti-deviation capabilities are provided.
The present invention can be configured to the value of parameter M allow to occur with transmitting-receiving two-end is maximum, or the carrier frequency shift Δ f that occurs of maximum possible
maxrelevant, usually, if the speed of supposition baseband signalling is B
ssymbol/second, carrier frequency shift Δ f
maxunit is Hz, and normalization carrier wave frequency deviation is so
the maximum in theory frequency deviation that can detect of synchronous code block meets following formula:
Also be, the 1/2M that detectable maximum frequency deviation is maximum character rate in theory, if M obtains less here, the scope that frequency deviation detects is so larger, in the time of minimum M=1, current synchronous code block can detect the super large frequency deviation that is not more than 1/2 base band speed in theory, for example, under the base band speed of 49.2M, we can detect the frequency shift (FS) that is not more than 24.6MHz in theory.But in all M that meet detection range, if M is too little, the estimated accuracy of frequency deviation will decline so.Preferably adopt following formula to determine M:
Wherein, Δ f
maxfor the maximum frequency deviation value of system pre-detection, in other words, the maximum permissible frequency deviation value that system specifies the maximum frequency deviation value there will be or system, B
sfor baseband signalling speed, unit is symbol/second,
represent to round downwards.
2) parameter L
The receiving end of synchronous code block need to utilize a detection window to detect, in order to ensure enough large successful detection probability, reduce false dismissal probability and false alarm probability simultaneously as far as possible, detection window should be grown a bit as far as possible, but long detection window will cause the complexity of hardware and software to increase considerably, the present invention can adapt from the receiving end of setting different size detection windows by the value of parameters L neatly.
L is receiving end detection window half strip length, its size can flexible configuration, and under one times of baseband signalling speed, the length of receiving end detection window is 2L+1, and under dual-rate, the length of receiving end detection window is 4L+1, correspondingly, under n times of speed, the length of receiving end detection window is 2nL+1.L value larger, can suppress the secondary lobe that receiving end detects, and under microwave channel, preferably, gets L=10 to 15, and meanwhile, in order to carry out Multipath searching under some special multipath channel, the value of L can be larger, and maximum can reach p-1.
3) parameter p
The present invention can change the length of synchronous code block by parameters p, thereby changes the size of final accumulation baseband signal effective energy, resists different signal to noise ratio environment and channel condition.
Parameter p is the binary sequence cycle, can carry out flexible configuration, and in order to improve correlation, preferably, p value is odd prime, and for example, from p=31, following all values are all fine:
31 37 41 43 47 53 59 61
67 71 73 79 83 89 97 101
103 107 109 113 127 131 137 139
149 151 157 163 167 173 179 181
191 193 197 199 211 223 227 229
233 239 241 251 257 263 269 271
277 281 283 293 307 311 313 317
331 337 347 349 353 359 367 373
379 383 389 397 401 409 419 421
431 433 439 443 449 457 461 463
467 479 487 491 499 503 509 521
523 541 547 557 563 569 571 577
587 593 599 601 607 613 617 619
631 641 643 647 653 659 661 673
677 683 691 701 709 719 727 733
739 743 751 757 761 769 773 787
797 809 811 821 823 827 829 839
853 857 859 863 877 881 883 887
907 911 919 929 937 941 947 953
967 971 977 983 991 997 1009 1013
1019 1021 1031 1033 1039 1049 1051 1061
1063 1069 1087 1091 1093 1097 1103 1109
1117 1123 1129 1151 1153 1163 1171 1181
1187 1193 1201 1213 1217 1223 1229 1231
1237 1249 1259 1277 1279 1283 1289 1291
1297 1301 1303 1307 1319 1321 1327 1361
1367 1373 1381 1399 1409 1423 1427 1429
1433 1439 1447 1451 1453 1459 1471 1481
1483 1487 1489 1493 1499 1511 1523 1531
1543 1549 1553 1559 1567 1571 1579 1583
1597 1601 1607 1609 1613 1619 1621 1627
1637 1657 1663 1667 1669 1693 1697 1699
1709 1721 1723 1733 1741 1747 1753 1759
1777 1783 1787 1789 1801 1811 1823 1831
1847 1861 1867 1871 1873 1877 1879 1889
1901 1907 1913 1931 1933 1949 1951 1973
1979 1987 1993 1997 1999 2003 2011 2017
2027 2029 2039
Application example
The planisphere of supposing receiving-transmitting sides agreement normalization QPSK is 4 following complex points, as shown in Figure 7,
Baseband signalling speed is 49.2M symbol/second, signal to noise ratio 20dB, and maximum frequency deviation 2MHz, according to formula
Get and determine M=8, signal to noise ratio environment, the channel condition that may face according to system are got and are determined p=257, L=15, and the synchronous code modulated process of training symbol piece comprises:
A) preset 8 bits are 01100110;
B) make c=0,1,2,3 ..., 286, calculate respectively (c
128mod 257) mod2, obtain thus 287 bits as described below:
0，1，1，0，1，0，0，0，1，1，0，1，0，1，0，1，1，1，1，0，0，1，1，1，0，1，1，0，0，1，1，1，1，0，1，1，1，0，0，0，0，0，1，0，1，0，1，0，0，1，1，0，1，0，0，0，0，1，1，1，1，1，1，0，1，0，0，1，1，0，1，0，1，1，0，0，0，0，0，1，0，1，0，0，1，0，0，0，1，1，0，0，1，0，0，1，0，0，1，1，1，0，0，0，1，0，0，0，0，0，0，1，0，1，1，0，1，1，1，0，1，1，1，1，1，0，0，0，1，1，0，0，0，1，1，1，1，1，0，1，1，1，0，1，1，0，1，0，0，0，0，0，0，1，0，0，0，1，1，1，0，0，1，0，0，1，0，0，1，1，0，0，0，1，0，0，1，0，1，0，0，0，0，0，1，1，0，1，0，1，1，0，0，1，0，1，1，1，1，1，1，0，0，0，0，1，0，1，1，0，0，1，0，1，0，1，0，0，0，0，0，1，1，1，0，1，1，1，1，0，0，1，1，0，1，1，1，0，0，1，1，1，1，0，1，0，1，0，1，1，0，0，0，1，0，1，1，0，1，1，0，1，0，0，0，1，1，0，1，0，1，0，1，1，1，1，0，0，1，1，1，0，1，1，0，0，1
C) above-mentioned 287 bits are sent into XOR device according to order from left to right, as shown in Figure 5, the bit after the new XOR obtaining is:
0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 11 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 0 11 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 11 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 01 1 1 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 0 0 0 0 1 1 1 0 00 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 00 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 0 0
D) existing 8 preset bits before above-mentioned 287 bits, obtain new synchronization bit piece:
0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 11 1 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 01 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 0 1 0 00 1 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 00 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 00 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 1 0 01 1 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 0 0
E) utilize formula
(1+j) (1-2x) (wherein j is plural imaginary part) to cornerwise 2 of QPSK planisphere " lower-left-upper right ", obtains the synchronizing symbol piece that a length is 295 symbols by these 295 bit modulation.
So far, we have completed the coded modulation process of a synchronizing symbol piece obtaining according to signal to noise ratio condition and Frequency Offset, and follow-up, this encoding block can be inserted into any one place of Frame at any time, for carrying out synchronously in receiving end.
Accordingly, the present invention also provides a kind of synchronous training symbol piece coded modulation device, and as shown in Figure 8, this device comprises:
The seemingly best auto-correlation binary sequence that sequence generating unit is p for generating period;
Code block generation unit, is connected with described sequence generating unit, for this is spaced apart to the differential coding of M bit like best auto-correlation binary sequence, wherein before M differential coding bit be preset bit;
Linear modulation unit, is connected with described sequence generating unit, two some a for sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
Preferably, described sequence generating unit specifically comprises: counter and the Montgomery Algorithm device being connected with this counter, described counter for since 0 progressively cumulative 1 until p+2L-1, and export count value c to Montgomery Algorithm device;
Described Montgomery Algorithm device, for according to formula
each c value to counter output is carried out Montgomery Algorithm, obtains successively described p+2L the bit like best auto-correlation binary sequence.
Preferably, described differential coding unit comprises:
Shift register, its number of bits is M, for a preset M bit, and successively the bit of high order end is exported to synchronous code block register and XOR device;
XOR device, for the bit of described shift register high order end is carried out to XOR with sequence generating unit generates like the next bit of best auto-correlation binary sequence successively, and will obtain XOR result and input the low order end of described shift register;
Synchronous code block register, for depositing the bit of described shift register input, finally obtains p+2L+M bit.
M makes a start to set in advance according to the maximum frequency deviation value of pre-detection, and the frequency deviation value of pre-detection is larger, and M value is less, and preferably, the maximum frequency deviation value of pre-detection is Δ f
maxtime, M meets the following conditions
wherein B
sfor baseband signalling speed, unit is symbol/second,
represent to round downwards.
As mentioned above, p sets in advance according to signal to noise ratio environment and channel condition, and L is according to being the half strip length setting of receiving end detection window.
Than prior art, the beneficial effect of technical solution of the present invention is mainly reflected in following several aspect:
Code modulating method of the present invention is realized simple, has effectively simplified code modulated process;
This scheme is insensitive for the initial phase deviation of reception carrier, is also sane for phase noise, and for frame synchronization, symbol slightly synchronous and frequency deviation estimates not produce too much influence.
This technical scheme can be according to signal to noise ratio, synchronous error requires, system allows maximum frequency deviation (or the maximum frequency deviation that may occur), carry out extremely flexible and changeable configuration, with the demand of adaptive system, comprise: according to the difference of maximum frequency deviation value, set different parameter M, make to meet frequency offset estimation range, can farthest improve again estimated accuracy; According to different signal to noise ratio situations (or the minimum permission signal to noise ratio of system), the size of flexible configuration p, to meet different signal to noise ratio demands; According to the hardware resource of receiving end and the requirement to detection probability, flexible configuration iSCSI receiving end window parameter L;
The coding of the synchronizing symbol piece of the present invention's design establishes one's own system, and with data independence, can be used as a completely independently module, the random optional position that is inserted into Frame, or be inserted in the middle of continuous multiple Frame,
This technical scheme can make receiving end in a synchronizing symbol piece, the disposable Symbol Timing that completes, frame position is synchronous, super large frequency deviation is estimated three tasks, and the frequency deviation that can estimate can be quite large (theoretical maximum can reach character rate 1/2), and this is difficult to accomplish in many systems the insides (such as aforesaid satellite TDMA packet communication);
The synchronous code block of the present invention has good correlation, has good identifiability, and receiving end can utilize the characteristic of synchronizing signal to identify easily the arrival of synchronous code block;
The concrete system coding that the present invention provides has only used simple Montgomery Algorithm, bit XOR and simple modulation.And be particularly suitable for utilizing software radio or configurable can programming circuit along with the state of link carries out auto-adaptive parameter adjustment to adapt to different channel conditions, can also the precalculated memory that leaves system in.
In sum, the inventive method and device can be in Frame independent insertion can flexible configuration synchronizing symbol piece, so that at low signal-to-noise ratio, have the in the situation that of there is super large frequency deviation compared with noisy channels, sending and receiving end carrier wave, can make receiving end complete that preassigned timing synchronization, frame position are synchronous, three mission criticals of carrier frequency synchronization.
One of ordinary skill in the art will appreciate that all or part of step in said method can carry out instruction related hardware by program and complete, described program can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits.Correspondingly, the each module/unit in above-described embodiment can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Claims (7)
1. a synchronous training symbol piece code modulating method, is characterized in that, the method comprises:
Sequence generates step: the seemingly best auto-correlation binary sequence that generating period is p;
Code block generates step: this is spaced apart to the differential coding of M bit like best auto-correlation binary sequence: a preset M bit in M level shift register; By the one-level that moves to left of bit in M level shift register, the bit moving to left out enters synchronous code block register, and carries out XOR with the described next bit like best auto-correlation binary sequence successively, XOR result is sent into the right-hand member of M level shift register; Circulation is carried out this step p+2L time, until c=p+2L-1, finally obtain M+p+2L synchronous code block bit, M makes a start to set in advance according to the maximum frequency deviation value of pre-detection, the frequency deviation value of pre-detection is larger, M value is less, and p sets in advance according to signal to noise ratio environment and channel condition, and L arranges according to receiving end detection window half strip length;
Linear modulation step, two the some as of the sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
2. the method for claim 1, is characterized in that: described sequence generates step and specifically wraps
for setting in advance.
3. the method for claim 1, is characterized in that: the maximum frequency deviation value of pre-detection is Δ f
maxtime, M meets the following conditions
wherein B
sfor baseband signalling speed, unit is symbol/second,
represent to round downwards.
4. the method for claim 1, is characterized in that: the method for linear modulation is Quadrature Phase Shift Keying (QPSK), quadrature amplitude modulation (QAM), the QPSK with differential coding or the QAM with differential coding.
5. a synchronous training symbol piece coded modulation device, is characterized in that, this device comprises:
Sequence generating unit: for according to ordered series of numbers a
n=n generating period is the seemingly best auto-correlation binary sequence of p:
Code block generation unit: be connected with described sequence generating unit, for a preset M bit is spaced apart to the differential coding of M with this together with best auto-correlation binary sequence, and described M preset bit and differential coding result formed to synchronous code block; M makes a start to set in advance according to the maximum frequency deviation value of pre-detection, and the frequency deviation value of pre-detection is larger, and M value is less;
Described code block generation unit comprises:
Shift register, its number of bits is M, for a preset M bit, and successively the bit of high order end is exported to synchronous code block register and XOR device;
XOR device, for the bit of described shift register high order end is carried out to XOR with sequence generating unit generates like the next bit of best auto-correlation binary sequence successively, and will obtain XOR result and input the low order end of described shift register;
Synchronous code block register, for depositing the bit of described shift register input, finally obtains p+2L+M bit; P sets in advance according to signal to noise ratio environment and channel condition, and L is according to being the half strip length setting of receiving end detection window;
Linear modulation unit, is connected with described sequence generating unit, two the some as of the sequence that differential coding is obtained on as synchronization code sequence linear modulation to complex number plane, b, and a=-b.
6. device as claimed in claim 5, it is characterized in that: described sequence generating unit specifically comprises: counter and the Montgomery Algorithm device being connected with this counter, described counter for since 0 progressively cumulative 1 until p+2L-1, and export count value c to Montgomery Algorithm device;
set in advance.
7. device as claimed in claim 5, is characterized in that: the maximum frequency deviation value of pre-detection is Δ f
maxtime, M meets the following conditions
wherein B
sfor baseband signalling speed, unit is symbol/second,
represent to round downwards.
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| CN201010282487.9A CN102404071B (en) | 2010-09-14 | 2010-09-14 | Encoding modulation method and device of synchronous training symbol blocks |
| PCT/CN2010/079162 WO2012034319A1 (en) | 2010-09-14 | 2010-11-26 | Method and apparatus for encoding modulation of synchronization training symbol blocks |
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| CN102959918B (en) * | 2012-08-31 | 2015-02-25 | 华为技术有限公司 | A training sequence generating method, a training sequence generating device, and an optical communication system |
| KR102365330B1 (en) * | 2017-05-04 | 2022-02-21 | 광동 오포 모바일 텔레커뮤니케이션즈 코포레이션 리미티드 | Timing method of sync signal block and related products |
| CN114584258B (en) * | 2022-02-15 | 2023-05-26 | 烽火通信科技股份有限公司 | Service delay reduction method, device, equipment and readable storage medium |
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| CN1404307A (en) * | 2001-08-24 | 2003-03-19 | 国家广播电影电视总局广播科学研究院 | Data frame forming method and corresponding interleaving and encoding modulation method |
| CN1870465A (en) * | 2005-05-24 | 2006-11-29 | 都科摩（北京）通信技术研究中心有限公司 | Generating method, communication system and communication method of circulation training sequence |
| CN101184078A (en) * | 2007-12-24 | 2008-05-21 | 清华大学 | Method for filling protection spacing in orthogonal frequency division multiplexing modulation system and communication system thereof |
| EP2043318A2 (en) * | 2007-09-27 | 2009-04-01 | Intel Corporation | Preamble techniques for communications networks |
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| US6519275B2 (en) * | 2001-06-29 | 2003-02-11 | Motorola, Inc. | Communications system employing differential orthogonal modulation |
| US9065714B2 (en) * | 2007-01-10 | 2015-06-23 | Qualcomm Incorporated | Transmission of information using cyclically shifted sequences |
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| CN1404307A (en) * | 2001-08-24 | 2003-03-19 | 国家广播电影电视总局广播科学研究院 | Data frame forming method and corresponding interleaving and encoding modulation method |
| CN1870465A (en) * | 2005-05-24 | 2006-11-29 | 都科摩（北京）通信技术研究中心有限公司 | Generating method, communication system and communication method of circulation training sequence |
| EP2043318A2 (en) * | 2007-09-27 | 2009-04-01 | Intel Corporation | Preamble techniques for communications networks |
| CN101184078A (en) * | 2007-12-24 | 2008-05-21 | 清华大学 | Method for filling protection spacing in orthogonal frequency division multiplexing modulation system and communication system thereof |
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