CN102404071A - Encoding modulation method and device of synchronous training symbol blocks - Google Patents
Encoding modulation method and device of synchronous training symbol blocks Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention relates to encoding modulation method and device of synchronous training symbol blocks. The method comprises a sequence generating step for generating a seemingly optimal self-correlation binary sequence of which the period is p, a code block generating step for differentially encoding the seemingly optimal self-correlation binary sequence at an interval of M bits, wherein first M differentially encoded bits are preset bits, and a linear modulating step for linearly modulating a sequence obtained by differential encoding to two points a, b on a complex number plane as a synchronous code sequence, and a=-b. The encoding modulation method and device of synchronous training symbol blocks disclosed by the invention aim to simplify an encoding modulation method and can simplify an encoding modulation progress.
Description
Technical field
The present invention relates to the communication technology, especially a kind of synchronous training symbol block encoding modulator approach and device.
Background technology
In current wireless and wired communication system; The modulation of single carrier symbol linear is because its maturity, simplicity and the high-rate characteristics under some channel; Still adopted by the different communication standard agreement still in occupation of the important communication system market share, and in different communication and telecommunication field.For example cable digital TV, satellite digital TV on ground; The microwave relay link; In many continuous perhaps Packet data services such as (defending) star ground (face) TDMA (time division multiple access) packet communication, all adopted this single carrier, linear modulation (to contain QPSK, QAM; Perhaps with the QPSK of differential coding, emission system QAM).The main feature that this system transmits is to make a start to send with single symbol sequence, and as shown in Figure 1, each symbol all is modulated onto on the fixing single carrier, and this carrier signal is sent out.
In current sorts of systems, look the difference of business demand, sorts of systems has been used the different synchronization method.In many method for synchronous; The method of using training sequence because of its flexibly, reliable, can be widely used accomplishing synchronous (perhaps coarse synchronization) down than low signal-to-noise ratio and abominable channel condition; Such as among the gsm system of TDMA, just used synchronous training sequence to accomplish synchronously.The characteristics of different synchronization training sequence are different; Can separate the multiple synchronization parameter that is coupled by channel and The noise cleverly through well-designed synchronous training sequence; Thereby make each synchronization parameter (timing error; Frame position judges, frequency offset estimating and skew estimation etc.) can separate basically, be convenient to each synchronization parameter and independently detect and correct.
Can know from the above mentioned; The form of synchronous training sequence and Design of Signal are the key issues that relies in the synchro system of training sequence; Synchronous training symbol sequence through good design; Can help receiving terminal to accomplish synchronous overall tasks more easily, perhaps can accomplish slightly catching fast of most parameters, be convenient to follow-up synchronization loop and restrain fast.
In current nothing (having) line communication system, the training sequence that generally adopts some to know is such as leading (Preamble) sequence in OFDM (OFDM) system; Synchronous-frequency expansion sequence in the synchronizing channel among the WCDMA; But obtain the method more complicated of these synchronous training sequences, and some common shortcomings are all arranged, such as; After having stipulated synchronizing symbol; Maximum timing and frequency departure that system can correct just are determined, and under the situation of king-sized frequency departure, the timing of synchronizing sequence and frequency deviation correction function are with cisco unity malfunction.
Such as, in some satellite tdma system, use double-periodic synchronizing symbol, phase length is N weekly; If this moment frequency departure bigger (such as reached character rate 20%～30%), use traditional correlation technique so, relevant peaks maybe not can occur; Be difficult to carry out accurate sign synchronization and frame synchronization, even and relevant peaks has appearred, utilize the characteristic of bi-period structure; Also can only estimate the frequency deviation of 1/2N, surpass this frequency departure, Frequency Estimation will go wrong.Can operate as normal for system, be necessary maximum frequency deviation is carried out rigid restriction, this has just proposed very high requirement to devices such as the crystal oscillator of sending and receiving end and digital oscillators.
In addition, if the maximum frequency deviation that system possibly occur changes (such as becoming big), perhaps the maximum permissible frequency deviation of communication standard regulation changes (such as becoming big), and the synchronizing symbol that has designed is difficult to adjust to adapt to this variation again.
For this reason, need a kind of coding simple synchronization training symbol of design.
Summary of the invention
The technical problem that the present invention will solve is a kind of synchronous training symbol block encoding modulator approach and device to be provided, to simplify the coded modulation process.
For solving above technical problem, the present invention also provides a kind of synchronous training symbol block encoding modulator approach, and this method comprises:
Sequence generates step, and the generation cycle is the seemingly best auto-correlation binary sequence of p;
Code block generates step, and this is spaced apart the differential coding of M bit like best auto-correlation binary sequence, wherein before M differential coding bit for presetting bit;
The linear modulation step, the sequence that differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
Further; Said sequence generates step and specifically comprises: according to formula
successively to c=0; 1,2,3... (p+2L-2); (p+2L-1) carry out Montgomery Algorithm; Obtain this p+2L bit like best auto-correlation binary sequence successively, wherein, p and L are for be provided with in advance.
Further, said code block generation step specifically comprises: in M level shift register, preset M bit;
With bit left one-level in the M level shift register, the bit that moves to left out gets into the synchronous code block register, and carries out XOR with said next bit like best auto-correlation binary sequence successively, the XOR result is sent into the right-hand member of M level shift register; Circulation is carried out this step p+2L time, until c=p+2L-1, finally obtains M+p+2L code block bit synchronously.
Further, M is that the maximum frequency deviation value of making a start according to pre-detection is provided with in advance, and the frequency deviation value of pre-detection is big more, and the M value is more little.
Further, p is provided with according to signal to noise ratio environment and channel condition in advance, and L is provided with according to receiving end detection window half strip length.
Further, the method for linear modulation is the QPSK of QPSK (QPSK), quadrature amplitude modulation (QAM), band differential coding or the QAM of band differential coding.
For solving above technical problem, the present invention also provides a kind of synchronous training symbol block encoding modulating device, and this device comprises:
Sequence generating unit is used for according to ordered series of numbers a
nThe n generation cycle is the seemingly best auto-correlation binary sequence of p;
The code block generation unit is connected with said sequence generating unit, is used for the M that a presets bit is spaced apart the differential coding of M with this like best auto-correlation binary sequence, and presets bit and the differential coding result forms synchronous code block with said M;
The linear modulation unit is connected with said sequence generating unit, and the sequence that differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
Further, said sequence generating unit specifically comprises: counter and the Montgomery Algorithm device that is connected with this counter, said counter are used for since 0 progressively adding up 1 up to p+2L-1, and export count value c to the Montgomery Algorithm device;
Said Montgomery Algorithm device; Be used for each c value of counter output being carried out Montgomery Algorithm, obtain said p+2L bit successively like best auto-correlation binary sequence according to formula
.
Further, said differential coding unit comprises:
Shift register, its number of bits is M, is used to preset M bit, and exports the bit of high order end to synchronous code block register and XOR device successively;
The XOR device is used for the bit of said shift register high order end is carried out XOR with the next bit like best auto-correlation binary sequence that sequence generating unit generates successively, and will obtains the low order end that the XOR result imports said shift register;
The synchronous code block register is used to deposit the bit of said shift register input, finally obtains p+2L+M bit.
Further, M is that the maximum frequency deviation value of making a start according to pre-detection is provided with in advance, and the frequency deviation value of pre-detection is big more, and the M value is more little.
Further, p is provided with according to signal to noise ratio environment and channel condition in advance, and L is according to being provided with for receiving end detection window half strip length.
The code modulating method of the synchronous training symbol block encoding of the present invention modulator approach, device is easy to realize; Can effectively simplify the coded modulation process; Can be in Frame independent insertion can flexible configuration the synchronizing symbol piece, also applicable to low signal-to-noise ratio, have the system environments that there are the super large frequency deviation in abominable channel, sending and receiving end carrier wave.
Description of drawings
Fig. 1 is a single carrier continuous symbol linear modulation sketch map;
Fig. 2 is the sketch map of the synchronous training symbol block encoding of the present invention modulator approach;
Fig. 3 is a synchronizing symbol piece sketch map of the present invention;
Fig. 4 is M and presets the placement location sketch map of bit in M level shift register;
Fig. 5 is the reference circuit sketch map of a kind of M of presetting bit;
Fig. 6 is the two QPSK sketch mapes sending out agreement of transmitting-receiving;
Fig. 7 is the embodiment sketch map of synchronous training symbol block encoding modulator approach;
Fig. 8 is the embodiment sketch map of synchronous training symbol block encoding modulating device.
Embodiment
As shown in Figure 2, the synchronous training symbol block encoding of the present invention modulator approach comprises the steps:
Step 201: the generation cycle is the seemingly best auto-correlation binary sequence of p;
Prime field (GF (p)) the last cycle is the seemingly optimal period auto-correlation binary sequence (being also referred to as almost desirable auto-correlation binary sequence) of p; These sequences are difference set or the difference set sequences almost on the GF (p); Its method has a variety of, preferably, can adopt the method for Montgomery Algorithm to realize.
The item number N and the period p of ordered series of numbers can be provided with flexibly.Wherein, period p can be according to different signal to noise ratio environment and channel condition setting.Item number N holds detection window half strip length L that N=p+2L is set according to p with receiving.
Preferably, step 201 may further comprise the steps:
201a) make a start a counter c is set, this counter is progressively added up 1 since 0, be added to p+2L-1 always;
201b) for the value of each counter (since 0 up to p+2L-1), transmitting terminal will calculate following value
and obtain a bit;
It is the seemingly best auto-correlation binary sequence of p that all Montgomery Algorithm results were arranged in order the composition cycle, and also promptly, this cycle is that the binary sequence of p is (almost) difference set sequence on the finite field gf (p).
Step 202: will be somebody's turn to do the differential coding that is spaced apart the M bit like best auto-correlation binary sequence, wherein preceding M differential coding bit is for presetting bit;
Differential coding can be realized through XOR.Particularly, this step comprises:
202a) in M level shift register, preset M bit;
Make a start use one arbitrarily pseudo-random bits generator PSBG produce M and preset bit, perhaps use M the bit of predesignating to produce the individual bit that presets of M, it is as shown in Figure 4 that this M bit is admitted to (bit) shift register of a long M level;
Preferably; Adopt the preset bit of the XOR result of another shift register, thereby constantly produce the new bit that presets automatically, illustrate: as shown in Figure 5 as M level shift register; In 11 grades of shift registers, preset 11 bits; Be set to (1 011001100 0) from left to right like initial state, the bit of low order end bit and the individual deposit unit of n (as the 9th) is carried out XOR, when shift register XOR each time generates a new bit; Just sent into the right-hand member of M bit shift register and the high order end of shift register, simultaneously the shift register one-level that moves right by the left side that causes from the right side of order.
202b) with bit left one-level in the M level shift register; The bit that moves to left out gets into the synchronous code block register; And carry out XOR with the next bit (also being current Montgomery Algorithm result) of binary sequence, and then the XOR result is sent into the right-hand member of M level shift register successively;
This step can be described as: the leftmost bit of Montgomery Algorithm result and shift register is carried out XOR; The shift register bit one-level that moves to left, the bit that moves to left out gets into the synchronous code block register, and the XOR result sends into the shift register right-hand member.
Understandably, the description of this step lay particular emphasis on XOR and move to left after the result that changes of the bit position that causes, and the sequencing of not operation.
It should be noted that Montgomery Algorithm, move to left, the frequency of operation such as XOR is consistent.
202c) circulation execution in step 202b) p+2L until c=p+2L-1, finally obtains M+p+2L code block bit synchronously.
It is thus clear that, in counters throughout 0,1; 2 ..., after this p+2L of p+2L-1 the value; Montgomery Algorithm has also carried out p+2L operation; Obtained p+2L XOR result, and the M in the M level shift register presets bit and p+2L XOR result all is admitted to the synchronous code block register, finally obtain M+p+2L code block bit synchronously.
Step 203: the sequence that differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
A=-b, also promptly these 2 in complex number plane about former point symmetry.
The method of linear modulation can be QPSK (Quadrature Phase Shift Keying, QPSK), QAM (Quadrature Amplitude Modulation, quadrature amplitude modulation), perhaps with the QPSK of differential coding, and QAM.
With QPSK is example, and this is made a start this M+p+2L bit through a modulation mapping, is mapped to one arbitrarily on any diagonal of QPSK (4 phase phase-shift keying) planisphere, that is, if suppose the modulation constellation of this QPSK on complex number plane be
, e
(the i of π+φ),
Four points, the φ here be arbitrarily the planisphere initial phase ([0,2 π] is any; Arrange jointly by receiving-transmitting sides); For any synchronous code block bit x (the x value is 0 or 1), use any (two the sending out of transmitting-receiving appointed) of two following formula so, modulate:
After ovennodulation, the synchronizing symbol piece that finally obtains is as shown in Figure 3, is made up of M+2L+p modulation symbol, according to from left to right order M+2L+p symbol is all sent during transmission.
These synchronizing symbols constitute an autonomous block, can be inserted into Frame very easily Anywhere.
The coded modulation process is as shown in Figure 6 particularly:
In the drawings, c is a counter, since 0, up to p+2L-1, each value of counter is all carried out one ask Montgomery Algorithm; The leftmost bit of the shift register that 0 or 1 bit that generates and length are M is carried out XOR; Carrying out XOR bit afterwards subsequently sends into from M level shift register low order end; And this moment the M level shift register bit that moves to left; Leftmost bit gets into the synchronous code block register, and synchronous code block register total length is M+p+2L.Before coding beginning, M level shift register by at random or pseudo-random bits preset.Final effect is that preceding M bit of synchronous code block register is exactly aforementioned M bit shift register initial condition position; And the XOR output valve x when synchronously the M+1 bit of code block promptly is c=0; XOR output valve x when the M+2 bit of code block promptly is c=1 synchronously, by that analogy ....Synchronously code block is after sending into linear modulator, is modulated onto on the complex number plane on 2 about the initial point symmetry.
The present invention program can be applicable to different system environmentss through the flexible setting of M, L and p, as being provided with flexibly according to signal to noise ratio environment and channel condition, receipts end detection window length and frequency deviation region etc.
Particularly, receiving-transmitting sides is appointed same configurable parameter p jointly according to prior agreement (negotiation when perhaps starting shooting, the perhaps negotiation in the communication process), L, and M is retained in the system separately separately; In this embodiment, p, L, these three parameters of M are all configurable, also constituted the core of the present invention's " configurable " notion.
Below each configurable parameter is described:
1) parameter M
Receive end and make a start and to have bigger frequency deviation because of device difference, Doppler effect etc.; To different maximum frequency deviations; Just need different capturing frequency deviation scopes; Also need frequency offset estimation accuracy enough high in addition, the present invention can make the present invention program go for different frequency deviations through configuration M, and enough anti-deviation capabilities are provided.
The present invention can be configured to the value of parameter M allow to occur with transmitting-receiving two-end is maximum, perhaps the carrier frequency shift Δ f that occurs of maximum possible
MaxRelevant, usually, if the speed of supposition baseband signalling is B
SSymbol/second, carrier frequency shift Δ f
MaxUnit is Hz, and the normalization carrier wave frequency deviation does so
The maximum in theory frequency deviation that can detect of code block satisfies following formula synchronously:
Also promptly, detectable in theory maximum frequency deviation is the 1/2M of maximum character rate, if M obtains more little here; The scope of frequency deviation detection is big more so; When minimum M=1, current synchronous code block can detect the super large frequency deviation that is not more than 1/2 base band speed in theory, for example; Under the base band speed of 49.2M, we can detect the frequency shift (FS) that is not more than 24.6MHz in theory.But in satisfying all M of detection range, if M is too little, the estimated accuracy of frequency deviation will descend so.Preferably adopt following formula to confirm M:
Wherein, Δ f
MaxBe the maximum frequency deviation value of system's pre-detection, in other words, i.e. the maximum permissible frequency deviation value of system's maximum frequency deviation value that will occur or system regulation, B
SBe baseband signalling speed, unit is symbol/second,
Expression rounds downwards.
2) parameter L
The receipts end of code block need utilize a detection window to detect synchronously; In order to ensure enough big successful detection probability; Reduce false dismissal probability and false alarm probability simultaneously as far as possible; Detection window should be grown a bit as far as possible, but long detection window will cause the complexity of hardware and software to increase considerably, and the present invention can adapt with the receipts end of setting different size detection windows through the value that parameter L is set neatly.
L is for receiving end detection window half strip length; Its size can flexible configuration, and the length of receiving the end detection window under one times of baseband signalling speed is 2L+1, and the length that dual-rate is received the end detection window down is 4L+1; Correspondingly, the length of receiving the end detection window under n times of speed is 2nL+1.L value bigger can suppress to receive the secondary lobe that end detects, and under microwave channel, preferably, gets L=10 to 15, and simultaneously, in order under some special multipath channel, to carry out Multipath searching, the value of L can be bigger, and maximum can reach p-1.
3) parameter p
The present invention is through being provided with the length that parameter p can change synchronous code block, thereby changes the size of final accumulation baseband signal effective energy, resists different signal to noise ratio environment and channel condition.
Parameter p is the binary sequence cycle, can carry out flexible configuration, and in order to improve correlation, preferably, the p value is an odd prime, for example, begins from p=31, and all following values all are fine:
31 37 41 43 47 53 59 61
67 71 73 79 83 89 97 101
103 107 109 113 127 131 137 139
149 151 157 163 167 173 179 181
191 193 197 199 211 223 227 229
233 239 241 251 257 263 269 271
277 281 283 293 307 311 313 317
331 337 347 349 353 359 367 373
379 383 389 397 401 409 419 421
431 433 439 443 449 457 461 463
467 479 487 491 499 503 509 521
523 541 547 557 563 569 571 577
587 593 599 601 607 613 617 619
631 641 643 647 653 659 661 673
677 683 691 701 709 719 727 733
739 743 751 757 761 769 773 787
797 809 811 821 823 827 829 839
853 857 859 863 877 881 883 887
907 911 919 929 937 941 947 953
967 971 977 983 991 997 1009 1013
1019 1021 1031 1033 1039 1049 1051 1061
1063 1069 1087 1091 1093 1097 1103 1109
1117 1123 1129 1151 1153 1163 1171 1181
1187 1193 1201 1213 1217 1223 1229 1231
1237 1249 1259 1277 1279 1283 1289 1291
1297 1301 1303 1307 1319 1321 1327 1361
1367 1373 1381 1399 1409 1423 1427 1429
1433 1439 1447 1451 1453 1459 1471 1481
1483 1487 1489 1493 1499 1511 1523 1531
1543 1549 1553 1559 1567 1571 1579 1583
1597 1601 1607 1609 1613 1619 1621 1627
1637 1657 1663 1667 1669 1693 1697 1699
1709 1721 1723 1733 1741 1747 1753 1759
1777 1783 1787 1789 1801 1811 1823 1831
1847 1861 1867 1871 1873 1877 1879 1889
1901 1907 1913 1931 1933 1949 1951 1973
1979 1987 1993 1997 1999 2003 2011 2017
2027 2029 2039
Application example
The planisphere of supposing receiving-transmitting sides agreement normalization QPSK is 4 following complex points, and is as shown in Figure 7,
Baseband signalling speed is 49.2M symbol/second, signal to noise ratio 20dB, and maximum frequency deviation 2MHz is according to formula
Get and decide M=8, signal to noise ratio environment, the channel condition that possibly face according to system are got and are decided p=257, L=15, and the process of training symbol block encoding modulation synchronously comprises:
A) presetting 8 bits is 01100110;
B) make c=0,1,2,3 ..., 286, calculate (c respectively
128Mod 257) mod2, obtain 287 bits thus and be described below:
0，1，1，0，1，0，0，0，1，1，0，1，0，1，0，1，1，1，1，0，0，1，1，1，0，1，1，0，0，1，1，1，1，0，1，1，1，0，0，0，0，0，1，0，1，0，1，0，0，1，1，0，1，0，0，0，0，1，1，1，1，1，1，0，1，0，0，1，1，0，1，0，1，1，0，0，0，0，0，1，0，1，0，0，1，0，0，0，1，1，0，0，1，0，0，1，0，0，1，1，1，0，0，0，1，0，0，0，0，0，0，1，0，1，1，0，1，1，1，0，1，1，1，1，1，0，0，0，1，1，0，0，0，1，1，1，1，1，0，1，1，1，0，1，1，0，1，0，0，0，0，0，0，1，0，0，0，1，1，1，0，0，1，0，0，1，0，0，1，1，0，0，0，1，0，0，1，0，1，0，0，0，0，0，1，1，0，1，0，1，1，0，0，1，0，1，1，1，1，1，1，0，0，0，0，1，0，1，1，0，0，1，0，1，0，1，0，0，0，0，0，1，1，1，0，1，1，1，1，0，0，1，1，0，1，1，1，0，0，1，1，1，1，0，1，0，1，0，1，1，0，0，0，1，0，1，1，0，1，1，0，1，0，0，0，1，1，0，1，0，1，0，1，1，1，1，0，0，1，1，1，0，1，1，0，0，1
C) above-mentioned 287 bits are sent into the XOR device according to order from left to right, as shown in Figure 5, the bit after the new XOR that obtains is:
0?0?0?0?1?1?1?0?1?1?0?1?1?0?1?1?0?0?1?1?1?1?0?0?0?1?0?1?1?0?1?1?1?1?1?0?0?0?1?1?11?0?0?1?0?0?1?1?0?1?0?0?0?0?1?1?1?0?1?1?1?1?1?0?1?0?0?0?1?0?1?1?0?0?0?0?1?0?0?1?1?0?0?11?0?0?0?0?0?0?0?1?0?1?0?0?1?1?1?1?0?1?1?0?1?1?1?1?0?0?1?1?0?1?0?0?1?0?0?0?1?0?1?0?1?0?11?1?0?1?1?0?1?0?0?1?1?0?0?0?0?1?0?0?1?0?0?0?0?1?1?0?1?0?1?1?1?1?1?1?1?0?0?1?1?0?0?1?1?01?1?1?1?0?0?1?0?1?1?1?0?1?0?0?0?0?0?1?0?0?0?1?1?1?1?0?1?0?0?1?1?0?1?1?0?0?0?0?1?1?1?0?00?0?0?1?0?0?1?0?1?1?1?0?0?0?0?1?1?0?0?1?0?0?1?0?0?1?0?0?0?1?1?1?1?1?0?0?1?1?0?0?1?0?1?00?1?0?0?0?1?1?1?0?0?0?1?1?0?0?1?0?1?1?0?1?1?1?1?0?0
D) before above-mentioned 287 bits, have 8 and preset bit, obtain new synchronization bit piece:
0?1?1?0?0?1?1?0?0?0?0?0?1?1?1?0?1?1?0?1?1?0?1?1?0?0?1?1?1?1?0?0?0?1?0?1?1?0?1?1?11?1?0?0?0?1?1?1?1?0?0?1?0?0?1?1?0?1?0?0?0?0?1?1?1?0?1?1?1?1?1?0?1?0?0?0?1?0?1?1?0?0?0?01?0?0?1?1?0?0?1?1?0?0?0?0?0?0?0?1?0?1?0?0?1?1?1?1?0?1?1?0?1?1?1?1?0?0?1?1?0?1?0?0?1?0?00?1?0?1?0?1?0?1?1?1?0?1?1?0?1?0?0?1?1?0?0?0?0?1?0?0?1?0?0?0?0?1?1?0?1?0?1?1?1?1?1?1?1?00?1?1?0?0?1?1?0?1?1?1?1?0?0?1?0?1?1?1?0?1?0?0?0?0?0?1?0?0?0?1?1?1?1?0?1?0?0?1?1?0?1?1?00?0?0?1?1?1?0?0?0?0?0?1?0?0?1?0?1?1?1?0?0?0?0?1?1?0?0?1?0?0?1?0?0?1?0?0?0?1?1?1?1?1?0?01?1?0?0?1?0?1?0?0?1?0?0?0?1?1?1?0?0?0?1?1?0?0?1?0?1?1?0?1?1?1?1?0?0
E) utilize formula
(1+j) (1-2x) (wherein j is the imaginary part of plural number) with these 295 bit modulation to cornerwise 2 of QPSK planisphere " left side down-upper right ", the synchronizing symbol piece that to obtain a length be 295 symbols.
So far, we have accomplished the coded modulation process of a synchronizing symbol piece that obtains according to signal to noise ratio condition and frequency deviation condition, and follow-up, this encoding block can be inserted into any old place of Frame at any time, are used for carrying out synchronously receiving end.
Accordingly, the present invention also provides a kind of synchronous training symbol block encoding modulating device, and as shown in Figure 8, this device comprises:
Sequence generating unit, being used for the generation cycle is the seemingly best auto-correlation binary sequence of p;
The code block generation unit is connected with said sequence generating unit, be used for this is spaced apart the differential coding of M bit like best auto-correlation binary sequence, wherein before M differential coding bit for presetting bit;
The linear modulation unit is connected with said sequence generating unit, and the sequence that is used for differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
Preferably, said sequence generating unit specifically comprises: counter and the Montgomery Algorithm device that is connected with this counter, said counter are used for since 0 progressively adding up 1 up to p+2L-1, and export count value c to the Montgomery Algorithm device;
Said Montgomery Algorithm device; Be used for each c value of counter output being carried out Montgomery Algorithm, obtain said p+2L bit successively like best auto-correlation binary sequence according to formula
.
Preferably, said differential coding unit comprises:
Shift register, its number of bits is M, is used to preset M bit, and exports the bit of high order end to synchronous code block register and XOR device successively;
The XOR device is used for the bit of said shift register high order end is carried out XOR with the next bit like best auto-correlation binary sequence that sequence generating unit generates successively, and will obtains the low order end that the XOR result imports said shift register;
The synchronous code block register is used to deposit the bit of said shift register input, finally obtains p+2L+M bit.
M is that the maximum frequency deviation value of making a start according to pre-detection is provided with in advance, and the frequency deviation value of pre-detection is big more, and the M value is more little, and preferably, the maximum frequency deviation value of pre-detection is Δ f
MaxThe time, M meets the following conditions
B wherein
SBe baseband signalling speed, unit is symbol/second,
Expression rounds downwards.
As stated, p is provided with according to signal to noise ratio environment and channel condition in advance, and L is according to being provided with for receiving end detection window half strip length.
Than prior art, the beneficial effect of technical scheme of the present invention is mainly reflected in following several aspect:
Code modulating method of the present invention is realized simple, has effectively simplified code modulated process;
This scheme is insensitive for the initial phase deviation of reception carrier, also is sane for phase noise, for frame synchronization, symbol thick synchronously and frequency offset estimating do not produce too much influence.
This technical scheme can be according to signal to noise ratio; Synchronous error requires, system allows maximum frequency deviation (maximum frequency deviation that perhaps possibly occur), carries out extremely flexible and changeable configuration, with the demand of adaptive system; Comprise: according to the difference of maximum frequency deviation value; Set different parameter M, make and to satisfy frequency offset estimation range, can farthest improve estimated accuracy again; According to different signal to noise ratio situations (the perhaps minimum permission signal to noise ratio of system), the size of flexible configuration p is so that satisfy different signal to noise ratio demands; According to the hardware resource of receiving end with to the requirement of detection probability, flexible configuration iSCSI receiving end window parameter L;
The coding of the synchronizing symbol piece of the present invention's design establishes one's own system, and with data independence, can be used as a fully independently module, and the random optional position that is inserted into Frame perhaps is inserted in the middle of continuous a plurality of Frame,
This technical scheme can make receives end in a synchronizing symbol piece; Disposable completion symbol regularly; Frame position is synchronous; Three tasks of super large frequency offset estimating, and the frequency deviation that can estimate can be quite big (theoretical maximum can reach character rate 1/2), and this is difficult to accomplish in many systems the insides (such as aforesaid satellite TDMA packet communication);
The synchronous code block of the present invention has good correlation, has identifiability preferably, receives and holds the characteristic that can utilize synchronizing signal to identify the arrival of synchronous code block easily;
The concrete system coding that the present invention provides has only only used simple Montgomery Algorithm, bit XOR and simple modulation.But and be particularly suitable for utilizing software radio, or configurable programming circuit carry out the auto-adaptive parameter adjustment to adapt to different channel conditions along with the state of link, can also calculate in advance in the memory of the system of leaving in.
In sum; The inventive method and device can be in Frame independent insertion can flexible configuration the synchronizing symbol piece; So that at low signal-to-noise ratio, have abominable channel, the sending and receiving end carrier wave exists under the situation of super large frequency deviation, can make receive end accomplish preassigned timing synchronization, frame position synchronously, three mission criticals of carrier frequency synchronization.
One of ordinary skill in the art will appreciate that all or part of step in the said method can instruct related hardware to accomplish through program, said program can be stored in the computer-readable recording medium, like read-only memory, disk or CD etc.Alternatively, all or part of step of the foregoing description also can use one or more integrated circuits to realize.Correspondingly, each the module/unit in the foregoing description can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Claims (13)
1. synchronous training symbol block encoding modulator approach is characterized in that this method comprises:
Sequence generates step, and the generation cycle is the seemingly best auto-correlation binary sequence of p;
Code block generates step, and this is spaced apart the differential coding of M bit like best auto-correlation binary sequence, wherein before M differential coding bit for presetting bit;
The linear modulation step, the sequence that differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
2. the method for claim 1; It is characterized in that: said sequence generates step and specifically comprises: according to formula
successively to c=0; 1,2,3... (p+2L-2); (p+2L-1) carry out Montgomery Algorithm; Obtain this p+2L bit like best auto-correlation binary sequence successively, wherein, p and L are for be provided with in advance.
3. according to claim 1 or claim 2 method, it is characterized in that: said code block generates step and specifically comprises: in M level shift register, preset M bit;
With bit left one-level in the M level shift register, the bit that moves to left out gets into the synchronous code block register, and carries out XOR with said next bit like best auto-correlation binary sequence successively, the XOR result is sent into the right-hand member of M level shift register; Circulation is carried out this step p+2L time, until c=p+2L-1, finally obtains M+p+2L code block bit synchronously.
4. the method for claim 1 is characterized in that: M is that the maximum frequency deviation value of making a start according to pre-detection is provided with in advance, and the frequency deviation value of pre-detection is big more, and the M value is more little.
5. the method for claim 1, it is characterized in that: the maximum frequency deviation value of pre-detection is Δ f
MaxThe time, M meets the following conditions
B wherein
SBe baseband signalling speed, unit is symbol/second,
Expression rounds downwards.
6. the method for claim 1, it is characterized in that: p is provided with according to signal to noise ratio environment and channel condition in advance, and L is provided with according to receiving end detection window half strip length.
7. the method for claim 1 is characterized in that: the method for linear modulation is the QPSK of QPSK (QPSK), quadrature amplitude modulation (QAM), band differential coding or the QAM of band differential coding.
8. synchronous training symbol block encoding modulating device is characterized in that this device comprises:
Sequence generating unit is used for according to ordered series of numbers a
n=n generation the cycle is the seemingly best auto-correlation binary sequence of p;
The code block generation unit is connected with said sequence generating unit, is used for the M that a presets bit is spaced apart the differential coding of M with this like best auto-correlation binary sequence, and presets bit and the differential coding result forms synchronous code block with said M;
The linear modulation unit is connected with said sequence generating unit, and the sequence that differential coding is obtained is as two the some as of synchronization code sequence linear modulation on the complex number plane, b, and a=-b.
9. device as claimed in claim 8; It is characterized in that: said sequence generating unit specifically comprises: counter and the Montgomery Algorithm device that is connected with this counter; Said counter is used for since 0 progressively adding up 1 up to p+2L-1, and exports count value c to the Montgomery Algorithm device;
Said Montgomery Algorithm device; Be used for each c value of counter output being carried out Montgomery Algorithm, obtain said p+2L bit successively like best auto-correlation binary sequence according to formula
.
10. like claim 8 or 9 described devices, it is characterized in that said differential coding unit comprises:
Shift register, its number of bits is M, is used to preset M bit, and exports the bit of high order end to synchronous code block register and XOR device successively;
The XOR device is used for the bit of said shift register high order end is carried out XOR with the next bit like best auto-correlation binary sequence that sequence generating unit generates successively, and will obtains the low order end that the XOR result imports said shift register;
The synchronous code block register is used to deposit the bit of said shift register input, finally obtains p+2L+M bit.
11. device as claimed in claim 8 is characterized in that: M is that the maximum frequency deviation value of making a start according to pre-detection is provided with in advance, and the frequency deviation value of pre-detection is big more, and the M value is more little.
12. device as claimed in claim 8 is characterized in that: the maximum frequency deviation value of pre-detection is Δ f
MaxThe time, M meets the following conditions
B wherein
SBe baseband signalling speed, unit is for will number/second,
Expression rounds downwards.
13. device as claimed in claim 8 is characterized in that: p is provided with according to signal to noise ratio environment and channel condition in advance, and L is according to being provided with for receiving end detection window half strip length.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102959918A (en) * | 2012-08-31 | 2013-03-06 | 华为技术有限公司 | A training sequence generating method, a training sequence generating device, and an optical communication system |
| WO2018201391A1 (en) * | 2017-05-04 | 2018-11-08 | Oppo广东移动通信有限公司 | Timing method for synchronization signal block, and related product |
| CN114584258A (en) * | 2022-02-15 | 2022-06-03 | 烽火通信科技股份有限公司 | Service delay reduction method, device, equipment and readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404307A (en) * | 2001-08-24 | 2003-03-19 | 国家广播电影电视总局广播科学研究院 | Data frame forming method and corresponding interleaving and encoding modulation method |
| CN1870465A (en) * | 2005-05-24 | 2006-11-29 | 都科摩（北京）通信技术研究中心有限公司 | Generating method, communication system and communication method of circulation training sequence |
| CN101184078A (en) * | 2007-12-24 | 2008-05-21 | 清华大学 | Method for filling protection spacing in orthogonal frequency division multiplexing modulation system and communication system thereof |
| EP2043318A2 (en) * | 2007-09-27 | 2009-04-01 | Intel Corporation | Preamble techniques for communications networks |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6519275B2 (en) * | 2001-06-29 | 2003-02-11 | Motorola, Inc. | Communications system employing differential orthogonal modulation |
| US9065714B2 (en) * | 2007-01-10 | 2015-06-23 | Qualcomm Incorporated | Transmission of information using cyclically shifted sequences |
-
2010
- 2010-09-14 CN CN201010282487.9A patent/CN102404071B/en active Active
- 2010-11-26 WO PCT/CN2010/079162 patent/WO2012034319A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404307A (en) * | 2001-08-24 | 2003-03-19 | 国家广播电影电视总局广播科学研究院 | Data frame forming method and corresponding interleaving and encoding modulation method |
| CN1870465A (en) * | 2005-05-24 | 2006-11-29 | 都科摩（北京）通信技术研究中心有限公司 | Generating method, communication system and communication method of circulation training sequence |
| EP2043318A2 (en) * | 2007-09-27 | 2009-04-01 | Intel Corporation | Preamble techniques for communications networks |
| CN101184078A (en) * | 2007-12-24 | 2008-05-21 | 清华大学 | Method for filling protection spacing in orthogonal frequency division multiplexing modulation system and communication system thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102959918A (en) * | 2012-08-31 | 2013-03-06 | 华为技术有限公司 | A training sequence generating method, a training sequence generating device, and an optical communication system |
| CN102959918B (en) * | 2012-08-31 | 2015-02-25 | 华为技术有限公司 | A training sequence generating method, a training sequence generating device, and an optical communication system |
| US9698909B2 (en) | 2012-08-31 | 2017-07-04 | Huawei Technologies Co., Ltd. | Training sequence generation method, training sequence generation apparatus, and optical communications system |
| WO2018201391A1 (en) * | 2017-05-04 | 2018-11-08 | Oppo广东移动通信有限公司 | Timing method for synchronization signal block, and related product |
| US11297580B2 (en) | 2017-05-04 | 2022-04-05 | Guangdong Oppo Mobile Telecommunications Corp., Ltd. | Timing method for synchronization signal block, and related product |
| CN114584258A (en) * | 2022-02-15 | 2022-06-03 | 烽火通信科技股份有限公司 | Service delay reduction method, device, equipment and readable storage medium |
| CN114584258B (en) * | 2022-02-15 | 2023-05-26 | 烽火通信科技股份有限公司 | Service delay reduction method, device, equipment and readable storage medium |
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