CN101459639A - Adaptive complementary code keying demodulation apparatus and method - Google Patents

Abstract

The invention provides a self-adaptive complementary code shift keying demodulation device, which comprises a receiver, a modulation vector error computing device, a selection device, a first demodulator and a second demodulator, wherein the receiver, the modulation vector error computing device and the selection device are connected in turn, the selection device is also respectively connected with the first demodulator and the second demodulator, the receiver obtains modulation vector errors of a chip through demodulating single chips, the modulation vector error computing device estimates the size of a current phase error through the modulation vector errors, and the selection device is used to select the first demodulator or the second demodulator according to the size of the phase errors. The self-adaptive complementary code shift keying demodulation device has the beneficial technical effect that when the sizes the phase errors are different, the device can self-adaptively adjust the demodulation method to achieve performance optimization.

Description

A kind of adaptive complementary code keying demodulation apparatus and method

Technical field

The present invention relates to a kind of demodulating equipment and method, relate in particular to a kind of adaptive complementary code keying demodulation apparatus and method.

Background technology

In IEEE 802.11b standard, when transmission rate is 11Mbps, adopt the modulation system of CCK (complementary code keying).The CCK modulation is a kind of special shape of M ary quadrature keying (MOK).

In the CCK modulation, per 8 data bit (b ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆, b ₇) coded modulation becomes a transmitted codewords s, to bit to (b ₀, b ₁) carry out the DQPSK modulation by table 1, corresponding phase is

Table 1:DQPSK modulation

With k symbol Be designated as

Then have

To (b ₂, b ₃, b ₄, b ₅, b ₆, b ₇) in bit to (b ₂, b ₃), (b ₄, b ₅), (b ₆, b ₇) carry out the QPSK modulation by table 2 respectively, corresponding phase is

Table 2:QPSK modulation

n＝2，3，4

Obtain code word through CCK coding back:

Each code word has 256 code words by 8 data bit modulation.Common factor

Four kinds of values are arranged.64 code words and 6 data bit (b with identical common factor ₂, b ₃, b ₄, b ₅, b ₆, b ₇) correspondence, have good cross correlation and autocorrelation.

The demodulation of CCK is also relevant with IEEE 802.11b frame structure, Fig. 1 is the frame structure of IEEE 802.11b: receiver is when reception PLCP (physical layer convergence protocol) is leading, because SYNC (synchronously) field is known, be easier to obtain carrier synchronization, thereby in the demodulation of follow-up DBPSK (difference two is to the translation keying) or DQPSK (difference four-way translation keying), initial fixed phase arranged.Follow-up DBPSK or DQPSK are separated timing, carrier wave can be asynchronous, be that receiver can exist phase error, suppose that this phase error is a constant in a PPDU (PLCP protocol Data Unit), therefore can demodulate information by the phase difference of front and back chip.

CCK demodulation and performance evaluation thereof in AWGN (additive white Gaussian noise) channel has introduction in paper " A Performance of Complementary Code Keying Codes " (Yusung Lee, Hyuncheol Park work) to CCK.Mainly contain dual mode, a kind of is the maximum likelihood mode, because used 256 correlators, claims the demodulation mode with 256 correlators here; Another kind is the correlation magnitude demodulation mode, because used 64 correlators, claims the demodulation mode with 64 correlators here.Though need 4 times correlator quantity with the demodulator of 256 correlators, but owing to only get relevant real part with the demodulator of 256 correlators, and will get relevant mould with the demodulator of 64 correlators, so the multiplication of each related operation of the latter is the former 3 times.So the increase of the complexity of bringing with the demodulation of 256 correlators is little.Following formula is to get the formula of real part and delivery:

real{(a+bj)(c+dj)}＝ac-bd

‖(a+bj)(c+dj)‖ ²＝(ac-bd) ²+(bc+ad) ²

Correlator generally adopts the mode of Fast W alsh conversion, can reduce operand significantly.

Fig. 2 is that the CCK with 64 correlators separates the ber curve that is in harmonious proportion with the CCK demodulation of 256 correlators.This ber curve uses Matlab to carry out Monte Carlo emulation and obtains.256 correlators represent the CCK demodulation with 256 correlators, 64 correlators represent the CCK demodulation with 64 correlators, 256 correlators, phase error represents the CCK demodulation with 256 correlators when the phase error of π/12 can not be corrected, 64 correlators, phase error represent the CCK demodulation with 64 correlators when the phase error of π/12 can not be corrected.As can be seen when the phase error of π/12 can not be corrected, CCK demodulation with 64 correlators there is not influence substantially, this is because are modulo operations during back 6 bit demodulation, therefore phase error can not cause the mistake of demodulation, and preceding 2 bits are differential ference spirals, so phase error does not influence the mistake of demodulation substantially.Yet bigger to the CCK demodulation influence with 256 correlators, its performance descends significantly.

Summary of the invention

The object of the present invention is to provide a kind of adaptive complementary code keying demodulation apparatus and method, the demodulator that this adaptive complementary code keying demodulation apparatus and method are intended to solve prior art is when phase error varies in size, and demodulator performance can not reach the problem of optimization.

The invention provides a kind of adaptive complementary code keying demodulation apparatus, comprise receiver, the modulation vector error calculating device, choice device, first demodulator and second demodulator, described receiver, the modulation vector error calculating device links to each other successively with choice device, described choice device also respectively with first demodulator, second demodulator links to each other, described receiver is by carrying out demodulation to single chip, obtain the modulation vector error of described chip, described modulation vector error calculating device is estimated current phase error size by this modulation vector error, and makes choice device select first demodulator or second demodulator according to the phase error size.

Technical scheme of the present invention also comprises: described first demodulator is the demodulator with 256 correlators, and described second demodulator is the demodulator with 64 correlators.

Technical scheme of the present invention also comprises: described multiplexing with the factor in the demodulator of 256 correlators with the correlator in the demodulator of 64 correlators It all is 1 correlator.

Another technical scheme of the present invention is: a kind of adaptive complementary code keying demodulation method comprises: single chip is carried out demodulation, obtain the modulation vector error of described chip; Estimate current phase error size by the modulation vector error; Select demodulator according to the phase error size.

Technical scheme of the present invention also comprises: described selection demodulator is specially: adopt CCK demodulation with 256 correlators at the leading portion of PSDU (PLCP service data unit), when the modulation vector error surpasses a certain given thresholding, adopt CCK demodulation with 64 correlators.

Technical scheme of the present invention has following advantage or beneficial effect: adaptive complementary code keying demodulation apparatus of the present invention and method adopt CCK demodulation with 256 correlators at the leading portion of PSDU, when the modulation vector error surpasses a certain given thresholding, change and adopt CCK demodulation with 64 correlators, performance can not descend when different phase errors is arranged.

Description of drawings

Fig. 1 is the frame structure schematic diagram of IEEE 802.11b;

Fig. 2 is that the CCK with 64 correlators separates the ber curve that is in harmonious proportion with the CCK demodulation of 256 correlators;

Fig. 3 is the structural representation of adaptive complementary code keying demodulation apparatus of the present invention;

Fig. 4 is the schematic diagram with the CCK demodulation of 256 correlators;

Fig. 5 is the schematic diagram with the CCK demodulation of 64 correlators;

Fig. 6 is the flow chart of adaptive complementary code keying demodulation method of the present invention.

Embodiment

In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.

See also Fig. 3, be the structural representation of adaptive complementary code keying demodulation apparatus of the present invention.Adaptive complementary code keying demodulation apparatus of the present invention comprises receiver 10, modulation vector error calculating device 20, choice device 30, with the demodulator 40 of 256 correlators with the demodulator 50 of 64 correlators.Receiver 10 is by carrying out demodulation to single chip, obtain the modulation vector error of this chip, plural number that promptly demodulates and the distance between the ideal constellation point, modulation vector error calculating device 20 is estimated current phase error size by this modulation vector error, and makes the demodulator 40 of 256 correlators of choice device 30 select tapes or with the demodulator 50 of 64 correlators according to the phase error size.Because the SYNC field in a frame is known, obtain the synchronous of carrier wave easily, and the field of back is not easy to obtain the synchronous of carrier wave, therefore forward more PSDU chip has more little phase error.Again owing to the CCK demodulation with 256 correlators is applicable to the situation that phase error is less, and be applicable to the situation that phase error is bigger with the CCK demodulation of 64 correlators, CCK demodulator of the present invention adopts CCK demodulation with 256 correlators at the leading portion of PSDU, when the modulation vector error surpasses a certain given thresholding, change and adopt CCK demodulation with 64 correlators.64 correlators are subclass of 256 correlators, wherein the factor of 64 correlators All be the factor of 1,64 correlator in can multiplexing 256 correlators

It all is 1 correlator.

See also Fig. 4, be schematic diagram with the CCK demodulation of 256 correlators.Demodulation mode with 256 correlators is: the advanced line phase compensation of error of received signal, carry out related calculation with 256 correlators again, and select the correlator sequence number of the relevant real part maximum of output, and then demodulate 8 data bits $({\hat{b}}_0^{\′},{\hat{b}}_1^{\′},{\hat{b}}_2,{\hat{b}}_3,{\hat{b}}_4,{\hat{b}}_5,{\hat{b}}_6,{\hat{b}}_7),({\hat{b}}_2,{\hat{b}}_3,{\hat{b}}_4,{\hat{b}}_5,{\hat{b}}_6,{\hat{b}}_7)$ For will exporting bit,

Be absolute coding, need be back into absolute phase, deduct fixed phase then, obtain relative phase

Table look-up and obtain 2 output bits $({\hat{b}}_0,{\hat{b}}_1).$

Note K the symbol that be to receive, and transmission is m code word in all 256 code words,

Be to carry out relevant code word, and what get is n code word with k symbol,

Be the relevant of them.

Phase error for receiver.

$r_{m,n}^{\left(k\right)}=<r_m^{\left(k\right)},s_n^{\left(k\right)}>$

Because phase error is constant in a PPDU, and receives PLCP and obtain therefore can estimate phase error synchronously when leading, PSDU is separated timing this phase error compensation is gone back.

See also Fig. 5, be schematic diagram with the CCK demodulation of 64 correlators.Demodulation mode with 64 correlators is: received signal and 64 correlators carry out related calculation, and select the relevant mould value maximum correlation value sequence number of output, and then demodulate 6 output bits

It is relevant that mould value maximum correlation value and the mould value maximum correlation value of last symbol are carried out, and can obtain relative phase, and then table look-up and obtain 2 output bits

Below the demodulation mode of mathematics mark and 256 correlators in the same, at this moment Promptly

For

Be not with

Part, therefore

Have 64.

$r_{m,n}^{\left(k\right)}=<r_m^{\left(k\right)},c_n^{\left(k\right)}>$

$\left|r_{m,n}^{\left(k\right)}\right|\&le;|<c_m^{\left(k\right)},c_n^{\left(k\right)}>|+|<n_m^{\left(k\right)},c_n^{\left(k\right)}>|$

By selecting maximum mould, obtain most probable

Wherein

Carry out relevantly with previous correlation again, obtain phase difference

See also Fig. 6, be the flow chart of adaptive complementary code keying demodulation method of the present invention.Adaptive complementary code keying demodulation method of the present invention comprises:

Step 100: single chip is carried out demodulation, obtain the modulation vector error of this chip, plural number that promptly demodulates and the distance between the ideal constellation point;

Step 200: estimate current phase error size by the modulation vector error;

Step 300: make choice device select demodulator according to the phase error size, adopt CCK demodulation, when the modulation vector error surpasses a certain given thresholding, change and adopt CCK demodulation with 64 correlators with 256 correlators at the leading portion of PSDU.

The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (5)

1, a kind of adaptive complementary code keying demodulation apparatus, it is characterized in that, comprise receiver, the modulation vector error calculating device, choice device, first demodulator and second demodulator, described receiver, the modulation vector error calculating device links to each other successively with choice device, described choice device also respectively with first demodulator, second demodulator links to each other, described receiver is by carrying out demodulation to single chip, obtain the modulation vector error of described chip, described modulation vector error calculating device is estimated current phase error size by this modulation vector error, and makes choice device select first demodulator or second demodulator according to the phase error size.

2, adaptive complementary code keying demodulation apparatus as claimed in claim 1 is characterized in that, described first demodulator is the demodulator with 256 correlators, and described second demodulator is the demodulator with 64 correlators.

3, adaptive complementary code keying demodulation apparatus as claimed in claim 2 is characterized in that, and is described multiplexing with the factor in the demodulator of 256 correlators with the correlator in the demodulator of 64 correlators

It all is 1 correlator.

4, a kind of adaptive complementary code keying demodulation method comprises:

Single chip is carried out demodulation, obtain the modulation vector error of described chip;

Estimate current phase error size by the modulation vector error;

Select demodulator according to the phase error size.

5, adaptive complementary code keying demodulation method as claimed in claim 4, it is characterized in that, described selection demodulator is specially: adopt CCK demodulation with 256 correlators at the leading portion of PSDU, when the modulation vector error surpasses a certain given thresholding, adopt the CCK demodulation with 64 correlators.

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