RU2271607C1 - Radio communication line affording enhanced security of data transferred - Google Patents

Abstract

FIELD: digital data transfer over radio channels to space and ground communication systems using noise-like signals.

SUBSTANCE: proposed radio transmitting line that has data source, pulse-width modulator, phase modulator, balance modulator, power amplifier, phase-keyed signal generator, carrier generator, transmitter synchronizer, and transmitting antenna on transmitting end as well as receiving antenna, mixer, intermediate-frequency amplifier, corrector, demodulator, heterodyne, reference phase-keyed signal generator, receiver synchronizer, and data receiver on receiving end is provided, in addition, with switch, decoder, flip-flop, random-access memory, and random-access memory address generator introduced in transmitting and receiving ends, respectively.

EFFECT: enhanced security of data transferred.

1 cl, 2 dwg

Description

The invention relates to the field of transmission of discrete information and can be used in radio channels for transmitting information in space and terrestrial communication systems using noise-like signals.

Known radio communication systems with noise-like signals, for example, as. 651492, which serves to transmit discrete information. The main disadvantage of this system is the low secrecy of the transmitted information.

Also known is a radiotelephone communication system with phase-shifted broadband signals (see L. Varakin, “Communication Systems with Noise-Like Signals”, M., “P and S”, 1985, p. 16, Fig. 1.7), the main disadvantage of which is is a low secrecy of the transmitted information.

Closest to the technical nature of the claimed device is the device shown in the book of L. Varakin. "Communication systems with noise-like signals", M., "P and C", 1985, p. 18, Fig. 1.9, taken as a prototype.

The functional diagram of the prototype device is shown in figure 1, where the following notation is introduced:

transmitting part:

1 - source of information;

2 - pulse-width modulator (PWM);

3 - phase modulator;

4 - balanced modulator;

5 - power amplifier;

6 - phase-manipulated (FM) signal generator (pseudo-random sequence generator);

7 - transmitter synchronizer;

8 - carrier frequency generator;

9 - transmitting antenna;

receiving part:

10 - receiving antenna;

11 - mixer;

12 - intermediate frequency amplifier;

13 - correlator;

14 - demodulator;

15 - recipient of information;

16 - local oscillator;

17 - generator reference phase-shift (FM) signal;

18 - receiver synchronizer.

The prototype device consists of a transmitting and receiving part.

The transmitting part contains a series-connected information source 1, which is the input of the device, pulse-width modulator 2, phase modulator 3, balanced modulator 4 and power amplifier 5, the output of which is connected to the transmitting antenna 9. In addition, it contains a transmitter synchronizer 7, the first output which is connected to the second input of the pulse-width modulator 2, and the second output is connected to the second input of the phase modulator 3 through a phase-shift (FM) signal generator 6; and also contains a carrier frequency generator 8, the output of which is connected to the second input of the balanced modulator 4.

The receiving part comprises a receiving antenna 10 connected in series, a mixer 11, an intermediate frequency amplifier 12, a correlator 13, a demodulator 14, and an information receiver 15, which is the output of the device. In addition, it contains a receiver synchronizer 18, the first output of which through the local oscillator 16 is connected to the second input of the mixer 11, and the second output of the receiver synchronizer 18 is connected to the second inputs of the demodulator 14 and the correlator 13, the output of which is connected to the input of the receiver synchronizer 18, the third output of which the reference FM signal generator 17 is connected to the third input of the correlator 13.

The prototype device operates as follows.

From the information source 1, a telephone message arrives at the first input of a pulse-width modulator (PWM) 2, from the output of which the PWM signal is fed to the first input of the phase modulator 3, the second input of which receives a phase-shifted broadband signal (FM SHPS) from the output of the FM signal generator 6 The operation of the pulse-width modulator 2 and the FM signal generator 6 is controlled by the transmitter synchronizer 7, which generates the necessary frequencies and control signals.

The FM signal from the output of the phase modulator 3 containing information is fed to the first input of the balanced modulator 4, the second input of which receives the FM signal from the output of the carrier frequency generator 8. In the balanced modulator 4, the FM signal is balanced modulated with the carrier frequency. In a power amplifier 5 FM, the signal is amplified to the required value and then transmitted through the antenna 9 into space.

The signal received by the receiving antenna 10 is fed to a mixer 11, where it is transferred using an local oscillator 16 to an intermediate frequency, amplified in an intermediate frequency amplifier 12, and fed to the first input of the correlator 13, the third input of which is supplied with pulses from the reference FM signal generator 17. In the correlator 13 optimal signal processing is performed, as a result of which a telephone message is generated at the output of the correlator 13 in the form of a PWM signal, which is fed to the input of the receiver synchronizer 18 and the first input of the demodulator 14, where information component. From the output of the demodulator 14, the received telephone message is sent to the recipient of information 15. The receiver synchronizer 18, controlling the local oscillator 16, searches for the FM signal in frequency and time, and then maintains synchronism in the receiving part by controlling the operation of the reference FM signal generator 17, the correlator 13 and the demodulator fourteen.

The disadvantage of the prototype device is the low secrecy of the transmitted information, because information is broadcast in unprotected form.

To eliminate this drawback in a radio communication line with increased secrecy of the transmitted information, which contains in the transmitting part: a series-connected information source, which is the input of the device, pulse-width modulator, phase modulator, balanced modulator and power amplifier, the output of which is connected to the transmitting antenna, and also containing a carrier frequency generator, the output of which is connected to the second input of the balanced modulator, and a transmitter synchronizer, the first output of which is connected to the W th input of the pulse width modulator, and a second synchronizer output connected to the input of the transmitter oscillator phase manipulated signal; in the receiving part: a receiving antenna, a mixer, an intermediate frequency amplifier, a correlator, a demodulator, and an information receiver, which is the output of the device, as well as a receiver synchronizer, the first output of which is connected through the local oscillator to the second input of the mixer, and the second output of the receiver synchronizer is connected to the second inputs of the demodulator and correlator, the output of which is connected to the input of the receiver synchronizer, the third output of which is connected to the input of the reference phase oscillator generator of the transmitted signal: the transmitter switch, the random access memory of the transmitter, the address generator of the RAM of the transmitter, the counting trigger of the transmitter and the decoder of the transmitter, while the second output of the transmitter synchronizer is connected to the counting input of the address of the address of the RAM of the transmitter, the output of which is connected with address input of the RAM of the transmitter, serial output of the phase generator a pulled signal is connected to the first information input of the transmitter switch and the information input of the transmitter memory, the output of which is connected to the second information input of the transmitter switch, the output of which is connected to the second input of the phase modulator, n parallel outputs of the phase-shifted signal generator are connected respectively to n inputs of the transmitter decoder, the output of which is connected to the counting input of the counting trigger of the transmitter, the control input of which is is the control input of the transmitting part of the device, the direct output of the transmitter counting trigger is connected to the first control inputs of the address of the RAM of the transmitter, the RAM of the transmitter and the switch of the transmitter, the inverse output of the counting trigger of the transmitter is connected to the second control inputs of the address of the transmitter of the RAM of the transmitter, transmitter storage device and transmitter switch; introduced into the receiving part: the receiver switch, the receiver random access memory, the address generator of the receiver random access memory, the receiver counting trigger and the receiver decoder, the third output of the receiver synchronizer connected to the counting input of the address generator of the receiver random access memory, the output of which is connected to the address input of the random access memory receiver memory, the serial output of the reference phase-shift signal generator is connected the first information input of the receiver switch and the information input of the receiver RAM, the output of which is connected to the second information input of the receiver switch, the output of which is connected to the third input of the correlator, n parallel outputs of the reference phase generator of the manipulated signal are connected respectively to n inputs of the decoder of the receiver, the output of which is connected to the counting input of the counting trigger of the receiver, the control input of which is the control input of the receiver three, the direct output of the receiver counting trigger is connected to the first control inputs of the address of the RAM of the receiver, the RAM of the receiver and the switch of the receiver, the inverse output of the counting trigger of the receiver is connected to the second control inputs of the address of the RAM of the receiver, the RAM of the receiver and switch receiver.

Figure 2 shows the functional diagram of the proposed device, where the notation is introduced:

transmitting part:

1 - source of information;

2 - pulse-width modulator (PWM);

3 - phase modulator;

4 - balanced modulator;

5 - power amplifier;

6 - phase-manipulated (FM) signal generator (pseudo-random sequence generator);

7 - transmitter synchronizer;

8 - carrier frequency generator;

9 - transmitting antenna;

19 - transmitter switch;

20 - random access memory (RAM) of the transmitter;

21 - address generator random access memory (FA RAM) of the transmitter;

22 - transmitter counting trigger;

23 - transmitter decoder;

receiving part:

10 - receiving antenna;

11 - mixer;

12 - intermediate frequency amplifier;

13 - correlator;

14 - demodulator;

15 - recipient of information;

16 - local oscillator;

17 - generator reference phase-shift (FM) signal (reference pseudo-random sequence generator);

18 - receiver synchronizer;

24 - receiver switch;

25 - random access memory (RAM) of the receiver;

26 - address generator random access memory (FA RAM) of the receiver;

27 - receiver counting trigger;

28 - receiver decoder.

The proposed device consists of a transmitting and receiving part.

The transmitting part of the device contains a series-connected information source 1, which is the input of the device, pulse width modulator (PWM) 2, phase modulator 3, balanced modulator 4 and power amplifier 5, the output of which is connected to the transmitting antenna 9, while the second input of the balanced modulator 4 is connected to the output of the carrier frequency generator 8. The first output of the transmitter synchronizer 7 is connected to the second input of the PWM 2, and the second output of the transmitter synchronizer 7 is connected to the counting input of the operational address generator a second storage device (RAM RAM) of the transmitter 21, the output of which is connected to the address input of the random access memory (RAM) of the transmitter 20. In addition, the second output of the transmitter synchronizer 7 is connected to the input of the phase-shift (FM) generator of the signal 6, n parallel outputs of which are connected respectively with n inputs of the decoder of the transmitter 23, the output of which is connected to the counting input of the counting trigger of the transmitter 22, the control input of which is the control input of the transmitting part of the device. The serial output of the phase-manipulated (FM) signal generator 6 is connected to the first information input of the transmitter switch 19 and the information input of the transmitter RAM 20, the output of which is connected to the second information input of the transmitter 19 switch, the output of which is connected to the second input of the phase modulator 3. Direct output of the transmitter counting trigger 22 is connected to the first control inputs of the RAM of the transmitter 21, the RAM of the transmitter 20 and the switch of the transmitter 19. The inverse output of the counting trigger of the transmitter 22 is connected to about the second control inputs of the RAM of the transmitter 21, the RAM of the transmitter 20 and the switch of the transmitter 19.

The receiving part of the device contains a series-connected receiving antenna 10, a mixer 11, an intermediate frequency amplifier 12, a correlator 13, a demodulator 14, and an information receiver 15, which is the output of the device. The first output of the receiver synchronizer 18 is connected through the local oscillator 16 to the second input of the mixer 11. The second output of the receiver synchronizer 18 is connected to the second inputs of the demodulator 14 and the correlator 13, the output of which is connected to the input of the receiver synchronizer 18, the third output of which is connected to the counting input of the receiver RAM 26 the output of which is connected to the address input of the RAM of the receiver 25. In addition, the third output of the synchronizer of the receiver 18 is connected to the input of the generator of the reference FM signal 17, n parallel outputs of which are connected respectively with n inputs of the decoder of the receiver 28, the output of which is connected to the counting input of the counting trigger of the receiver 27, the control input of which is the control input of the receiving part of the device. The serial output of the reference FM signal generator 17 is connected to the first information input of the receiver switch 24 and the information input of the RAM receiver 25, the output of which is connected to the second information input of the receiver switch 24, the output of which is connected to the third input of the correlator 13. The direct output of the counting trigger of the receiver 27 is connected to the first control inputs of the FA RAM of the receiver 26, the RAM of the receiver 25 and the switch of the receiver 24. The inverse output of the counting trigger of the receiver 27 is connected to the second control inputs of the FA of the RAM p iemnika 26, the RAM 25 of the receiver 24 and the receiver switch.

The proposed device operates as follows.

From the information source 1, a telephone message arrives at the first input of the PWM 2, to the second input of which pulses are received from the first output of the synchronizer of the transmitter 7. From the output of block 2, the PWM signal goes to the first input of the phase modulator 3, to the second input of which from the output of the transmitter 19 phase-shifted broadband signal, which is an alternation of forward and reverse pseudo-random sequences (PSP). As an MSS, an M-sequence of maximum length can be used (see L. Varakin, “Communication Systems with Noise-Like Signals,” M., “P and S, 1985, p. 49).

Direct PSP is generated at the serial output of the FM signal generator 6, controlled by clock pulses supplied to its input from the second output of the transmitter synchronizer 7, and fed to the first information input of the transmitter switch 19. The reverse PSP is formed from the direct PSP by flipping, that is, that PSP element that was the first becomes the last, and that element of the PSP that was the last becomes the first. The overturn of the PSP is as follows. From the serial output of the FM signal generator 6, the SRP is fed to the information input of the RAM of the transmitter 20, which is set to record. The write or read mode of the RAM of the transmitter 20 is provided by the state of the outputs of the counting trigger of the transmitter 22, to the control input of which a signal is log. "1" from the control input of the receiving part, which allows the mode of classification, that is, alternating forward and reverse SRP, and to the counting input, the signal the output of the decoder of the transmitter 23, formed as follows.

From n parallel outputs of the FM signal generator 6, a parallel binary code of the SRP (for example, with n equal to 10 will be an M-sequence of length 1023) is supplied respectively to the n inputs of the decoder of the transmitter 23, tuned to a given number (in this case, the number 1023). At the same time, the log signal “1” will appear at the output of the transmitter decoder 23, which determines the temporary switching of the counting trigger of the transmitter 22, which has direct and inverse outputs.

If a log level signal “1” is generated at the direct output of the counting trigger of the transmitter 22, then it, having entered the first control input of the RAM of the transmitter 20, sets it to the recording mode. At the same time, at the inverse output of the counting trigger of the transmitter 22 and, therefore, at the second control input of the RAM of the transmitter 20, there will be a log level signal. "0".

In addition, the output signals of the counting trigger of the transmitter 22 control the RAM of the transmitter 21. Upon receipt of the signal level log. "1" from the direct output of the counting trigger of the transmitter 22 to the first control input of the FA of the RAM of the transmitter 21, a recording address is formed in it by adding the clock pulses, arriving at its counting input from the second output of the transmitter synchronizer 7. At the same time, at the inverse output of the counting trigger of the transmitter 22 and, therefore, at the second control input of the RAM of the transmitter 21 there will be a log level signal. "0".

If a log level signal “1” is generated at the inverted output of the counting trigger of the transmitter 22, then, having received the second control input of the RAM of the transmitter 20, it sets it to the read mode. In this case, at the direct output of the counting trigger of the transmitter 22 and, therefore, at the first control input of the RAM of the transmitter 20, there will be a log level signal. "0". Upon receipt of a signal of the level of logic "1" from the inverse output of the counting trigger of the transmitter 22 to the second control input of the RAM of the transmitter 21, a read address is formed in it by subtracting the clock pulses arriving at its counting input. The address when reading from the RAM of the transmitter 20 is set such that the information is read in the reverse order.

In addition, the signals from the direct and reverse outputs of the counting trigger of the transmitter 22 are respectively supplied to the first and second control inputs of the switch of the transmitter 19, which switches the direct memory bandwidth to its output if a log signal is applied to its first control input. "1" from the direct output of the counting the trigger of the transmitter 22, or the SRP with the reverse order of the pulses, if a signal log. "1" is supplied to its second control input from the inverse output of the counting trigger of the transmitter 22.

The FM signal from the output of the phase modulator 3, containing information, is fed to the first input of the balanced modulator 4, the second input of which receives the signal from the output of the carrier frequency generator 8. In the balanced modulator 4, the FM signal is balanced modulated with the carrier frequency. From the output of the balanced modulator 4, the FM signal is fed to the input of the power amplifier 5, where it is amplified to the required value and then transmitted through the antenna 9 into space.

The signal received by the receiving antenna 10 is fed to a mixer 11, where it is transferred using an local oscillator 16 to an intermediate frequency, amplified in an intermediate frequency amplifier 12, and fed to the first input of the correlator 13, the third input of which receives a phase-shifted broadband signal (FM ШПС) from the output of the receiver switch 24, which is an alternation of forward and reverse SRP. A direct SRP is generated at the serial output of the reference FM signal generator 17, controlled by clock pulses supplied to its input from the third output of the receiver synchronizer 18, and is fed to the first information input of the receiver switch 24. A reverse SRP is generated from the direct SRP as follows. From the serial output of the generator of the reference FM signal 17, the SRP is fed to the information input of the RAM of the receiver 25, which is set to record. The write or read mode of the RAM of the receiver 25 is provided by the state of the outputs of the counting trigger of the receiver 27, to the control input of which there is a signal log. "1" from the control input of the receiving part, which allows the mode of secretion, that is, the alternation of forward and reverse SRP, and the signal to the counting input - signal the output of the decoder of the receiver 28, formed as follows.

From n parallel outputs of the generator of the reference phase-manipulated (FM) signal 17, the parallel binary code of the SRP (as in the transmitting part, this is an M-sequence of length 1023) is supplied respectively to the n inputs of the decoder of the receiver 28, tuned to a given number (in this case, the number 1023 ) Thus at the output of the decoder of the receiver 28 will appear the signal log. "1", which determines the temporary switching of the counting trigger of the receiver 27.

If the log level signal “1” is formed at the direct output of the counting trigger of the receiver 27, then he, having entered the first control input of the RAM of the receiver 25, will set it to the recording mode. At the same time, at the inverted output of the counting trigger of the receiver 27 and, therefore, at the second control input of the RAM of the receiver 25, there will be a log level signal. "0".

In addition, the output signals of the counting trigger of the receiver 27 control the FA of the RAM of the receiver 26, the counting input of which is supplied with clock pulses from the third output of the synchronizer of the receiver 18. When a signal of level “1” is received from the direct output of the counting trigger of the receiver 27 to the first control input of the FA The RAM of the receiver 26 in it is the formation of the recording address by adding the clock pulses arriving at its counter input. At the same time, at the inverse output of the counting trigger of the receiver 27 and, therefore, at the second control input of the FA of the RAM of the receiver 26, there will be a log level signal “0”.

If at the inverted output of the counting trigger of the receiver 27 a signal of level log. "1" is generated, then he, having arrived at the second control input of the RAM of the receiver 25, sets it to read mode. At the same time, at the direct output of the counting trigger of the receiver 27 and, therefore, at the first control input of the RAM of the receiver 25, there will be a log level signal. "0". Upon receipt of a signal level of logic. "1" from the inverse output of the counting trigger of the receiver 27 to the second control input of the FA RAM of the receiver 26, a read address is formed in it by subtracting the clock pulses arriving at its counting input. The address when reading from the RAM of the receiver 25 is set such that the information is read in the reverse order.

In addition, the signals from the direct and reverse outputs of the counting trigger of the receiver 27 are respectively supplied to the first and second control inputs of the switch of the receiver 24, which switches the direct memory bandwidth to its output if a signal log. "1" is sent to its first control input from the direct output of the counting the trigger of the receiver 27, or the SRP with the reverse order of the pulses, if a signal log. "1" is supplied to its second control input from the inverse output of the counting trigger of the receiver 27.

In the correlator 13, optimal signal processing is performed, as a result of which the telephone message is generated at the output of the correlator 13 in the form of a PWM signal, which is fed to the input of the receiver synchronizer 18 and the first input of the demodulator 14, where the information component is extracted. From the output of the demodulator 14, the received telephone message is sent to the information recipient 15. The receiver synchronizer 18, controlling the local oscillator 16, searches for the FM signal in frequency and time, and then maintains synchronism in the receiving part, controlling the operation of the correlator 13 and demodulator 14. Moreover, the time search is carried out until there is a coincidence of direct and reverse SRP at the first and third inputs of the correlator 13.

As the generator of the FM signal 6 and the generator of the reference FM signal 17, the maximum length M-sequence generator performed on binary triggers shown in Fig. 3.18, page 49 can be used. books of Varakin L.E. "Communication systems with noise-like signals", M., "P and S", 1985

The address generator of the RAM of the transmitter 21 and the address generator of the RAM of the receiver 26 can be performed on the basis of a counter with addition and subtraction control (reverse counter) shown on page 249 of the book by G.I. Pukhalsky, T.Ya. Novoseltseva "Design of discrete devices on integrated circuits", M., "R and S", 1999

The implementation of the remaining blocks of the claimed device also does not cause any difficulties, since their descriptions are widely published in the technical literature.

Thus, the use of the proposed device for transmitting information alternating forward and reverse PSP has significantly improved the secrecy of the transmitted information.

Claims (1)

A radio communication line with increased secrecy of the transmitted information, containing in the transmitting part a series of information source, which is the input of the device, pulse-width modulator, phase modulator, balanced modulator and power amplifier, the output of which is connected to the transmitting antenna, and also containing a carrier frequency generator, the output of which is connected to the second input of the balanced modulator, and a transmitter synchronizer, the first output of which is connected to the second input of the pulse-width modulator a, and the second output of the transmitter synchronizer is connected to the input of the phase-manipulated signal generator, in the receiving part: a receiving antenna, a mixer, an intermediate frequency amplifier, a correlator, a demodulator and an information receiver, which is the output of the device, and also containing a receiver synchronizer, the first output of which is connected in series through a local oscillator connected to the second input of the mixer, the second output of the receiver synchronizer is connected to the second inputs of the demodulator and the correlator, the output of which is connected with the input of the receiver synchronizer, the third output of which is connected to the input of the reference phase-manipulated signal generator, characterized in that the transmitter’s RAM, the transmitter’s random access memory, the transmitter’s memory address generator, the transmitter’s counting trigger, and the transmitter decoder are inserted into the transmitter the synchronizer of the transmitter is connected to the counting input of the address generator of the memory of the transmitter, the output of which is connected to the address input of the transmitter memory, the serial output of the phase-shift signal generator is connected to the first information input of the transmitter switch and the information input of the transmitter memory, the output of which is connected to the second information input of the transmitter switch, the output of which is connected to the second input of the phase modulator, n the parallel outputs of the phase-shift signal generator are connected respectively to n inputs transmitter encoder, the output of which is connected to the counting input of the transmitter counting trigger, the control input of which is the control input of the transmitting part of the device, the direct output of the transmitter counting trigger is connected to the first control inputs of the transmitter address of the RAM of the transmitter, the RAM of the transmitter and the transmitter switch, inverse output counting trigger of the transmitter is connected to the second control inputs of the address shaper operatively of the transmitter’s storage device, the transmitter’s RAM and the transmitter’s switch, the receiver’s switch, the receiver’s RAM, the address of the receiver’s RAM, the receiver’s counting trigger and the receiver decoder are inserted into the receiver, the third output of the receiver synchronizer is connected to the counting input of the address generator random access memory of the receiver, the output of which is connected to the address input of the operational the receiver’s memory device, the serial output of the reference phase-manipulated signal generator is connected to the first information input of the receiver switch and the information input of the receiver memory, the output of which is connected to the second information input of the receiver switch, the output of which is connected to the third input of the correlator, n parallel outputs of the reference phase generator of the manipulated signal connected respectively to the n inputs of the decoder of the receiver, the output of which is connected with the counting input of the receiver counting trigger, the control input of which is the control input of the receiving part of the device, the direct output of the receiver counting trigger is connected to the first control inputs of the address of the receiver random access memory, the receiver random access memory and the receiver switch, the inverse output of the receiver counting trigger is connected to the second control inputs of the address generator of the random access memory of the receiver, the operational memory its receiver device and a receiver switch.

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