CN211930610U - Power-on reset circuit - Google Patents
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- CN211930610U CN211930610U CN202020149940.8U CN202020149940U CN211930610U CN 211930610 U CN211930610 U CN 211930610U CN 202020149940 U CN202020149940 U CN 202020149940U CN 211930610 U CN211930610 U CN 211930610U
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Abstract
The application discloses power-on reset circuit, it includes: the reset signal generating circuit is used for receiving a voltage signal of an external power supply and outputting a first reset signal; the delay circuit is connected with the reset signal generating circuit and is used for receiving a first reset signal and outputting a second reset signal to the first reset signal in a delayed mode, wherein the delay circuit comprises an oscillator circuit and a narrow pulse generating circuit, and the oscillator circuit generates a clock signal according to the first reset signal; the narrow pulse generating circuit is used for generating a second reset signal according to a clock signal and the first reset signal. The delay of the reset signal is realized by adding the delay circuit, so that the error reset caused by the power burr is avoided, and the normal work of the circuit is further ensured.
Description
Technical Field
The utility model relates to an integrated circuit field specifically, relates to power-on reset circuit.
Background
The geomagnetic field is used as an important resource of the earth, and has important application in the aspects of aerospace, traffic communication, national defense construction, earthquake prediction and the like. Based on the important value of the geomagnetic field, magnetic sensors are widely used as sensor elements for measuring the magnitude of the magnetic field, and anisotropic magnetoresistive sensors are most popular in practical applications due to the advantages of high sensitivity, high reliability, good linearity, low power consumption, easiness in miniaturization and the like. The resistance value of anisotropic magnetic resistance in the anisotropic magnetic resistance sensor can change under magnetic fields in different directions, a Wheatstone bridge formed by the anisotropic magnetic resistance can convert the resistance value change of the magnetic resistance into voltage change, and then the magnetic field size is calculated by measuring voltage difference. In order to make the magnetoresistance have high sensitivity, it is necessary to align the inside of the anisotropic magnetoresistance by a SET/RESET (SET/RESET) circuit at the time of test.
The reset circuit, as the name implies, is a circuit that restores the circuit to an initial state. Generally, the means by which different reset circuits are activated varies. Firstly, when the circuit is electrified, the reset operation is immediately carried out; secondly, the operation can be manually operated when necessary. A Reset circuit that performs a Reset operation immediately when the circuit is powered On is called a POR (Power On Reset) circuit, and has been widely integrated into an SOC chip. In the initial stage of power-up of a circuit system, the power supply voltage has not reached a stable expected state, and the node voltage and logic state of the circuit are unstable, which may cause the system to operate incorrectly. In order to start the system from a predetermined initial state, it is necessary to initialize the system by generating a reset signal at the initial stage of power-on using a power-on reset circuit. In general, a power-on reset circuit is required to output a valid signal after a certain delay time after a power supply voltage exceeds a detection threshold value, so as to ensure that the circuit operates under a stable power supply voltage condition.
With the continuous reduction of the process size of integrated circuits, more circuits can be integrated in the chip, but the integrated circuit designers are still required to reduce the chip area as much as possible under the premise of realizing the circuit function, because the increase of the chip area means more tape-out cost. However, implementing delay detection in the power-on reset circuit faces the problem that implementing a large delay consumes an excessive chip area.
In addition, because the resistance value of the anisotropic magnetic resistance is small, the current flowing through the magnetic resistance is large, and the power supply voltage generates large burrs when setting/resetting is carried out, so that a power-on reset signal is influenced, and the power supply is reset when the triggering condition of the power-on reset circuit is not met.
Disclosure of Invention
In view of the above, the present invention is directed to a power-on reset circuit, which realizes the delay of a reset signal through a delay circuit when detecting a power failure, and avoids a false reset caused by a power glitch.
According to the utility model discloses an aspect provides a power-on reset circuit, include: the reset signal generating circuit receives a voltage signal of an external power supply and outputs a first reset signal; the time delay circuit is connected with the reset signal generating circuit, receives the first reset signal, delays the first reset signal and outputs a second reset signal; wherein the delay circuit includes an oscillator circuit and a narrow pulse generation circuit, wherein the oscillator circuit generates a clock signal according to the first reset signal; the narrow pulse generating circuit is used for generating a second reset signal according to a clock signal and the first reset signal; when the low level maintaining time of the first reset signal is less than the preset time, the second reset signal is invalid; and when the low level maintaining time of the first reset signal is not less than the preset time, the second reset signal is effective.
Preferably, the narrow pulse generating circuit includes: a frequency divider circuit for dividing the clock signal by 2nDividing frequency and outputting a frequency division signal, wherein n is a positive integer; a flip-flop receiving a first reset signal POR0, the frequency-divided signal, and the voltage signal, and outputting a second reset signal according to the first reset signal, the frequency-divided signal, and the voltage signal; wherein when the first reset signal is at a low level, the second reset signal is inactive when the divided signal does not have a rising edge; the second reset signal is active when a rising edge of the divided signal occurs.
Preferably, the period of the frequency-divided signal is 2 of the period of the clock signalnN is more than or equal to 4 and less than or equal to 8.
Preferably, the preset time is a period of the frequency-divided signal.
Preferably, the reset signal generating circuit includes: the first current mirror unit receives the voltage signal and generates a first bias current; the second current mirror unit receives the voltage signal, is connected with the first current mirror unit and generates a second bias current according to the first bias current; the power-on circuit unit is connected with the first current mirror unit and the second current mirror unit and generates a voltage turnover signal according to the first bias current and the second bias current; the output control unit is connected with the second current mirror unit and the power-on circuit unit and used for generating a first reset signal and a feedback control signal according to a second bias current and a voltage turnover signal; and the feedback control unit is connected with the first current mirror unit, the output control unit and the power-on circuit unit, and is used for generating a feedback signal according to the first bias current and the feedback control signal and feeding the feedback signal back to the power-on circuit unit.
Preferably, the first current mirror unit includes a first transistor and tenth to thirteenth transistors, wherein a gate of the first transistor is connected to a ground terminal, a drain thereof is connected to a drain of the tenth transistor, a source thereof receiving the voltage signal, a gate of the tenth transistor being connected to a drain thereof, a source thereof is connected to a ground terminal, a gate of the eleventh transistor is connected to a gate of the tenth transistor, a source thereof is connected to a ground terminal, a drain thereof is connected to the second current mirror unit, a gate of the twelfth transistor is connected to a gate of the eleventh transistor, a source thereof is connected to a ground terminal, a drain thereof is connected to the power-on circuit unit, a gate of the thirteenth transistor is connected to a gate of the eleventh transistor, the source electrode of the feedback control unit is connected with the grounding end, and the drain electrode of the feedback control unit is connected with the output control unit.
Preferably, the first transistor is a P-type transistor, and the tenth to thirteenth transistors are N-type transistors.
Preferably, the second current mirror unit includes a second transistor, a fourth transistor, and a seventh transistor, wherein a gate of the second transistor is connected to a drain thereof, a source thereof receives the voltage signal, a gate of the fourth transistor is connected to a gate of the second transistor, a source thereof receives the voltage signal, a drain thereof is connected to the power-on circuit unit, a gate of the seventh transistor is connected to a gate of the fourth transistor, a source thereof receives the voltage signal, and a drain thereof is connected to the output control unit.
Preferably, the second transistor, the fourth transistor, and the seventh transistor are P-type transistors.
Preferably, the power-on circuit unit includes a third transistor, a fifth transistor, a sixth transistor and a first capacitor, wherein a gate of the third transistor is connected to a drain thereof, a drain thereof is simultaneously connected to a ground terminal, and a source thereof is connected to the second current mirror unit; the gate of the fifth transistor is connected to the drain of the fifth transistor, the drain of the fifth transistor is connected to the first current mirror unit, and the source of the fifth transistor is connected to the source of the third transistor; the grid electrode of the sixth transistor is connected with the grid electrode of the fifth transistor, the drain electrode of the sixth transistor is connected with the first current mirror unit and the output control unit, and the source electrode of the sixth transistor is connected with the drain electrode of the eighth transistor; the first capacitor is connected between the gate of the fifth transistor and a ground terminal.
Preferably, the third transistor, the fifth transistor and the sixth transistor are P-type transistors.
Preferably, the output control unit includes a fourteenth transistor, a second capacitor, and first to third inverters, wherein an input terminal of the first inverter is connected to the first current mirror unit and the power-on circuit unit; a gate of the fourteenth transistor is connected to the output terminal of the first inverter, a source thereof is connected to a ground terminal, and a drain thereof is connected to the input terminal of the second inverter and the second current mirror unit; the second capacitor is connected between the input end of the second inverter and the ground end, the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter outputs the first reset signal; and the output end of the second inverter outputs the feedback control signal.
Preferably, the fourteenth transistor is an N-type transistor.
Preferably, the feedback control unit includes an eighth transistor, a ninth transistor and a fifteenth transistor, wherein a gate of the eighth transistor and a gate of the ninth transistor are commonly connected to a ground terminal, a drain thereof is connected to a source of the ninth transistor, and a source thereof receives the voltage signal; the drain of the ninth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor is connected to the output control unit, and the source of the fifteenth transistor is connected to a ground terminal.
Preferably, the eighth transistor and the ninth transistor are P-type transistors, and the fifteenth transistor is an N-type transistor.
Preferably, the oscillator circuit comprises: a feedback signal generating unit which generates a feedback signal according to the clock signal; and the clock signal generating unit receives the first reset signal and the feedback signal and generates a clock signal according to the first reset signal and the feedback signal.
Preferably, the clock signal generating unit includes a fourth inverter, a fifth inverter, a sixth inverter, a nand gate, and a third capacitor, an input end of the fourth inverter receives the first reset signal, and an output end of the fourth inverter is connected to the first input end of the nand gate; the input end of the fifth inverter receives the feedback signal, and the output end of the fifth inverter is connected with the input end of the sixth inverter; the output end of the sixth inverter is connected with the second input end of the NAND gate; the third capacitor is connected between the input end of the fifth inverter and the output end of the sixth inverter; and the output end of the NAND gate outputs the clock signal.
Preferably, the feedback signal generating unit includes a first resistor, a second resistor, a fourth capacitor and a fifth capacitor, where the first resistor and the second resistor are connected in series between one end of the clock signal generating unit receiving the feedback signal and one end of the clock signal generating unit outputting the clock signal; the fourth capacitor is connected between one end of the clock signal generating unit for receiving the feedback signal and a ground terminal, and the fifth capacitor is connected between a connection node of the first resistor and the second resistor and the ground terminal.
Preferably, the power-on reset circuit is connected with the magnetoresistive sensor, so as to ensure effective time delay of the magnetoresistive sensor.
Preferably, the power-on-reset circuit is for a magnetometer.
The utility model provides a power-on reset circuit realizes reset signal's time delay through increasing delay circuit, avoids resetting because the mistake that great power burr caused, and then ensures that the circuit normally works. And simultaneously, the utility model discloses do not adopt traditional RC filtering structure to carry out the time delay to reset signal, but through producing clock signal to first reset signal after oscillator circuit handles, later carry out the frequency division to clock signal and produce the second reset signal, so the chip area that the delay circuit of this application occupy is less, reduces the cost of product, improves the competitiveness of product.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a power-on reset circuit according to an embodiment of the present invention.
Fig. 2 shows a block diagram of a reset signal generating circuit according to an embodiment of the present invention.
Fig. 3 shows a circuit diagram of the reset signal generating circuit in fig. 2.
Fig. 4 shows a block diagram of an oscillator circuit according to an embodiment of the present invention.
Fig. 5 shows a circuit diagram of the oscillator circuit of fig. 4.
Fig. 6 shows a circuit diagram of a narrow pulse generating circuit according to an embodiment of the present invention.
Fig. 7 shows a signal waveform diagram of a power-on reset circuit according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
Fig. 1 shows a schematic block diagram of a power-on reset circuit according to an embodiment of the present invention.
As shown in fig. 1, the power-on reset circuit includes a reset signal generating circuit 100 and a delay circuit 200, wherein the reset signal generating circuit 100 is configured to receive a voltage signal Vdd of an external power source and output a first reset signal POR0, the delay circuit 200 is connected to the reset signal generating circuit 100, and is configured to receive the first reset signal POR0 and delay and output a second reset signal POR to the first reset signal POR0, the delay circuit 200 includes an oscillator circuit 201 and a narrow pulse generating circuit 202, the oscillator circuit 201 generates a clock signal CLK according to the first reset signal POR0, and the narrow pulse generating circuit 202 is configured to generate the second reset signal POR according to the clock signal CLK and the first reset signal POR 0.
In the present embodiment, during power-on, the output voltage of the output terminal of the reset signal generating circuit 100 varies with the voltage signal Vdd of the external power supply. When the power voltage rises to a certain voltage, the output voltage value at the output terminal of the reset signal generating circuit 100 jumps to Vdd, and the first reset signal POR0 is a high level signal. When the Power supply is powered on and detects a Power failure (Power failure), the output voltage value of the output terminal of the reset signal generating circuit 100 jumps to 0, and at this time, the first reset signal POR0 is a low level signal and is maintained for a certain time.
Fig. 2 shows a block diagram of a reset signal generating circuit according to an embodiment of the present invention, and fig. 3 shows a circuit diagram of the reset signal generating circuit in fig. 2.
As shown in fig. 2 and 3, the reset signal generating circuit 100 includes: a first current mirror unit 101, a second current mirror unit 102, an output control unit 104 and a feedback control unit 105, and a power-on circuit unit 103.
The first current mirror unit 101 is configured to generate a first bias current.
In the present embodiment, the first current mirror unit 101 includes a first transistor M1, tenth to thirteenth transistors M10-M13, wherein the gate of the first transistor M1 is connected to the ground GND, the drain is connected to the drain of the tenth transistor M10, a source of the tenth transistor M10 receives the voltage signal Vdd, a gate of the tenth transistor M10 is connected to a drain thereof, a source thereof is connected to a ground terminal GND, a gate of the eleventh transistor M11 is connected to a gate of the tenth transistor M10, a source thereof is connected to the ground terminal GND, a drain thereof is connected to the second current mirror unit 102, a gate of the twelfth transistor M12 is connected to a gate of the eleventh transistor M11, a source thereof is connected to the ground terminal GND, the drain thereof is connected to the power-on circuit unit 103, the gate of the thirteenth transistor M13 is connected to the gate of the eleventh transistor M11, the source thereof is connected to the ground GND, and the drain thereof is connected to the feedback control unit 105 and the output control unit 104.
And a second current mirror unit 102 connected to the first current mirror unit 101 for generating a second bias current according to the first bias current.
In the present embodiment, the second current mirror unit 102 includes a second transistor M2, a fourth transistor M4, and a seventh transistor M7, wherein the gate of the second transistor M2 is connected to its own drain, its source receives the voltage signal Vdd, and its drain is connected to the first current mirror unit 101; the gate of the fourth transistor M4 is connected to the gate of the second transistor M2, the source thereof receives the voltage signal Vdd, and the drain thereof is connected to the power-on circuit unit 103; the gate of the seventh transistor M7 is connected to the gate of the fourth transistor M4, the source thereof receives the voltage signal Vdd, and the drain thereof is connected to the output control unit 104.
And a power-on circuit unit 103 connected to the first current mirror unit 101 and the second current mirror unit 102, and configured to generate a voltage flipping signal according to the first bias current and the second bias current.
In the embodiment, the power-on circuit unit 103 includes a third transistor M3, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1, wherein the gate of the third transistor M3 is connected to its drain, the drain is connected to the ground GND, and the source is connected to the drain of the fourth transistor M4 in the second current mirror unit 102; the gate of the fifth transistor M5 is connected to its own drain, the drain is connected to the drain of the twelfth transistor M12 in the first current mirror cell 101, and the source is connected to the source of the third transistor M3; the gate of the sixth transistor is connected to the gate of the fifth transistor, the drain of the sixth transistor is connected to the first current mirror unit and the output control unit, and the source of the sixth transistor is connected to the feedback control unit 105; the first capacitor C1 is connected between the gate of the fifth transistor M5 and the ground GND.
And the output control unit 104 is connected with the second current mirror unit 102 and the power-on circuit unit 103, and is used for generating a first reset signal and a feedback control signal according to the second bias current and the voltage reversal signal.
In the present embodiment, the output control unit 104 includes a fourteenth transistor M14, a second capacitor C2, and first to third inverters U1 to U3, wherein an input terminal of the first inverter U1 is connected to the first current mirror unit 101 and the power-on circuit unit 103; a gate of the fourteenth transistor M14 is connected to the output terminal of the first inverter U1, a source thereof is connected to the ground terminal GND, and a drain thereof is connected to the input terminal of the second inverter U2 and the second current mirror unit 102; the second capacitor C2 is connected between the input terminal of the second inverter U2 and the ground terminal GND, the input terminal of the third inverter U3 is connected to the output terminal of the second inverter U2, the output terminal thereof outputs the first reset signal POR0, and the output terminal of the second inverter U2 outputs the feedback control signal.
And a feedback control unit 105, connected to the first current mirror unit 101, the output control unit 104 and the power-on circuit unit 103, for generating a feedback signal according to the first bias current and the feedback control signal, and feeding the feedback signal back to the power-on circuit unit 103.
In the present embodiment, the feedback control unit 105 includes an eighth transistor M8, a ninth transistor M9, and a fifteenth transistor M15, wherein the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are commonly connected to the ground GND, the drain thereof is connected to the source of the ninth transistor M9, and the source thereof receives the voltage signal Vdd; the gate of the fifteenth transistor M15 is connected to the output control unit 104, the source thereof is connected to the ground GND, and the drain thereof is connected to the drain of the ninth transistor M9.
Specifically, the drain of the eleventh transistor M11 is connected to the drain of the second transistor M2; the source of the third transistor M3 is connected to the drain of the fourth transistor M4; the drain of the fifth transistor M5 is connected to the drain of the twelfth transistor M12; the drain of the sixth transistor M6 is connected to the drain of the thirteenth transistor M13 and the input terminal of the first inverter U1, the source thereof is connected to the drain of the eighth transistor M8, and the connection point of the sixth transistor M6 and the thirteenth transistor M13 outputs the voltage reversal signal; a drain of the fourteenth transistor M14 is connected to a drain of the seventh transistor M7; an input end of the first inverter U1 is connected to a drain of the thirteenth transistor and a drain of the sixth transistor; a gate of the fifteenth transistor M15 is connected to the output terminal of the second inverter U2.
A connection point between the gate of the fifth transistor M5 and the gate of the sixth transistor M6 is a first node a, a connection point between the drain of the sixth transistor M6 and the drains of the thirteenth transistor M13 and the input terminal of the first inverter U1 is a node B, the output terminal of the first inverter U1 is a node C, a connection point between the drain of the seventh transistor M7 and the drains of the fourteenth transistor M14 and the input terminal of the second inverter U2 is a node D, a connection point between the output terminal of the second inverter U2 and the gate of the fifteenth transistor M15 is a node E, and a connection point between the drain of the eighth transistor M8 and the source of the ninth transistor M9 is a node F.
Further, the first to ninth transistors M1-M9 are P-type field effect transistors, and the tenth to fifteenth transistors M10-M15 are N-type field effect transistors.
The voltage signal Vdd starts to rise from 0, and all transistors are turned off at first; when the power supply voltage Vdd rises to a certain value, all transistors are turned on. The gate voltage of the first transistor M1 is 0, the first transistor M1 operates in a saturation region, the tenth transistor M10 and the eleventh, twelfth and thirteenth transistors M11, M12 and M13 constitute the first current mirror unit 101, the tenth transistor M10 supplies bias voltages to the eleventh, twelfth and thirteenth transistors M11, M12 and M13, and the eleventh, twelfth and thirteenth transistors M11, M12 and M13M13 was all operating in the saturation region. Similarly, the second transistor M2, the fourth transistor M4, and the seventh transistor M7 form the second current mirror unit 102, and the fourth transistor M4 and the seventh transistor M7 both operate in the saturation region. The third transistor M3 is equivalent to a diode and acts as a voltage clamp to ensure that the node A is at a low level, so that the sixth transistor M6 is turned on, and the voltage at the node B is pulled high, VB＝VFThe voltage V at the node C via the first inverter U1CPulled low, the fourteenth transistor M14 is turned off, and the current of the seventh transistor M7 flows into the second capacitor C2, and the voltage V at the node DDSlowly increasing. Voltage V of initial node DDIs low, the first reset signal POR0 is low, and the voltage V at the node EEAt Vdd, the sixth transistor M6 is turned on and the voltage V at node FFVdd/2. When the voltage V of the node DDWhen the output voltage of the output end of the third inverter U3 reaches a certain value, the output voltage is inverted from 0 to Vdd, and the voltage V of the node E at the momentE0, the fifteenth transistor M15 is turned off, the voltage V at the node FF＝Vdd。
Fig. 4 shows a block diagram of an oscillator circuit according to an embodiment of the present invention, and fig. 5 shows a circuit diagram of the oscillator circuit in fig. 4. As shown in fig. 4 and 5, the delay circuit 200 includes an oscillator circuit 201 and a narrow pulse generating circuit 202, wherein the oscillator circuit 201 generates the clock signal CLK according to the first reset signal POR 0.
In the present embodiment, the oscillator circuit 201 includes a clock signal generating unit 2011 and a feedback signal generating unit 2012, wherein the clock signal generating unit 2011 includes a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a nand gate U7 and a third capacitor C3, the feedback signal generating unit 2012 includes a first resistor R1 and a second resistor R3 connected in series between an input terminal of the fifth inverter U5 and an output terminal of the nand gate U7, and a fourth capacitor C4 and a fifth capacitor C5.
Specifically, the input end of the fourth inverter U4 receives a first reset signal POR0, and the output end of the fourth inverter U4 is connected to the first input end X1 of the nand gate U7; the input end of the fifth inverter U5 is connected to the ground GND via a fourth capacitor C4, and is connected to the ground GND via a first resistor R1 and a fifth capacitor C5, and is connected to the output end of the nand gate U7 via a first resistor R1 and a second resistor R2, and the output end of the fifth inverter U5 is connected to the input end of the sixth inverter U6; the output end of the sixth inverter U6 is connected to the second input end X2 of the NAND gate U7, and the output end thereof is simultaneously connected to the input end of the fifth inverter U5 through the third capacitor C3; the nand gate U7 has a first input terminal X1 connected to the output terminal of the fourth inverter U4, a second input terminal X2 connected to the output terminal of the sixth inverter U6, and an output terminal outputting the clock signal CLK.
When the power-down is detected when the power supply is powered on, the first reset signal POR0 is at low level, and the NAND gate
The signal at the first input terminal X1 of the U7 is at a high level, the clock signal CLK is X2, and the clock signal CLK is fed back to the second input terminal X2 of the nand gate U7 through two stages of series-connected RC circuits (i.e., an RC circuit formed by R2 and C5 and an RC circuit formed by R1 and C4), so as to implement a ring oscillator circuit. When the power-on reset circuit normally operates, the first reset signal POR0 is at a high level, the signal at the first input terminal X1 of the nand gate U7 is at a low level, the clock signal CLK is equal to X2 equal to 1, and the clock signal CLK is at a high level.
In the present embodiment, the narrow pulse generating circuit 202 is used for generating the second reset signal POR according to the clock signal CLK and the first reset signal POR 0. Fig. 6 shows a circuit diagram of a narrow pulse generating circuit according to an embodiment of the present invention. As shown in fig. 6, the narrow pulse generating circuit 202 includes a frequency dividing circuit 2021 and a flip-flop 2022, wherein the frequency dividing circuit 2021 is used for dividing the clock signal CLK by 2nAnd frequency division is carried out, and a frequency division signal is output. The flip-flop 2022 receives the first reset signal POR0, the frequency-divided signal, and the voltage signal Vdd, and outputs a second reset signal POR according to the first reset signal POR0, the frequency-divided signal, and the voltage signal Vdd. Wherein when the first reset signal POR0 is in an active state, the voltage signal Vdd is taken as the second reset signal POR when no rising edge of the frequency-divided signal occurs; outputting the voltage signal Vdd reversely when the frequency-divided signal has a rising edgeIs the second reset signal POR.
The frequency division circuit 2021 is composed of n D flip-flops D1-Dn for realizing frequency division, and Q1-Qn are frequency division signals output by the D flip-flops D1-Dn respectively. The clock signal CLK has a period T, and the frequency divider circuit 2021 divides the CLK signal by 2, 4, … …, 2nDividing frequency, where n is more than or equal to 4 and less than or equal to 8, and then taking 2nThe frequency-divided output is used as a frequency-divided signal having a period of 2 times the period of the clock signalnMultiplication, i.e. the period of the divided signal being 2nT; and then triggers the output of the frequency-divided signal when the first reset signal POR0 is at a low level, so as to realize the time delay. At this time, the second reset signal POR is delayed with respect to the first reset signal POR0 by a delay time of 2nT, as shown in fig. 7. In fig. 7, for example, if n is 5, Q1 is the frequency-divided signal output by the 1 st D flip-flop D1 in the frequency-dividing circuit 2021; q2 is the frequency-divided signal output by the 2 nd D flip-flop D2 in the frequency-dividing circuit 2021; q3 is the frequency-divided signal output by the 3 rd D flip-flop D3 in the frequency-dividing circuit 2021; q4 is the frequency-divided signal output by the 4 th D flip-flop D4 in the frequency-dividing circuit 2021; q5 is the frequency-divided signal output by the 5 th D flip-flop D5 in the frequency-dividing circuit 2021. The values of n are different, the periods of the frequency division signals are different, the larger the value is, the larger the period is, and the longer the delay time of the second reset signal POR is. Preferably, the power-on reset circuit is connected with a magnetoresistive sensor (such as an anisotropic magnetoresistive sensor), and n is more than or equal to 4 and less than or equal to 8, so that the effective time delay of the anisotropic magnetoresistive sensor can be ensured. As shown in fig. 7, when the frequency-divided signal Q5 does not have a rising edge while the first reset signal POR0 is at a low level (Tpor1 period), the flip-flop 2022 is not triggered, and the level of the second reset signal POR output therefrom remains unchanged, i.e., remains at a high level, at which the second reset signal POR is disabled. During the period when the first reset signal POR0 is at the low level (during Topr 2), when the divided-frequency signal Q5 has a rising edge, the flip-flop 2022 is triggered, and the level of the second reset signal POR output by the flip-flop has a falling edge, i.e., the second reset signal POR changes from the high level to the low level, at which time the second reset signal POR is active.
The functional relationship between the area of the delay circuit and the delay time can be expressed as A1＝α1· log2(D1+0.5)+1+α2(ii) a Wherein A is1Is the area of the layout, D, required by the delay circuit1Is the delay time, alpha, produced by the delay circuit1And alpha2Is to determine the parameter of the delay unit circuit depending on the process variation. The RC method adopted by the traditional delay circuit can be expressed as A according to the functional relation between the area and the delay time2＝1.32(β1·β2/γ·D2)1/2Wherein A is2Is the area of the layout, D, required by the RC method2Is the delay time, gamma, beta, produced by the RC method1，β2Is a parameter depending on process variation under the determination of the delay cell circuit. In terms of formula, the area required by the delay circuit provided by the embodiment is a base-2 logarithmic function, and the traditional delay circuit is a square root function. The area required by the delay circuit provided by the embodiment is insensitive to delay time variation; while the area required for the RC method is a linear function of the square root of the implemented delay time. When D is present1＝D2When, A1＜A2. Therefore, when a large delay variation is to be realized, the area required by the delay circuit provided by the embodiment is much smaller than that required by the RC method.
Further, when the low level of the first reset signal POR0 maintains the time Tpor less than the period 2 of the frequency-divided signalnT, the second reset signal POR is inactive. When the low level of the first reset signal is maintained for a time Tpor not less than the period 2 of the frequency division signalnTime T, the second reset signal POR is delayed by 2nEffective after T.
As shown in FIG. 7, for the power glitch1 (i.e., power glitch1), the low level of the first reset signal POR0 has a retention time Tpor1, since Tpor1 < 2nT, the second reset signal POR generated by the delay circuit 202 is inactive, i.e., not reset. For power glitch2 (i.e., power glitch2), the low level of the first reset signal POR0 has a retention time Tpor2, since Tpor2 is greater than or equal to 2nT, the second reset signal POR generated by the delay circuit 202 is delayed by 2nActive after T, i.e. second reset signal POR delayed by 2nAnd resetting after T. The utility model provides a power-on reset circuit realizes reset signal's time delay through increasing delay circuit, avoids resetting because the mistake that great power burr caused, and then ensures that the circuit normally works. Meanwhile, the time delay circuit occupies a small chip area, reduces the cost of the product and improves the competitiveness of the product.
Embodiments of the invention are described above, and these embodiments do not set forth any exhaustive details or limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The protection scope of the present invention should be subject to the scope defined by the claims of the present invention.
Claims (20)
1. A power-on-reset circuit, comprising:
the reset signal generating circuit receives a voltage signal of an external power supply and outputs a first reset signal;
the time delay circuit is connected with the reset signal generating circuit, receives the first reset signal, delays the first reset signal and outputs a second reset signal;
wherein the delay circuit includes an oscillator circuit and a narrow pulse generation circuit, wherein the oscillator circuit generates a clock signal according to the first reset signal; the narrow pulse generating circuit is used for generating a second reset signal according to a clock signal and the first reset signal;
when the low level maintaining time of the first reset signal is less than the preset time, the second reset signal is invalid; and when the low level maintaining time of the first reset signal is not less than the preset time, the second reset signal is effective.
2. The power-on-reset circuit of claim 1, wherein the narrow pulse generation circuit comprises:
a frequency divider circuit for dividing the clock signal by 2nDividing frequency and outputting a frequency division signal, wherein n is a positive integer;
a flip-flop receiving a first reset signal POR0, the frequency-divided signal, and the voltage signal, and outputting a second reset signal according to the first reset signal, the frequency-divided signal, and the voltage signal;
wherein when the first reset signal is at a low level, the second reset signal is inactive when the divided signal does not have a rising edge; the second reset signal is active when a rising edge of the divided signal occurs.
3. The power-on-reset circuit of claim 2, wherein the period of the frequency-divided signal is 2 of the period of the clock signalnN is more than or equal to 4 and less than or equal to 8.
4. The power-on-reset circuit of claim 3, wherein the preset time is a period of the frequency-divided signal.
5. The power-on-reset circuit of claim 1, wherein the reset signal generation circuit comprises:
the first current mirror unit receives the voltage signal and generates a first bias current;
the second current mirror unit receives the voltage signal, is connected with the first current mirror unit and generates a second bias current according to the first bias current;
the power-on circuit unit is connected with the first current mirror unit and the second current mirror unit and generates a voltage turnover signal according to the first bias current and the second bias current;
the output control unit is connected with the second current mirror unit and the power-on circuit unit and used for generating a first reset signal and a feedback control signal according to a second bias current and a voltage turnover signal;
and the feedback control unit is connected with the first current mirror unit, the output control unit and the power-on circuit unit, and is used for generating a feedback signal according to the first bias current and the feedback control signal and feeding the feedback signal back to the power-on circuit unit.
6. The power-on-reset circuit of claim 5, wherein the first current mirror unit comprises a first transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor,
the gate of the first transistor is connected to a ground terminal, the drain of the first transistor is connected to the drain of the tenth transistor, the source of the tenth transistor receives the voltage signal, the gate of the tenth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the ground terminal, the gate of the eleventh transistor is connected to the gate of the tenth transistor, the source of the eleventh transistor is connected to the ground terminal, the drain of the eleventh transistor is connected to the second current mirror unit, the gate of the twelfth transistor is connected to the gate of the eleventh transistor, the source of the twelfth transistor is connected to the ground terminal, the drain of the twelfth transistor is connected to the power-on circuit unit, the gate of the thirteenth transistor is connected to the gate of the eleventh transistor, the source of the thirteenth transistor is connected to the ground terminal, and the drain of the thirteenth transistor is.
7. The power-on-reset circuit according to claim 6, wherein the first transistor is a P-type transistor, and the tenth to thirteenth transistors are N-type transistors.
8. The power-on-reset circuit of claim 5, wherein the second current mirror unit comprises a second transistor, a fourth transistor, and a seventh transistor,
the grid electrode of the second transistor is connected with the drain electrode of the second transistor, the source electrode of the second transistor receives the voltage signal, the grid electrode of the fourth transistor is connected with the grid electrode of the second transistor, the source electrode of the fourth transistor receives the voltage signal, the drain electrode of the fourth transistor is connected with the power-on circuit unit, the grid electrode of the seventh transistor is connected with the grid electrode of the fourth transistor, the source electrode of the seventh transistor receives the voltage signal, and the drain electrode of the seventh transistor is connected with the output control unit.
9. The power-on-reset circuit of claim 8, wherein the second, fourth, and seventh transistors are P-type transistors.
10. The power-on-reset circuit according to claim 5, wherein the power-on circuit unit includes a third transistor, a fifth transistor, a sixth transistor, and a first capacitor,
the grid electrode of the third transistor is connected with the drain electrode of the third transistor, the drain electrode of the third transistor is simultaneously connected with a grounding end, and the source electrode of the third transistor is connected with the second current mirror unit;
the gate of the fifth transistor is connected to the drain of the fifth transistor, the drain of the fifth transistor is connected to the first current mirror unit, and the source of the fifth transistor is connected to the source of the third transistor;
the grid electrode of the sixth transistor is connected with the grid electrode of the fifth transistor, the drain electrode of the sixth transistor is connected with the first current mirror unit and the output control unit, and the source electrode of the sixth transistor is connected with the feedback control unit;
the first capacitor is connected between the gate of the fifth transistor and a ground terminal.
11. The power-on reset circuit according to claim 10, wherein the third transistor, the fifth transistor and the sixth transistor are P-type transistors.
12. The power-on-reset circuit according to claim 5, wherein the output control unit includes a fourteenth transistor, a second capacitor, and first to third inverters,
the input end of the first inverter is connected with the first current mirror unit and the power-on circuit unit;
a gate of the fourteenth transistor is connected to the output terminal of the first inverter, a source thereof is connected to a ground terminal, and a drain thereof is connected to the input terminal of the second inverter and the second current mirror unit;
the second capacitor is connected between the input end of the second inverter and the ground terminal,
the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter outputs the first reset signal;
and the output end of the second inverter outputs the feedback control signal.
13. The power-on-reset circuit of claim 12, wherein the fourteenth transistor is an N-type transistor.
14. The power-on-reset circuit according to claim 5, wherein the feedback control unit includes an eighth transistor, a ninth transistor, and a fifteenth transistor,
the gate of the eighth transistor and the gate of the ninth transistor are commonly connected to a ground terminal, the drain of the eighth transistor is connected to the source of the ninth transistor, and the source of the eighth transistor receives the voltage signal;
the drain of the ninth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor is connected to the output control unit, and the source of the fifteenth transistor is connected to a ground terminal.
15. The power-on-reset circuit of claim 14, wherein the eighth and ninth transistors are P-type transistors and the fifteenth transistor is an N-type transistor.
16. The power-on-reset circuit of claim 1, wherein the oscillator circuit comprises:
a feedback signal generating unit which generates a feedback signal according to the clock signal;
and the clock signal generating unit receives the first reset signal and the feedback signal and generates a clock signal according to the first reset signal and the feedback signal.
17. The power-on-reset circuit of claim 16, wherein the clock signal generation unit comprises a fourth inverter, a fifth inverter, a sixth inverter, a NAND gate, and a third capacitor,
the input end of the fourth inverter receives the first reset signal, and the output end of the fourth inverter is connected with the first input end of the NAND gate;
the input end of the fifth inverter receives the feedback signal, and the output end of the fifth inverter is connected with the input end of the sixth inverter;
the output end of the sixth inverter is connected with the second input end of the NAND gate;
the third capacitor is connected between the input end of the fifth inverter and the output end of the sixth inverter;
and the output end of the NAND gate outputs the clock signal.
18. The power-on-reset circuit according to claim 16, wherein the feedback signal generating unit includes a first resistor, a second resistor, and fourth and fifth capacitors,
the first resistor and the second resistor are connected in series between one end of the clock signal generation unit, which receives a feedback signal, and one end of the clock signal generation unit, which outputs a clock signal;
the fourth capacitor is connected between one end of the clock signal generating unit for receiving the feedback signal and the ground end,
and the fifth capacitor is connected between the connection node of the first resistor and the second resistor and the ground terminal.
19. The power-on-reset circuit of claim 1, wherein the power-on-reset circuit is coupled to a magnetoresistive sensor to ensure an effective delay of the magnetoresistive sensor.
20. The power-on-reset circuit of claim 1, wherein the power-on-reset circuit is for a magnetometer.
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| CN202020149940.8U CN211930610U (en) | 2020-01-31 | 2020-01-31 | Power-on reset circuit |
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| CN202020149940.8U CN211930610U (en) | 2020-01-31 | 2020-01-31 | Power-on reset circuit |
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| CN114302305A (en) * | 2021-12-28 | 2022-04-08 | 荣成歌尔微电子有限公司 | Power supply reset circuit, ASIC chip and microphone |
| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
| CN117240270A (en) * | 2023-09-15 | 2023-12-15 | 深圳市紫光同创电子有限公司 | Power-on reset circuit, chip and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114302305A (en) * | 2021-12-28 | 2022-04-08 | 荣成歌尔微电子有限公司 | Power supply reset circuit, ASIC chip and microphone |
| CN114302305B (en) * | 2021-12-28 | 2024-01-19 | 荣成歌尔微电子有限公司 | Power supply reset circuit, ASIC chip and microphone |
| CN116566370A (en) * | 2023-07-11 | 2023-08-08 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
| CN116566370B (en) * | 2023-07-11 | 2024-01-30 | 麦斯塔微电子(深圳)有限公司 | Power-on reset circuit |
| CN117240270A (en) * | 2023-09-15 | 2023-12-15 | 深圳市紫光同创电子有限公司 | Power-on reset circuit, chip and electronic equipment |
| CN117318674A (en) * | 2023-10-25 | 2023-12-29 | 晟芯腾跃(北京)科技有限公司 | Fuse detection control circuit generating pulse signals independently of OSC |
| CN117318674B (en) * | 2023-10-25 | 2024-06-04 | 晟芯腾跃(北京)科技有限公司 | Fuse detection control circuit generating pulse signals independently of OSC |
| CN117749150A (en) * | 2024-02-19 | 2024-03-22 | 北京中天星控科技开发有限公司成都分公司 | Quick and slow power-on reset circuit |
| CN117749150B (en) * | 2024-02-19 | 2024-04-19 | 北京中天星控科技开发有限公司成都分公司 | Quick and slow power-on reset circuit |
| CN118199592A (en) * | 2024-05-16 | 2024-06-14 | 博瑞集信(西安)电子科技股份有限公司 | Power-on reset circuit with adjustable low-voltage reset time |
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