CN117318674A - Fuse detection control circuit generating pulse signals independently of OSC - Google Patents
Fuse detection control circuit generating pulse signals independently of OSC Download PDFInfo
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- CN117318674A CN117318674A CN202311387698.2A CN202311387698A CN117318674A CN 117318674 A CN117318674 A CN 117318674A CN 202311387698 A CN202311387698 A CN 202311387698A CN 117318674 A CN117318674 A CN 117318674A
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- 238000001514 detection method Methods 0.000 title claims abstract description 54
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims description 6
- HCUOEKSZWPGJIM-IYNMRSRQSA-N (e,2z)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N\O)\C(N)=O HCUOEKSZWPGJIM-IYNMRSRQSA-N 0.000 claims 3
- 238000009966 trimming Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000007664 blowing Methods 0.000 description 4
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 description 3
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 description 3
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 description 3
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 description 3
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 description 3
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 2
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- 230000007547 defect Effects 0.000 description 2
- 101150070189 CIN3 gene Proteins 0.000 description 1
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- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
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- 101150110298 INV1 gene Proteins 0.000 description 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A fuse detection control circuit which does not depend on OSC to generate pulse signals relates to the technical field of integrated circuits, and comprises a fuse detection signal generation circuit, a fuse control signal generation circuit and a fuse control circuit, wherein: the fuse detection signal generating circuit is used for generating a fuse detection pulse signal, and the first, second and third pulse signal output ends of the fuse detection signal generating circuit are connected to the fuse control signal generating circuit; the fuse control signal generating circuit receives the fuse detection pulse signal, is used for detecting the state of the fuse and generating a fuse control signal, and the output end of the fuse control signal is connected to the fuse control circuit; the fuse control circuit is used for controlling the connection and disconnection of the resistor into and from the circuit. The invention can realize the trimming of the fuse more accurately and easily, simplifies the effective pulse generating circuit without using an OSC circuit, saves the chip area, reduces the design complexity and reduces the power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a fuse detection control circuit which does not depend on an OSC to generate pulse signals.
Background
In the conventional fuse trimming circuit, fuses are directly connected to two ends of a circuit device to be connected, as shown in fig. 1, the circuit is simple but has a large defect. First, the fuse may not be fully blown after trimming, the fuse is not in an ideal open state, and some situations may be reduced to below 100kΩ, where the fuse will be used as a resistor in parallel at two ends of a device to be broken, so as to affect circuit performance and parameter accuracy. Second, the simple fuse connection makes the device only capable of being connected into a circuit, and cannot short-circuit the device already connected into the circuit, and this defect limits the flexibility of circuit trimming. Third, such fuse trimming techniques are susceptible to the environment of the chip, and changes in the environment surrounding the fuse will affect the electrical performance of the blown fuse, thereby affecting circuit parameters and performance.
The improvement of some existing fuse trimming circuits is that an NMOS switching device is connected in parallel to two ends of a device needing to be connected or short-circuited, a control signal is used for controlling the conduction state of the switching device, the initial state of the switch is set through a specific circuit, and the initial state of the switch is changed through blowing of a fuse. The fuse state detection circuit detects the state of the fuse and outputs a fuse state signal to control the on or off of the switching device. The fuse state is locked by the latch by using a pulse detection method in both the fuse detection and fuse state output circuits, and the OSC oscillator circuit is used for pulse generation, as shown in fig. 2. The addition of OSC blocks in the fuse detection circuit not only increases the complexity of the fuse detection circuit but also increases the risk of the fuse detection circuit.
Disclosure of Invention
The invention aims to provide a fuse detection control circuit which does not depend on an OSC to generate pulse signals, so that fuse trimming can be realized more accurately and easily, an OSC circuit is not needed to be used in a simplified and effective pulse generating circuit, the chip area is saved, the design complexity is reduced, and the power consumption is reduced.
In order to achieve the above purpose, the invention adopts the following technical scheme: a fuse detection control circuit generating pulse signals independently of OSC is composed of a fuse detection signal generating circuit, a fuse control signal generating circuit and a fuse control circuit;
the fuse detection signal generation circuit is used for generating a fuse detection pulse signal, and a first pulse signal output end, a second pulse signal output end and a third pulse signal output end of the fuse detection signal generation circuit are all connected to the fuse control signal generation circuit;
the fuse control signal generating circuit receives the fuse detection pulse signal, is used for detecting the state of a fuse and generating a fuse control signal, and the output end of the fuse control signal is connected to the fuse control circuit;
the input end of the fuse control circuit is connected with the fuse control signal output end of the fuse control signal generating circuit and is used for controlling the connection and disconnection of the resistor to and from the circuit.
Further, the fuse detection signal generation circuit has a structure that:
the grid electrode of the first PMOS tube is connected with the grid electrode of the second NMOS tube to form a second reference point, the source electrode of the first PMOS tube is connected with the power supply VIN, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the seventeenth PMOS tube to form a sixth reference point;
the source electrode of the second NMOS tube is grounded;
the source electrode of the seventeenth PMOS tube is connected with the power supply VIN through the third resistor, and the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of the seventh NMOS tube through the first resistor and the second resistor which are sequentially connected in series to form a seventh reference point;
the gates of the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube are all connected to a seventh reference point, and the sources thereof are all connected to a sixth reference point;
the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube to form a fourth reference point;
the drain electrode of the ninth NMOS tube is connected with the drain electrode of the tenth NMOS tube and the source electrode of the sixteenth NMOS tube;
the grid electrode of the sixteenth NMOS tube is grounded;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the fourteenth NMOS tube to form a fifth reference point;
the grid electrode of the twelfth NMOS tube is connected with a seventh reference point, and the source electrode of the twelfth NMOS tube is grounded;
the grid electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are connected to a sixth reference point, and the source electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are grounded;
the grid electrode and the drain electrode of the fourth PMOS tube are connected to a fourth reference point, and the source electrode of the fourth PMOS tube is connected with a power supply VIN through a fourth resistor;
the grid electrode of the fifth PMOS tube is connected to a fourth reference point, the source electrode of the fifth PMOS tube is connected to the power supply VIN through a fifth resistor, and the drain electrode of the fifth PMOS tube is connected to the fifth reference point;
the grid electrode of the sixth PMOS tube is connected to a fourth reference point, the source electrode of the sixth PMOS tube is connected with the power supply VIN through a sixth resistor, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the twelfth NMOS tube to form a first reference point;
the first reference point is grounded through a first capacitor;
the power-on reset signal POR is connected with the grid electrode of a fifteenth NMOS tube through a first inverter, a second inverter and a third inverter which are sequentially connected in series, the drain electrode of the fifteenth NMOS tube is connected with a first reference point, and the source electrode of the fifteenth NMOS tube is grounded;
the first reference point is connected with one input end of the first AND gate through a sixth inverter, a seventh inverter and an eighth inverter which are sequentially connected in series to form a third reference point, and a power-on reset signal POR is connected with the other input end of the first AND gate;
the output end of the first AND gate is connected with one input end of the first NOR gate, and the other input end of the first NOR gate is grounded;
the output end of the first NOR gate is connected with a second reference point through a ninth inverter;
the fourth reference point is used as a first pulse signal output end;
the seventh reference point is used as a second pulse signal output end;
the fifth reference point is sequentially connected with the fourth inverter and the fifth inverter, and the output end of the fifth inverter is used as the third pulse signal output end.
Further, the fuse control signal generating circuit has a structure of;
the grid electrode of the eighteenth PMOS tube is connected with the first pulse signal output end of the fuse detection signal generating circuit, the source electrode of the eighteenth PMOS tube is connected with the power supply VIN through a fuse, and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the nineteenth NMOS tube and the drain electrode of the twenty first PMOS tube;
the grid electrode of the nineteenth NMOS tube is connected with the second pulse signal output end of the fuse detection signal generating circuit, and the source electrode of the nineteenth NMOS tube is connected with the drain electrode of the twentieth NMOS tube;
the grid electrode of the twenty-second NMOS tube is connected with the third pulse signal output end of the fuse detection signal generating circuit, and the source electrode of the twenty-second NMOS tube is grounded;
the grid electrode of the twenty-first PMOS tube is connected with the third pulse signal output end of the fuse detection signal generation circuit, the source electrode of the twenty-first PMOS tube is connected with the power supply VIN, and the drain electrode of the twenty-first PMOS tube is connected with one input end of the latch through a tenth inverter and an eleventh inverter which are sequentially connected in series;
the power-on reset signal POR is connected with the other input end of the latch;
the latch consists of a first NAND gate and a second NAND gate;
the output end of the second NAND gate is connected with the input end of the twelfth inverter;
the twelfth inverter output outputs the fuse control signal as the fuse control signal output.
Further, the fuse control circuit has a structure that; the NMOS switching tube is connected in parallel with two ends of a resistor which is required to be connected into or disconnected from the circuit, and the fuse control signal output end of the fuse control signal generating circuit is connected to the grid electrode of the NMOS switching tube.
The initial state of the NMOS switching tube can be set by a fuse control signal generation circuit of a front stage, and the initial state of the NMOS switching tube is changed by blowing fuses, so that the corresponding resistor is connected into the circuit or disconnected from the circuit.
The beneficial effects of the invention are as follows:
the invention can realize the trimming of the fuse more accurately and easily, simplifies the effective pulse generating circuit without using an OSC circuit, saves the chip area, reduces the design complexity and reduces the power consumption.
Drawings
FIG. 1 is a schematic diagram of a conventional fuse trimming circuit;
fig. 2 is a prior art fuse sense control circuit with OSC;
FIG. 3 is a general block diagram of a circuit of an embodiment of the present invention;
FIG. 4 is a specific block diagram of a fuse detect signal generation circuit according to an embodiment of the present invention;
FIG. 5 is a specific block diagram of a fuse control signal generation circuit according to an embodiment of the present invention;
fig. 6 is a specific structural diagram of a fuse control circuit according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 3 to 6 show a specific embodiment of the present invention, which is a fuse detection control circuit that generates a pulse signal without depending on OSC, composed of a fuse detection signal generation circuit, a fuse control signal generation circuit, and a fuse control circuit;
the fuse detection signal generating circuit is used for generating a fuse detection pulse signal, and the first pulse signal output end VPULSE1, the second pulse signal output end VPULSE2 and the third pulse signal output end VPULSE3 of the fuse detection signal generating circuit are all connected to the fuse control signal generating circuit;
the fuse control signal generating circuit receives the fuse detection pulse signal, is used for detecting the state of a fuse and generating a fuse control signal, and the fuse control signal output end CTRL of the fuse control signal generating circuit is connected to the fuse control circuit;
the input end of the fuse control circuit is connected with the fuse control signal output end CTRL of the fuse control signal generating circuit and is used for controlling the connection and disconnection of the resistor into and from the circuit.
In this embodiment, the fuse detection signal generating circuit has a structure as follows:
the grid electrode of the first PMOS tube M1 is connected with the grid electrode of the second NMOS tube M2 to form a second reference point B, the source electrode of the first PMOS tube M1 is connected with the power supply VIN, and the drain electrode of the first PMOS tube M2 is connected with the drain electrode of the seventeenth PMOS tube M17 to form a sixth reference point F;
the source electrode of the second NMOS tube M2 is grounded;
the source electrode of the seventeenth PMOS tube M17 is connected with the power supply VIN through the third resistor R3, and the drain electrode is connected with the drain electrode of the seventh NMOS tube M7 through the first resistor R1 and the second resistor R2 which are sequentially connected in series to form a seventh reference point G;
the gates of the seventh NMOS tube M7, the eighth NMOS tube M8, the ninth NMOS tube M9, the tenth NMOS tube M10 and the eleventh NMOS tube M11 are connected to a seventh reference point G, and the sources thereof are connected to a sixth reference point F;
the drain electrode of the eighth NMOS tube M8 is connected with the drain electrode of the sixteenth NMOS tube M16 to form a fourth reference point D;
the drain electrode of the ninth NMOS tube M9 is connected with the drain electrode of the tenth NMOS tube M10 and the source electrode of the sixteenth NMOS tube M16;
the grid electrode of the sixteenth NMOS tube M16 is grounded;
the drain electrode of the eleventh NMOS tube M11 is connected with the drain electrode of the fourteenth NMOS tube M14 to form a fifth reference point E;
the grid electrode of the twelfth NMOS tube M12 is connected with a seventh reference point G, and the source electrode of the twelfth NMOS tube M12 is grounded;
the grid electrodes of the thirteenth NMOS tube M13 and the fourteenth NMOS tube M14 are connected to a sixth reference point F, and the source electrodes are grounded;
the grid electrode and the drain electrode of the fourth PMOS tube M4 are connected to a fourth reference point D, and the source electrode of the fourth PMOS tube M4 is connected to a power supply VIN through a fourth resistor R4;
the grid electrode of the fifth PMOS tube M5 is connected to a fourth reference point D, the source electrode of the fifth PMOS tube M5 is connected to a power supply VIN through a fifth resistor R5, and the drain electrode of the fifth PMOS tube M5 is connected to a fifth reference point E;
the grid electrode of the sixth PMOS tube M6 is connected to a fourth reference point D, the source electrode of the sixth PMOS tube M6 is connected to the power supply VIN through a sixth resistor R6, and the drain electrode of the sixth PMOS tube M6 is connected to the drain electrode of the twelfth NMOS tube M12 to form a first reference point A;
the first reference point A is grounded through a first capacitor C1;
the power-on reset signal POR is connected with the grid electrode of a fifteenth NMOS tube M15 through a first inverter INV1, a second inverter INV2 and a third inverter INV3 which are sequentially connected in series, the drain electrode of the fifteenth NMOS tube M15 is connected with a first reference point A, and the source electrode of the fifteenth NMOS tube M15 is grounded;
the first reference point A is connected with one input end of a first AND gate AND1 through a sixth inverter INV6, a seventh inverter INV7 AND an eighth inverter INV8 which are sequentially connected in series to form a third reference point C, AND a power-on reset signal POR is connected with the other input end of the first AND gate AND 1;
the output end of the first AND gate AND1 is connected with one input end of the first NOR gate NOR1, AND the other input end of the first NOR gate NOR1 is grounded;
the output end of the first NOR gate NOR1 is connected with a second reference point B through a ninth inverter INV 9;
the fourth reference point D is used as a first pulse signal output end VPULSE1;
the seventh reference point G is taken as a second pulse signal output end VPULSE2;
the fifth reference point E is sequentially connected to the fourth inverter INV4 and the fifth inverter INV5, and an output end of the fifth inverter INV5 is used as the third pulse signal output end VPULSE3.
The fuse detection signal generating circuit is used for generating a pulse signal, and the fuse control signal generating circuit detects the state of a fuse in the period of the pulse signal and generates a fuse control signal so as to determine parameters of the trimming circuit. The pulse generating circuit is not based on the OSC signal and performs frequency division and other logic operations on the OSC signal, but is skillfully formed by charging and discharging a capacitor through a logic circuit. During the power-on period of the input voltage VIN, the power-on reset signal POR is low, the level of the first reference point a is low, and the level of the third reference point C is high. When the power-on reset signal POR becomes high, the potential of the second reference point B becomes high, the current mirror starts to work, the current of the branch of the sixth PMOS tube M6 is larger than that of the branch of the twelfth NMOS tube M12, the difference between the current of the branch of the M6 and the current of the branch of the M12 charges the first capacitor C1, the VPULSE3 outputs high-level pulse before the potential of the first reference point A becomes high level, and the VPULSE2 and the VPULSE1 output voltages for maintaining the current mirror current. When the potential of the first reference point A becomes high, the current mirror stops working, and the circuit is turned off to stop consuming current. The difference between the current of the M6 branch and the current of the M12 branch and the capacitance value of the first capacitor C1 determine the width of the pulse, so that the pulse generation circuit is very convenient to adjust, and the pulse generation circuit only works in a few microseconds or hundreds of nanoseconds generated by the pulse, so that the power consumption is very saved.
In this embodiment, the fuse control signal generating circuit has a structure as follows;
the grid electrode of the eighteenth PMOS tube M18 is connected with the first pulse signal output end VPULSE1 of the FUSE detection signal generation circuit, the source electrode is connected with the power supply VIN through the FUSE, and the drain electrode is connected with the drain electrode of the nineteenth NMOS tube M19 and the drain electrode of the twenty first PMOS tube M21;
the grid electrode of the nineteenth NMOS tube M19 is connected with the second pulse signal output end VPULSE2 of the fuse detection signal generation circuit, and the source electrode of the nineteenth NMOS tube M19 is connected with the drain electrode of the twentieth NMOS tube M20;
the grid electrode of the twentieth NMOS tube M20 is connected with the third pulse signal output end VPULSE3 of the fuse detection signal generation circuit, and the source electrode is grounded;
the grid electrode of the twenty-first PMOS tube M21 is connected with the third pulse signal output end VPULSE3 of the fuse detection signal generation circuit, the source electrode is connected with the power supply VIN, and the drain electrode is connected with one input end of the latch through a tenth inverter INV10 and an eleventh inverter INV11 which are sequentially connected in series;
the power-on reset signal POR is connected with the other input end of the latch;
the latch consists of a first NAND gate NAND1 and a second NAND gate NAND 2;
the output end of the second NAND gate NAND2 is connected with the input end of the twelfth inverter INV 12;
the twelfth inverter INV12 outputs the fuse control signal as the fuse control signal output terminal CTRL.
The invention adopts the latch to generate the fuse control signal, and the advantage of the latch is that the fuse control signal is latched after the fuse is detected, and the subsequent change of the fuse state does not influence the fuse control signal any more. When the power-on reset signal POR is low (power enable phase), the fuse control signal is low; when the POR signal goes high, the pre-stage circuit gives a PULSE signal to detect the fuse state, and the PULSE signal is shown in fig. 5, if the fuse is not blown, the eighteenth PMOS transistor M18 and the nineteenth NMOS transistor M19 form a current comparator, the eighteenth PMOS transistor M18 has a current greater than the nineteenth NMOS transistor M19, and the fuse control signal output end CTRL outputs a low level. If the fuse is blown, the current of the nineteenth NMOS tube M19 is larger than that of the eighteenth PMOS tube M18, and the fuse control signal output end CTRL outputs a high level. The detection method is not sensitive to the resistance value of the fuse after the fuse is blown, and even if the resistance value of the fuse after the fuse is blown is as low as a few KΩ, the current comparator can output correct logic potential, thereby completely avoiding errors and even errors caused by insufficient fuse blowing.
In this embodiment, the fuse control circuit has a structure as follows; the three resistors to be connected to or disconnected from the circuit are a thirty-first resistor R31, a thirty-second resistor R32 and a thirty-third resistor R33, and the thirty-first NMOS switch tube M31, the thirty-second NMOS switch tube M32 and the thirty-third NMOS switch tube M33 are connected in parallel at two ends of the three resistors, respectively, so that the three fuse control signal generating circuits are required to generate three fuse control signals, and the gates of the three NMOS switch tubes are connected to serve as switch tube control signals.
The initial states of the three NMOS switching tubes can be respectively set through corresponding front-stage fuse control signal generation circuits, and the initial states of the three NMOS switching tubes can be changed through blowing corresponding fuses, so that the corresponding resistors can be connected into the circuit or disconnected from the circuit.
Claims (4)
1. A fuse detection control circuit that generates a pulse signal independently of OSC, characterized in that:
the device consists of a fuse detection signal generating circuit, a fuse control signal generating circuit and a fuse control circuit;
the fuse detection signal generating circuit is used for generating a fuse detection pulse signal, and a first pulse signal output end (VPULSE 1), a second pulse signal output end (VPULSE 2) and a third pulse signal output end (VPULSE 3) of the fuse detection signal generating circuit are all connected to the fuse control signal generating circuit;
the fuse control signal generating circuit receives the fuse detection pulse signal, is used for detecting the state of a fuse and generating a fuse control signal, and a fuse control signal output end (CTRL) of the fuse control signal generating circuit is connected to the fuse control circuit;
the fuse control circuit input end is connected with a fuse control signal output end (CTRL) of the fuse control signal generation circuit and is used for controlling the connection and disconnection of the resistor into and from the circuit.
2. The fuse detection control circuit of claim 1, wherein the fuse detection signal generation circuit is configured to generate the pulse signal independently of the OSC by:
the grid electrode of the first PMOS tube (M1) is connected with the grid electrode of the second NMOS tube (M2) to form a second reference point (B), the source electrode of the first PMOS tube is connected with the power source VIN, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube (M2) and the grid electrode of the seventeenth PMOS tube (M17) to form a sixth reference point (F);
the source electrode of the second NMOS tube (M2) is grounded;
the source electrode of the seventeenth PMOS tube (M17) is connected with the power supply VIN through the third resistor (R3), and the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of the seventh NMOS tube (M7) through the first resistor (R1) and the second resistor (R2) which are sequentially connected in series to form a seventh reference point (G);
the gates of the seventh NMOS tube (M7), the eighth NMOS tube (M8), the ninth NMOS tube (M9), the tenth NMOS tube (M10) and the eleventh NMOS tube (M11) are connected to a seventh reference point (G), and the sources thereof are connected to a sixth reference point (F);
the drain electrode of the eighth NMOS tube (M8) is connected with the drain electrode of the sixteenth NMOS tube (M16) to form a fourth reference point (D);
the drain electrode of the ninth NMOS tube (M9) is connected with the drain electrode of the tenth NMOS tube (M10) and the source electrode of the sixteenth NMOS tube (M16);
the grid electrode of the sixteenth NMOS tube (M16) is grounded;
the drain electrode of the eleventh NMOS tube (M11) is connected with the drain electrode of the fourteenth NMOS tube (M14) to form a fifth reference point (E);
the grid electrode of the twelfth NMOS tube (M12) is connected with a seventh reference point (G), and the source electrode of the twelfth NMOS tube is grounded;
the grid electrodes of the thirteenth NMOS tube (M13) and the fourteenth NMOS tube (M14) are connected to a sixth reference point (F), and the source electrodes are grounded;
the grid electrode and the drain electrode of the fourth PMOS tube (M4) are connected to a fourth reference point (D), and the source electrode of the fourth PMOS tube is connected to the power supply VIN through a fourth resistor (R4);
the grid electrode of the fifth PMOS tube (M5) is connected to a fourth reference point (D), the source electrode of the fifth PMOS tube is connected to the power supply VIN through a fifth resistor (R5), and the drain electrode of the fifth PMOS tube is connected to a fifth reference point (E);
the grid electrode of the sixth PMOS tube (M6) is connected to the fourth reference point (D), the source electrode of the sixth PMOS tube is connected with the power supply VIN through the sixth resistor (R6), and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the twelfth NMOS tube (M12) to form a first reference point (A);
the first reference point (A) is grounded through a first capacitor (C1);
the power-on reset signal POR is connected with the grid electrode of a fifteenth NMOS tube (M15) through a first inverter (INV 1), a second inverter (INV 2) and a third inverter (INV 3) which are sequentially connected in series, the drain electrode of the fifteenth NMOS tube (M15) is connected with a first reference point (A), and the source electrode of the fifteenth NMOS tube is grounded;
the first reference point (A) is connected with one input end of a first AND gate (AND 1) through a sixth inverter (INV 6), a seventh inverter (INV 7) AND an eighth inverter (INV 8) which are sequentially connected in series to form a third reference point (C), AND a power-on reset signal POR is connected with the other input end of the first AND gate (AND 1);
the output end of the first AND gate (AND 1) is connected with one input end of the first NOR gate (NOR 1), AND the other input end of the first NOR gate (NOR 1) is connected with the ground;
the output end of the first NOR gate (NOR 1) is connected with a second reference point (B) through a ninth inverter (INV 9);
a fourth reference point (D) as a first pulse signal output (VPULSE 1);
a seventh reference point (G) as a second pulse signal output (VPULSE 2);
the fifth reference point (E) is sequentially connected with the fourth inverter (INV 4) and the fifth inverter (INV 5), and the output end of the fifth inverter (INV 5) is used as a third pulse signal output end (VPULSE 3).
3. The fuse detection control circuit of claim 1, wherein the fuse control signal generation circuit is configured to generate the pulse signal independently of the OSC;
the grid electrode of the eighteenth PMOS tube (M18) is connected with the first pulse signal output end (VPULSE 1) of the FUSE detection signal generation circuit, the source electrode of the eighteenth PMOS tube is connected with the power supply VIN through the FUSE (FUSE), and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the nineteenth NMOS tube (M19) and the drain electrode of the twenty first PMOS tube (M21);
the grid electrode of the nineteenth NMOS tube (M19) is connected with the second pulse signal output end (VPULSE 2) of the fuse detection signal generation circuit, and the source electrode of the nineteenth NMOS tube (M20) is connected with the drain electrode of the twenty second NMOS tube;
the grid electrode of the twenty-second NMOS tube (M20) is connected with the third pulse signal output end (VPULSE 3) of the fuse detection signal generation circuit, and the source electrode is grounded;
the grid electrode of the twenty-first PMOS tube (M2) is connected with the third pulse signal output end (VPULSE 3) of the fuse detection signal generation circuit, the source electrode is connected with the power supply VIN, and the drain electrode is connected with one input end of the latch through a tenth inverter (INV 10) and an eleventh inverter (INV 11) which are sequentially connected in series;
the power-on reset signal POR is connected with the other input end of the latch;
the latch consists of a first NAND gate (NAND 1) and a second NAND gate (NAND 2);
the output end of the second NAND gate (NAND 2) is connected with the input end of the twelfth inverter (INV 12);
the twelfth inverter (INV 12) outputs the fuse control signal as the fuse control signal output (CTRL).
4. The fuse detection control circuit of claim 1, wherein the fuse control circuit is configured to generate the pulse signal independently of the OSC; the NMOS switching tube is connected in parallel with two ends of a resistor which needs to be connected into or disconnected from the circuit, and a fuse control signal output end (CTRL) of the fuse control signal generating circuit is connected to a grid electrode of the NMOS switching tube.
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