CN106253882A - The wide scope time delay circuit of band model handoff functionality - Google Patents
The wide scope time delay circuit of band model handoff functionality Download PDFInfo
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- CN106253882A CN106253882A CN201610890469.6A CN201610890469A CN106253882A CN 106253882 A CN106253882 A CN 106253882A CN 201610890469 A CN201610890469 A CN 201610890469A CN 106253882 A CN106253882 A CN 106253882A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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Abstract
The wide scope time delay circuit of band model handoff functionality, the present invention relates to double mode delay circuit technical field, solves prior art and can not carry out the technical problems such as the most on-demand handoff delay time.The invention mainly comprises reference signal module, be used for providing short delay pulse to trigger；Short-time delay module, receives the reference signal exported by reference signal module；Long delay module, including agitator and frequency dividing chronotron；Time delay handover module, receives the short time delayed signal exported by short-time delay module；Delay selection module, the long delay signal synchronize to receive the short time delayed signal exported by short-time delay module, being exported by agitator in long delay module by frequency dividing chronotron and the synchronism switching signal exported by time delay handover module, and export short delay output signal or long delay output signal by synchronism switching signal behavior ground.The present invention designs for delay circuit.
Description
Technical field
The present invention relates to double mode delay circuit technical field, the wide scope time being specifically related to band model handoff functionality prolongs
Circuit late.
Background technology
Traditional time delay circuit: be typically only capable to take into account one of which, or short delay circuit, or long delay
Circuit, and Precision Rough.Or the error for short time delay just becomes very realizing long-time delay feature when
Greatly, on the contrary long-time delay feature cannot be realized when realizing short time delay function.
Summary of the invention
For above-mentioned prior art, present invention aim at providing the wide scope time delay electricity of band model handoff functionality
Road, solves prior art and can not carry out the technical problems such as the most on-demand handoff delay time.
For reaching above-mentioned purpose, the technical solution used in the present invention is as follows:
The wide scope time delay circuit of band model handoff functionality, including
Reference signal module, is used for providing short delay pulse to trigger；
Short-time delay module, receives the reference signal that exported by reference signal module, and short-time delay module includes electric capacity and the
One comparator, the first comparator is connected to the first reference voltage, and short-time delay module controls capacitance voltage by the first reference voltage and becomes
Change and constitute short delay pulse window；
Long delay module, including agitator and frequency dividing chronotron；
Time delay handover module, receives the short time delayed signal exported by short-time delay module；
Delay selection module, synchronize receive exported by short-time delay module short time delayed signal, by long delay module vibrate
Device is by the long delay signal dividing chronotron output and the synchronism switching signal exported by time delay handover module, and passes through to synchronize
Switching signal selectively exports short delay output signal or long delay output signal.
In such scheme, described reference signal module, select reference current source.
In such scheme, described short-time delay module, including
Amplifier, its homophase amplifies end and receives reference signal and anti-phase amplification end ground connection；
The first transistor, its grid connects outfan and the source ground of amplifier；
Transistor seconds, its drain electrode connects the drain electrode of the first transistor；
Third transistor, with transistor seconds collectively form same drain potential point, with grid potential point trickle amplify electricity
Road；
Electric capacity, is used for modulating short delay pulse window, and its one end connects source electrode and the other end ground connection of third transistor；
First comparator, its input port connects the drain electrode of third transistor and receives the first reference voltage and export short prolonging
Time signal；
4th transistor, its grid connects the outfan of the first comparator, and its drain electrode connects the source electrode of third transistor, its
Source electrode is connected with capacity earth end；
Time delay latch, for buffering and the short time delayed signal of set the first comparator output, it exports short time delayed signal
To delay selection module.
In such scheme, described frequency dividing chronotron, connect including the enumerator being made up of d type flip flop array and enumerator
The latch connect and the set logic circuit controlled for enumerator output, latch output long delay signal is to delay selection mould
Block.
In such scheme, described time delay handover module, including the second comparator, the input port of the second comparator receives
Short time delayed signal and the second reference voltage and its outfan output synchronism switching signal are to delay selection module.
In such scheme, described time delay handover module, also include two phase inverters of series connection or plural even number
Individual phase inverter, constitutes even number set phase inverter array, and the input of even number set phase inverter array connects the outfan of the second comparator.
In such scheme, described delay selection module, including
First NAND gate, its input port receives short time delayed signal；
First phase inverter, its input reception synchronism switching signal and outfan are connected to the input of the first NAND gate
Mouthful；
Second NAND gate, its input port receives long delay signal and connects the input of the first phase inverter；
Second phase inverter, its input connects the outfan of the first NAND gate；
3rd phase inverter, its input connects the outfan of the second NAND gate；
First nor gate, its input port connects the second phase inverter and the outfan of the 3rd phase inverter；
4th phase inverter, its input connects the outfan of the first nor gate；
The 4th described phase inverter, exports short delay output signal or long delay output by synchronism switching signal behavior
Signal.
In such scheme, described set logic circuit, including
Enable signal, the first delayed modulation signal and the second delayed modulation signal；
One aaset bit transistor, count pick up device output signal, the first delayed modulation signal and the second delayed modulation signal；
Delay capacitor, for the time delay of the output signal of an aaset bit transistor；
Transistor is amplified in a pair output, receives the output signal of an aaset bit transistor；
The output signal of transistor is amplified in XOR gate, the output signal of count pick up device and a pair output；
Long delay signal after second nor gate, the output signal of reception XOR gate and enable signal and output set is to locking
Storage.
In such scheme, described agitator, including
3rd NAND gate, its input port receives power-on reset signal；
5th phase inverter, the outfan of its input connection the 3rd NAND gate and outputting oscillation signal are to dividing chronotron；
Hex inverter, its input connects the outfan of the 3rd NAND gate；
Schmidt trigger, its input connects the outfan of hex inverter and outfan is connected to the 3rd NAND gate
Input port；
Described Schmidt trigger and hex inverter constitute the self-feedback ciucuit of agitator.
Compared with prior art, beneficial effects of the present invention:
Time delay, wide ranges, can need to arrange flexibly in conjunction with actual application, and when for uncertain delay
Between applied environment time, the higher delay precision in the wide range delay time can be obtained by intelligent mode switching；And utilize
Set logic processing of circuit pulse signal, improves the versatility of the present invention further.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the present invention；
Fig. 2 is the set logic circuit diagram of the present invention；
Fig. 3 is the circuit diagram of the delay selection module of the present invention；
Fig. 4 is pierce circuit of the present invention；
Fig. 5 is that the present invention divides chronotron；
Fig. 6 is the circuit diagram of short-time delay module of the present invention.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually exclusive
Feature and/or step beyond, all can combine by any way.
The present invention will be further described below in conjunction with the accompanying drawings:
Embodiment 1
The built-in two kinds of time delays patterns of the present invention, are short time delay circuit and long-time delay circuit respectively, pass through
Numeral chip select circuit carries out pattern switching, such that it is able to realize wide scope time delay function.
Reference current source, the current settings in time charging electric capacity, this current precision is the highest, and time delay is the most accurate.
Trickle charging circuit and multilevel iudge circuit (i.e. comparator circuit), by the constant precision current (trickle) set
Electric capacity is charged, makes capacitance voltage raise, thus reach to compare threshold value, thus trigger comparator upset, deadline delay is sentenced
Break and labelling.
Pierce circuit, provides reference frequency for frequency dividing circuit, it is achieved long-time delay feature.
Selector circuit (sheet selects control circuit), selects short time delay and the long-time both of which that postpones and cuts
Change.
Circuit is always schemed as it is shown in figure 1, circuit overall includes short time delay circuit, Long-time-delay circuit, data selector and partially
Circuits.
Long-time-delay circuit is to realize longer delay time, uses enumerator to carry out time delay counting.During its work, first make
Can signal to constituting the d type flip flop of enumerator, and latch carries out set.After enabling effectively, circuit is started working, the most often
When input signal changes, then produce a counter set pulse, make counting start from scratch.When enumerator highest order is by 1
When becoming 0, after phase inverter, produce the rising triggering edge being become 1 from 0, control latch storage input-output data,
Clock input is turned off by the high level of phase inverter output simultaneously, stops counting, and output data do not change.Until input signal
When again there is upset, again to counter set, carry out again the next counting cycle.If input signal is the highest at enumerator
Position overturns before becoming 0 again, and the most former input data invalid will not be transferred into outfan.
Counter set logic circuit is as in figure 2 it is shown, DELAY1, DELAY2 are the electric current driving with relative different directions
Signal, IN is that set triggers signal, takes one and enables signal ENB=1, exports SET_0=0, to counter set.When this enable
Signal ENB=0, SET_0 are determined by XOR gate output.Input one end of XOR gate directly connects input signal, and another terminates input
Signal signal after time delay after a while, its role is to, and when input signal occurs upset, XOR gate all can export
One short pulse punching, so that SET_0 produces a short pulse sets signal.
Such as Fig. 3, described delay selection module, the first NAND gate U3, its input port receives short time delayed signal；First is anti-
Phase device U6, its input reception synchronism switching signal and outfan are connected to the input port of the first NAND gate U3；Second with non-
Door U4, its input port receives long delay signal and connects the input of the first phase inverter U6；Second phase inverter U8, its input
Connect the outfan of the first NAND gate U3；3rd phase inverter U9, its input connects the outfan of the second NAND gate U4；First or
Not gate U5, its input port connects the second phase inverter U8 and the outfan of the 3rd phase inverter U9；4th phase inverter U19, its input
End connects the outfan of the first nor gate U5；The 4th described phase inverter U19, exports short prolonging by synchronism switching signal behavior
Time output signal or long delay output signal.Wherein I N1 is long delay signal, and I N2 is short delay signal.
As Fig. 4, POR are a powering up reset signal；EN is to enable signal；OSC_PUL is outputting oscillation signal.Described vibration
Device, including the 3rd NAND gate U11, its input port receives power-on reset signal POR；5th phase inverter U13, its input connects
The outfan of the 3rd NAND gate U11 and outputting oscillation signal are to dividing chronotron；Hex inverter U12, its input connects the
The outfan of three NAND gate U11；Schmidt trigger U14, its input connects outfan and the outfan of hex inverter U12
It is connected to the input port of the 3rd NAND gate U11；Described Schmidt trigger U14 and hex inverter U12 constitutes agitator
Self-feedback ciucuit.This structure can increase by one and enable signal EN, receives power-on reset signal POR and enable by nor gate
Signal EN, its outfan is then connected to the 3rd NAND gate U11.Additionally, hex inverter U12 is then connected to execute by RC wave filter
The input of schmitt trigger U4.
Such as Fig. 5, for the frequency dividing chronotron of long delay, OSC_PUL is the oscillator signal of the certain frequency that agitator produces,
The R end of the d type flip flop array of cascade is all connected with por signal, and status set when being used for powering on, U18 is latch Latch.
Short time delay circuit as shown in Figure 6, current source and electric current sink produce 1uA bias current, it is to capacitor charge and discharge
The voltage produced accesses comparator U7 normal phase input end.Comparator U7 inverting input connects respectively and is carried out selecting by transistor Q7
2.505V and 2.495V realizes the sluggishness of 10mV.When transistor Q7 input is become 0 by 1, current source starts to charge electric capacity C2,
Voltage is started from scratch rising, and now negative input end input is 2.505V, when positive input voltage rises to 2.505, comparator U7
Output high level, negative input end input becomes 2.495V.Transistor Q7 input from 0 become 1 time, then electric capacity C2 voltage is passed through by 5V
When electric current sinking electricity is down to 2.495V, comparator U7 overturns.Delay circuit delay time is expressed from the next:
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Belong to those skilled in the art in the technical scope that the invention discloses, the change that can readily occur in or replacement, all answer
Contain within protection scope of the present invention.
Claims (9)
1. the wide scope time delay circuit of band model handoff functionality, it is characterised in that include
Reference signal module, is used for providing short delay pulse to trigger；
Short-time delay module, receives the reference signal exported by reference signal module, and short-time delay module includes electric capacity and the first ratio
Relatively device, the first comparator is connected to the first reference voltage, and short-time delay module controls capacitance voltage change structure by the first reference voltage
Become short delay pulse window；
Long delay module, including agitator and frequency dividing chronotron；
Time delay handover module, receives the short time delayed signal exported by short-time delay module；
Delay selection module, synchronize receive exported by short-time delay module short time delayed signal, led to by agitator in long delay module
The long delay signal of undue frequency delay device output and the synchronism switching signal exported by time delay handover module, and pass through synchronism switching
Signal behavior ground exports short delay output signal or long delay output signal.
The wide scope time delay circuit of band model handoff functionality the most according to claim 1, it is characterised in that described
Reference signal module, selects reference current source.
The wide scope time delay circuit of band model handoff functionality the most according to claim 1 and 2, it is characterised in that institute
The short-time delay module stated, including
Amplifier, its homophase amplifies end and receives reference signal and anti-phase amplification end ground connection；
The first transistor, its grid connects outfan and the source ground of amplifier；
Transistor seconds, its source electrode connects the drain electrode of the first transistor；
Third transistor, collectively forms same source potential point, trickle amplifying circuit with grid potential point with transistor seconds；
Electric capacity, is used for modulating short delay pulse window, and its one end connects source electrode and the other end ground connection of third transistor；
First comparator, its input port connects the source electrode of third transistor and receives the first reference voltage and export short time delay letter
Number；
4th transistor, its grid connects the outfan of the first comparator, and its drain electrode connects the source electrode of third transistor, its source electrode
It is connected with capacity earth end；
Delay buffer, for buffering and the short time delayed signal of set the first comparator output, it exports short time delayed signal to prolonging
Time select module.
The wide scope time delay circuit of band model handoff functionality the most according to claim 1 and 2, it is characterised in that institute
The frequency dividing chronotron stated, the latch being connected with enumerator including the enumerator being made up of d type flip flop array and for enumerator
The set logic circuit that output controls, latch output long delay signal is to delay selection module.
The wide scope time delay circuit of band model handoff functionality the most according to claim 3, it is characterised in that described
Time delay handover module, including the second comparator, the input port of the second comparator receives short time delayed signal and the second reference voltage
And its outfan output synchronism switching signal is to delay selection module.
The wide scope time delay circuit of band model handoff functionality the most according to claim 5, it is characterised in that described
Time delay handover module, also includes two phase inverters of series connection or plural even number of inverters, constitutes even number set phase inverter
Array, the input of even number set phase inverter array connects the outfan of the second comparator.
The wide scope time delay circuit of band model handoff functionality the most according to claim 1, it is characterised in that described
Delay selection module, including
First NAND gate, its input port receives short time delayed signal；
First phase inverter, its input reception synchronism switching signal and outfan are connected to the input port of the first NAND gate；
Second NAND gate, its input port receives long delay signal and connects the input of the first phase inverter；
Second phase inverter, its input connects the outfan of the first NAND gate；
3rd phase inverter, its input connects the outfan of the second NAND gate；
First nor gate, its input port connects the second phase inverter and the outfan of the 3rd phase inverter；
4th phase inverter, its input connects the outfan of the first nor gate；
The 4th described phase inverter, exports short delay output signal or long delay output letter by synchronism switching signal behavior
Number.
The wide scope time delay circuit of band model handoff functionality the most according to claim 4, it is characterised in that described
Set logic circuit, including
Enable signal, the first delayed modulation signal and the second delayed modulation signal；
One aaset bit transistor, count pick up device output signal, the first delayed modulation signal and the second delayed modulation signal；
Delay capacitor, for the time delay of the output signal of an aaset bit transistor；
Transistor is amplified in a pair output, receives the output signal of an aaset bit transistor；
The output signal of transistor is amplified in XOR gate, the output signal of count pick up device and a pair output；
Long delay signal after second nor gate, the output signal of reception XOR gate and enable signal and output set is to latch
Device.
The wide scope time delay circuit of band model handoff functionality the most according to claim 1, it is characterised in that described
Agitator, including
3rd NAND gate, its input port receives power-on reset signal；
5th phase inverter, the outfan of its input connection the 3rd NAND gate and outputting oscillation signal are to dividing chronotron；
Hex inverter, its input connects the outfan of the 3rd NAND gate；
Schmidt trigger, its input connects the outfan of hex inverter and outfan is connected to the input of the 3rd NAND gate
Port；
Described Schmidt trigger and hex inverter constitute the self-feedback ciucuit of agitator.
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| CN201610890469.6A CN106253882B (en) | 2016-10-12 | 2016-10-12 | Wide range time delay circuit with mode switching function |
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| CN201610890469.6A CN106253882B (en) | 2016-10-12 | 2016-10-12 | Wide range time delay circuit with mode switching function |
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| CN106253882B CN106253882B (en) | 2023-06-27 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347244A (en) * | 2017-12-06 | 2018-07-31 | 西安智多晶微电子有限公司 | Multi-mode POR circuit for FPGA |
| CN109212951A (en) * | 2018-06-08 | 2019-01-15 | 宗仁科技(平潭)有限公司 | A kind of electronic watch and its driving chip |
| CN117318674A (en) * | 2023-10-25 | 2023-12-29 | 晟芯腾跃(北京)科技有限公司 | Fuse detection control circuit generating pulse signals independently of OSC |
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| CN117318674A (en) * | 2023-10-25 | 2023-12-29 | 晟芯腾跃(北京)科技有限公司 | Fuse detection control circuit generating pulse signals independently of OSC |
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| CN106253882B (en) | 2023-06-27 |
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