CN102055449A - Low power-consumption time-delay controllable POR (power on reset) method and circuit - Google Patents
Low power-consumption time-delay controllable POR (power on reset) method and circuit Download PDFInfo
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- CN102055449A CN102055449A CN 201010612344 CN201010612344A CN102055449A CN 102055449 A CN102055449 A CN 102055449A CN 201010612344 CN201010612344 CN 201010612344 CN 201010612344 A CN201010612344 A CN 201010612344A CN 102055449 A CN102055449 A CN 102055449A
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Abstract
The invention relates to a low power-consumption time-delay controllable POR (power on reset) method and circuit. Impulse waveform signals are generated through changing the input control end Vc of a programmable oscillator, wherein the period of the impulse waveform signals is T1; a counter counts the impulse waveform signals, and when the count value of the counter reaches a set value m, the output of the counter is changed from a logic low level into a logic high level; and an output buffer circuit outputs the logic high level as a POR signal, namely the time delay (Tdelay) required for realizing POR is m*T1, and the programmable oscillator and the counter are shut by utilizing the logic high level output by the buffer circuit. By utilizing the low power-consumption time-delay controllable POR method and circuit, the technical problems that the existing POR circuit is difficult to reach the delay of millisecond magnitude and can not change the time delay interval under the condition of not adopting off-chip capacitance are solved; and the time delay value can be programmed and changed, the delay of millisecond magnitude can be realized, and the circuit only has tiny instant power consumption.
Description
Technical field
The invention belongs to electricity field, relate to a kind of electrification reset method and circuit, relate in particular to the electrification reset method and the circuit of electric power management circuit in a kind of CMOS integrated circuit.
Background technology
In electric power management circuit, electrify restoration circuit Power On Reset (POR) comes to provide reset signal for circuit.Electrify restoration circuit is used to guarantee circuit at the initial stage of powering on, and can system not make a mistake because of the instability of supply voltage.Generally, export useful signal after requiring electrify restoration circuit that certain time of delay can be provided after supply voltage surpasses detection threshold, under the stable power voltage conditions, work to guarantee circuit.
Figure 1 shows that common electrify restoration circuit schematic diagram at present, circuit is mainly by voltage detecting circuit, and delay circuit and output buffer stage constitute.Wherein voltage detecting circuit is used for the electrifying condition of supply voltage is detected, delay circuit by to capacitor C 0 charging play time-lag action, the output buffer stage is amplified the output signal output of delay circuit and as the output of electrify restoration circuit.
The power up of electrify restoration circuit as shown in Figure 2, in supply voltage VDD power up, when supply voltage surpassed the threshold value VDET1 of voltage detecting circuit, voltage detecting circuit output V_det point became logic high by logic low; Delay circuit is started working, and to capacitor C 0 charging, V_delay point voltage waveform as shown in the figure; Be higher than the threshold voltage VTH+ of output buffer stage circuit when the V_delay point voltage after, the output POR_RESET of Schmidt trigger becomes high level signal by low level.After supply voltage was higher than detection voltage VDET1, Tdelay was after the time in time-delay as POR_RESET point waveform among Fig. 2, and the output POR_RESET of electrify restoration circuit becomes logic-high signal by logic low.
When supply voltage descends, when supply voltage is lower than VDET2, the V_det signal becomes logic low by logic high, the delay circuit discharge, and discharge time is rapid, much smaller than the charging interval, V_delay point voltage step-down, discharge time is rapid, much smaller than the charging interval, therefore through this point voltage after the very little time-delay less than the threshold voltage VTH-of output buffer stage circuit by high step-down, the output POR_RESET of electrify restoration circuit becomes logic-low signal.
Electrify restoration circuit shown in Figure 1 if the resistance and the electric capacity that adopt chip integration to become are realized time-delay, because capacitance density is very little on the sheet, can only be realized pf level electric capacity under the rational situation of chip area, can't reach the delay of millisecond magnitude.This just need adopt nF rank or other electric capacity of uF level to realize postponing outside sheet, and the defective of doing like this is the quantity that has increased a package pins and peripheral components; Simultaneously, because the resistance capacitance value size on the sheet is fixed, be difficult to change the time-delay of electrify restoration circuit by the method for programming.
Summary of the invention
In order to solve the above-mentioned technical problem that exists in the background technology, the invention provides a kind of electrify restoration circuit that under the situation that does not increase outer member, makes and realize that bigger time-delay also can realize the controlled electrification reset method and the circuit of low-power consumption time-delay of delaying time controlled.
Technical solution of the present invention is:
The controlled electrification reset method of a kind of low-power consumption time-delay may further comprise the steps:
1] the control end Vc by the input of n bit programmes to the period T 1 that programmable oscillator produces pulse waveform signal;
2] programmable oscillator produces pulse waveform signal and gives counter;
3] when supply voltage is higher than threshold value, counter begins the pulse waveform signal that programmable oscillator produces is counted;
4] after the count value of counter reaches set point, counter output becomes logic high by logic low;
5] output signal of counter is had the output of latching with the output buffer of Protection Counter Functions and become logic high as power-on reset signal by logic low;
6] close the programmable oscillator sum counter with the logic high of output buffer output.
The controlled electrify restoration circuit of a kind of low-power consumption time-delay comprises voltage detecting circuit and output buffer; The input termination supply voltage VDD of described voltage detecting circuit, earth terminal ground connection; Its special character is: also comprise the programmable oscillator of the pulse waveform signal that is used to export some cycles, counter and the inverter that count value is m; The output V_det of voltage detecting circuit meets the Enable Pin EN_CNT of counter, connects the control input end of output buffer simultaneously, is used for controlling the work of output buffer; Programmable oscillator has a control end Vc that the n bit of programming the cycle of oscillation of output signal is imported, the output Freq_out of programmable oscillator connects the input of counter, and the Enable Pin EN_OSC of programmable oscillator connects the signal of output POR_RESET behind inverter of output buffer; The output V_ctrl of counter connects the input of output buffer.
Above-mentioned output buffer is flip-flop circuit or the latch circuit that can realize latch function.
The preferred d type flip flop circuit of above-mentioned output buffer; The signal input part D of d type flip flop circuit meets supply voltage VDD; The output V_det of voltage detecting circuit meets the reset terminal Reset of d type flip flop circuit after by inverter; D type flip flop circuit output end Q meets the Enable Pin EN_OSC of programmable oscillator behind inverter; The output V_ctr of counter) meets the input end of clock CLK of d type flip flop circuit.
Advantage of the present invention is:
1, the invention provides controlled electrification reset method and the circuit of a kind of low-power consumption time-delay, by adding programmable oscillator, logical circuit such as counter and inverter, make electrify restoration circuit can under the situation that does not increase outer member, realize the time-delay that needs, and this delay value can be programmed by the input control end Ctrl of programmable oscillator.
2, the count value at counter is under the situation of m, by changing the input control end Vc of programmable oscillator, the generation cycle is the pulse waveform signal of T1, counter is counted the output pulse waveform signal of programmable oscillator, can realize that promptly the needed time-delay of electrify restoration circuit Tdelay is m * T1.
3, the delay value Tdelay of the electrify restoration circuit change of can programming by the n bit input control signal Vc of programmable oscillator.
4, in the controlled electrify restoration circuit of low-power consumption time-delay of the present invention, because programmable oscillator and counter are only worked in the supply voltage power up, after the POR_RESET signal becomes high level, programmable oscillator and counter promptly are closed, the programmable oscillator sum counter only consumes power consumption in the power supply electrifying process of electrify restoration circuit, so only there is very little instantaneous power consumption in circuit.
5, the present invention is applicable to the SOC chip of Highgrade integration, without any need for outward element, makes this circuit be fit to the needs of disparity items.
Description of drawings
Fig. 1 is the electrical block diagram of traditional electrify restoration circuit POR;
Fig. 2 is the voltage waveform view of each node among the powered reset circuit POR shown in Figure 1;
Fig. 3 is the electrical block diagram of the controlled electrify restoration circuit POR of low-power consumption time-delay of the present invention;
Fig. 4 is a kind of particular circuit configurations figure of the controlled electrify restoration circuit POR of low-power consumption time-delay of the present invention;
Fig. 5 is the voltage waveform view of each node among the controlled electrify restoration circuit POR of low-power consumption shown in Figure 4 time-delay.
Embodiment
The electrification reset method that low-power consumption of the present invention time-delay is controlled may further comprise the steps: 1] control end Vc by the input of n bit programmes to the period T 1 that programmable oscillator produces pulse waveform signal; 2] programmable oscillator produces pulse waveform signal and gives counter; 3] when supply voltage is higher than threshold value, counter begins the pulse waveform signal that programmable oscillator produces is counted; 4] after the count value of counter reaches set point, counter output becomes logic high by logic low; 5] output signal of counter is had the output of latching with the output buffer of Protection Counter Functions and become logic high as power-on reset signal by logic low; 6] close the programmable oscillator sum counter with the logic high of output buffer output.
The concrete structure block diagram of the electrify restoration circuit that low-power consumption time-delay of the present invention is controlled comprises: voltage detecting circuit, programmable oscillator, counter, logical circuits such as output buffer and inverter as shown in Figure 3.Wherein, the input termination supply voltage VDD of voltage detecting circuit, earth terminal ground connection, output V_det meets the Enable Pin EN_CNT of counter circuit, is used for controlling the work of output buffer simultaneously; Programmable oscillator has the input control end Vc of n bit, and the cycle of the pulse waveform signal that programmable oscillator produces can programme by input control end Vc, and the output Freq_out of programmable oscillator connects the input of counter circuit; The count value of counter is m, and when the input pulse waveform signal is m all after dates, the output signal of counter becomes logic high by logic low, and the output V_ctrl of counter connects output buffer; The input of output buffer is the output V_ctrl of counter and the output V_det of voltage detecting circuit, output is the output POR_RESET of electrify restoration circuit POR, and POR_RESET meets the Enable Pin EN_OSC of pierce circuit after by inverter.
Wherein output buffer generally adopts the logical circuit that can realize latching with Protection Counter Functions, and such as latch, trigger etc. especially can adopt d type flip flop.
Output buffer adopts the physical circuit of d type flip flop referring to Fig. 4.The signal input part D of d type flip flop circuit meets supply voltage VDD, input end of clock CLK meets the output V_ctrl of counter, zero clearing input Reset meets the output V_det of voltage detecting circuit through the signal behind the inverter, the output Q of d type flip flop is the output POR_RESET of electrify restoration circuit, and the output POR_RESET of electrify restoration circuit meets the Enable Pin EN_OSC of programmable oscillator behind inverter simultaneously; When the clock input signal CLK of d type flip flop ran into the rising edge of input signal, its output valve Q became with its input value D and equates; As reset signal Reset during by low uprising, its output valve Q is cleared to low level.
The delay time operation principle of controlled electrify restoration circuit of the present invention is:
Referring to Fig. 5, in the supply voltage VDD power up, voltage detecting circuit and programmable oscillator are started working, after supply voltage VDD is higher than detection voltage VDET1 (threshold value of voltage detecting circuit), the output point V_det of voltage detecting circuit becomes logic high by logic low, and counter is started working; By the Vc end is that the pulse waveform signal of T1 is counted to counter in the programmed settings programmable oscillator output cycle, counter begins counting according to the pulse waveform signal of input, after count value reaches the counter set point, the output of counter becomes logic-high signal by logic low, by the d type flip flop circuit, make output signal POR_RESET become logic-high signal, the logic high of POR_RESET will be closed programmable oscillator simultaneously, make it no longer to work, because POR_RESET is latched by d type flip flop, therefore still can keep high level.Programmable oscillator sum counter circuit is only worked in the power supply electrifying process, and when the end that powers on, after electrify restoration circuit output became logic-high signal by logic-low signal, programmable oscillator sum counter circuit quit work.The programmable oscillator sum counter only consumes power consumption in the power supply electrifying process of electrify restoration circuit.
As shown in Figure 5, after electrify restoration circuit por circuit input voltage is higher than detection voltage VDET1, Tdelay is after the time in time-delay, the output signal POR_RESET of circuit becomes logic high by logic low, the value of time-delay Tdelay is determined by the setting count value that programmable oscillator produces the frequency sum counter of impulse waveform, the cycle of supposing to set by Vc the output pulse waveform signal of programmable oscillator is T1, the count value of counter is m, then the time-delay Tdelay of electrify restoration circuit is m * T1, and time-delay Tdelay can programme by T1 cycle of oscillation that changes programmable oscillator.Under the situation about needing, can be easy to realize bigger (greater than a ms level) time-delay.
When supply voltage descends, when supply voltage VDD drops to the low pressure detection voltage VDET2 (threshold value of voltage detecting circuit) that is lower than voltage detecting circuit, V_det becomes logic low by logic high, by the clear terminal of d type flip flop, the output point POR_RESET of electrify restoration circuit becomes logic low.
Claims (4)
1. the controlled electrification reset method of low-power consumption time-delay is characterized in that: may further comprise the steps:
1] the control end Vc by the input of n bit programmes to the period T 1 that programmable oscillator produces pulse waveform signal;
2] programmable oscillator produces pulse waveform signal and gives counter;
3] when supply voltage is higher than threshold value, counter begins the pulse waveform signal that programmable oscillator produces is counted;
4] after the count value of counter reaches set point, counter output becomes logic high by logic low;
5] output signal of counter is had the output of latching with the output buffer of Protection Counter Functions and become logic high as power-on reset signal by logic low;
6] close the programmable oscillator sum counter with the logic high of output buffer output.
2. the controlled electrify restoration circuit of low-power consumption time-delay comprises voltage detecting circuit and output buffer; The input termination supply voltage (VDD) of described voltage detecting circuit, earth terminal ground connection;
It is characterized in that: also comprise the programmable oscillator of the pulse waveform signal that is used to export some cycles, counter and the inverter that count value is m;
The output of voltage detecting circuit (V_det) connects the Enable Pin (EN_CNT) of counter, connects the control input end of output buffer simultaneously, is used for controlling the work of output buffer;
Programmable oscillator has a control end (Vc) that the n bit of programming the cycle of oscillation of output signal is imported, the output of programmable oscillator (Freq_out) connects the input of counter, and the Enable Pin of programmable oscillator (EN_OSC) connects the signal of output (POR_RESET) behind inverter of output buffer;
The output of counter (V_ctrl) connects the input of output buffer.
3. the controlled electrify restoration circuit of low-power consumption time-delay according to claim 2, it is characterized in that: described output buffer is flip-flop circuit or the latch circuit that can realize latch function.
4. the controlled electrify restoration circuit of low-power consumption time-delay according to claim 3, it is characterized in that: described output buffer is the d type flip flop circuit;
The signal input part of d type flip flop circuit (D) connects supply voltage (VDD);
The reset terminal (Reset) of the output of voltage detecting circuit (V_det) by connecing the d type flip flop circuit behind the inverter;
D type flip flop circuit output end (Q) connects the Enable Pin (EN_OSC) of programmable oscillator behind inverter;
The output of counter (V_ctrl) connects the input end of clock (CLK) of d type flip flop circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010612344 CN102055449A (en) | 2010-12-29 | 2010-12-29 | Low power-consumption time-delay controllable POR (power on reset) method and circuit |
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| CN 201010612344 CN102055449A (en) | 2010-12-29 | 2010-12-29 | Low power-consumption time-delay controllable POR (power on reset) method and circuit |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857222A (en) * | 2012-07-03 | 2013-01-02 | 山东华芯半导体有限公司 | Method and circuit for dynamic regulation of system clock |
| WO2013060137A1 (en) * | 2011-10-24 | 2013-05-02 | 中兴通讯股份有限公司 | Apparatus for controlling power-on sequence of multiple power supplies |
| CN107422824A (en) * | 2017-04-14 | 2017-12-01 | 广东浪潮大数据研究有限公司 | Power-on reset system and method |
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
| CN108347244A (en) * | 2017-12-06 | 2018-07-31 | 西安智多晶微电子有限公司 | Multi-mode POR circuit for FPGA |
| CN109917887A (en) * | 2019-03-06 | 2019-06-21 | 深圳芯马科技有限公司 | A kind of digital reset circuit applied to MCU chip |
| CN111753487A (en) * | 2020-07-01 | 2020-10-09 | 无锡中微亿芯有限公司 | FPGA device with power-on reset signal waveform adjustable function |
| CN112165320A (en) * | 2020-09-28 | 2021-01-01 | 上海磐启微电子有限公司 | Low-power-consumption digital power-on reset circuit and integrated circuit chip |
| CN112996183A (en) * | 2021-04-08 | 2021-06-18 | 东莞市华彩威科技有限公司 | LED control IC single-wire cascade data communication method |
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| JP2004260648A (en) * | 2003-02-27 | 2004-09-16 | Nec Corp | Power-on reset circuit |
| US20060066367A1 (en) * | 2004-09-30 | 2006-03-30 | Broadcom Corporation | Method and system for providing a power-on reset pulse |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013060137A1 (en) * | 2011-10-24 | 2013-05-02 | 中兴通讯股份有限公司 | Apparatus for controlling power-on sequence of multiple power supplies |
| CN102857222B (en) * | 2012-07-03 | 2015-09-16 | 山东华芯半导体有限公司 | A kind of dynamic adjusting method of system clock and circuit |
| CN102857222A (en) * | 2012-07-03 | 2013-01-02 | 山东华芯半导体有限公司 | Method and circuit for dynamic regulation of system clock |
| CN107422824A (en) * | 2017-04-14 | 2017-12-01 | 广东浪潮大数据研究有限公司 | Power-on reset system and method |
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
| CN107463236B (en) * | 2017-08-28 | 2023-05-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
| CN108347244B (en) * | 2017-12-06 | 2021-09-21 | 西安智多晶微电子有限公司 | Multi-mode POR circuit for FPGA |
| CN108347244A (en) * | 2017-12-06 | 2018-07-31 | 西安智多晶微电子有限公司 | Multi-mode POR circuit for FPGA |
| CN109917887A (en) * | 2019-03-06 | 2019-06-21 | 深圳芯马科技有限公司 | A kind of digital reset circuit applied to MCU chip |
| CN111753487A (en) * | 2020-07-01 | 2020-10-09 | 无锡中微亿芯有限公司 | FPGA device with power-on reset signal waveform adjustable function |
| CN112165320A (en) * | 2020-09-28 | 2021-01-01 | 上海磐启微电子有限公司 | Low-power-consumption digital power-on reset circuit and integrated circuit chip |
| CN112996183A (en) * | 2021-04-08 | 2021-06-18 | 东莞市华彩威科技有限公司 | LED control IC single-wire cascade data communication method |
| CN112996183B (en) * | 2021-04-08 | 2023-03-24 | 东莞市华彩威科技有限公司 | LED control IC single-wire cascade data communication method |
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Application publication date: 20110511 |