JP2004260648A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of surely performing an initial operation without depending on voltage rising characteristics, etc. of a power source. <P>SOLUTION: A power supply voltage Vcc of the power source 12 is inputted via an RC time constant circuit with a small time constant, the voltage is detected by a voltage detector 15, and a counter 16 and an R-S flip-flop 17 are controlled by the output of the voltage detector 15. An IC 11 is initialized and a counting operation of the counter 16 is controlled by the output of the flip-flop 17. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reset circuit, and more particularly, to a power-on reset circuit that initializes (initializes) an internal state at the time of power-on (power application) of an electronic circuit or an IC (hereinafter, referred to as IC or the like).
[0002]
[Prior art]
Many of recent electronic devices or electronic application devices are configured by digital circuits (or devices) such as flip-flops, counters, registers, and microprocessors, or circuits in which such digital circuits and analog circuits are mixed. Further, such a circuit is generally constituted by one or a plurality of ICs (semiconductor integrated circuits) for reducing the size and weight and increasing the reliability. Such an IC is mounted on a circuit board, supplies power, and connects input / output signals to perform a predetermined operation or function.
[0003]
The states of flip-flops, registers, counters, and the like inside such an IC are generally given an initial state predetermined by, for example, a register, and in the subsequent operation process, the internal state is changed according to a change in a register value or an input signal. Let it. However, at the time of power-on, the internal state is undefined, and there is a possibility that an expected operation cannot be obtained or a problem affecting the outside may occur. Therefore, at power-on, a power-on reset that generates a reset signal and forcibly initializes registers and the like is generally performed to determine the state until the internal state is determined by a register or an input signal. Is being done.
[0004]
Various techniques have been proposed as such a power-on reset circuit. In order to minimize the increase in the LSI chip area and obtain a sufficiently long reset period, a one-shot pulse generation means, a flip-flop reset by the one-shot pulse, and a power supply constituted by a timer connected to its output side An on-reset system and a semiconductor memory device using the same are disclosed (for example, refer to Patent Document 1). Further, there is disclosed a reset circuit including a detection circuit that detects a rise of a power supply, a clock circuit that operates in response to the output of the detection circuit, and a counter circuit (for example, see Patent Document 2). Further, a power-on reset circuit that generates a reset signal using a power supply voltage monitoring circuit is disclosed (for example, see Patent Document 3).
[0005]
Next, a general conventional power-on reset circuit will be described with reference to FIGS. FIG. 5A is an example of a power-on reset circuit 50A in a case where the IC 51 operates by being supplied with a power supply voltage from a built-in battery 52. FIG. 5B is an explanatory diagram of the operation of the power reset circuit 50A. The power reset circuit 50A supplies the voltage of the built-in battery 52 to the power terminal of the IC 51 via the power switch 53, and outputs the output voltage of the time constant circuit of the resistor R and the capacitor C connected in series to the reset terminal of the IC 51. Is applied.
[0006]
According to the power-on reset circuit 50A, the power supply voltage Vcc supplied to the power supply terminal of the IC 51 is the same as that when the power switch 53 is turned on (or closed) as shown in the upper part of FIG. A fixed voltage determined by the voltage of the internal battery 52 is applied to T0). However, since the capacitor C of the time constant circuit is charged via the resistor R, the time constant determined by the product of the capacitance of the capacitor C and the resistance value of the resistor R as shown in the lower part of FIG. And rise gradually. Then, at time T1 when the charging voltage of the capacitor C reaches a predetermined threshold, the IC 51 is reset. Therefore, the IC 51 is in the reset state between the time points T0 and T1, and becomes active after the time point T1.
[0007]
FIG. 6 shows another example of the conventional power-on reset circuit. FIG. 6A is a circuit diagram of the power-on reset circuit 50B, and FIG. 6B is an operation explanatory diagram thereof. In the power-on reset circuit 50B, the IC 51 operates by obtaining a predetermined power supply voltage by a regulator (or switching regulator) 54 connected to a built-in battery 52 via a power switch 53. Further, a capacitor C for smoothing the output voltage of the regulator 54 is connected, and a voltage detector (detector) 55 for detecting the voltage of the capacitor C is provided.
[0008]
The voltage of the regulator 54 or the capacitor C gradually increases as shown in FIG. When this voltage becomes a predetermined voltage, the voltage detector 55 outputs a reset signal to the IC 51 and resets it. That is, the IC 51 is in a non-operating state from the time T0 when the power switch 53 is turned on to the time T1 when the output voltage of the regulator 54 reaches the predetermined first voltage, and the output voltage of the regulator 54 becomes the second voltage from this time T1. Until time T2, the IC 51 is in a reset state, and after this time T2, the IC 51 is in an operating state.
[0009]
[Patent Document 1]
JP-A-5-291915 (page 4, FIG. 1)
[Patent Document 2]
JP-A-2-291008 (page 2, FIG. 1)
[Patent Document 3]
JP-A-2000-172381 (pages 2-3, FIG. 1)
[0010]
[Problems to be solved by the invention]
As described above, when the conventional power-on reset circuit resets the IC using the CR time constant circuit or the voltage detector, a correct reset signal is not generated due to the rising speed of the power supply voltage, and the reset operation is not performed. There is a problem of becoming stable. That is, when the RC time constant circuit is used, if the rise of the power supply voltage is slow, an unstable state may occur between the reset state and the operating state as shown in FIG. On the other hand, when the voltage detector is used, when the power supply voltage rises rapidly, a reset state having a sufficient length is obtained as shown in FIG. 8, although a reset period of at least 100 ns is generally required. And the IC 51 is not reset normally.
[0011]
[Object of the invention]
SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems of the related art, and has as its object to provide a power-on reset circuit that can securely initialize an IC.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the power-on reset circuit according to the present invention employs the following characteristic configuration.
[0013]
(1) In a power-on reset circuit for performing initialization when a power supply for driving an IC or the like is turned on,
A voltage detector for detecting the voltage of the power supply; a counter and a flip-flop operation-controlled by the output of the voltage detector; the output of the flip-flop initializes the IC and the like and counts the counter Power-on reset circuit that controls operation.
[0014]
(2) The power-on reset circuit according to (1), wherein the counter counts a clock output of an internal clock oscillator enabled by an output of the flip-flop.
[0015]
(3) The power-on reset circuit according to (1), wherein a clock externally supplied to the IC or the like is supplied to the counter via a gate.
[0016]
(4) The power-on reset circuit according to (1), (2) or (3), wherein the power supply voltage is input to the voltage detector via a time constant circuit having a small time constant.
[0017]
(5) The flip-flop is an RS flip-flop in which an output of the voltage detector is supplied to a set terminal and an output from the counter is supplied to a reset terminal. Power-on reset circuit.
[0018]
(6) The power-on reset circuit according to (5), wherein one output of the RS flip-flop is supplied to the IC or the like, and the other output controls supply of the clock to the counter.
[0019]
(7) The voltage detector sets the RS flip-flop when the input voltage exceeds a first threshold, and latches the set operation of the RS flip-flop when the input voltage exceeds a second threshold. Or the power-on reset circuit of (6).
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the configuration and operation of a preferred embodiment of a power-on reset circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0020]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a power-on reset circuit according to the present invention. The power-on reset circuit 10 includes a voltage detector 15, a counter 16, an RS (set / reset) flip-flop 17, an oscillator 18, and a resistor R and a capacitor C forming a time constant circuit having a small time constant (RC). You.
[0021]
The voltage from the power supply 12 is applied to the RC time constant circuit and the power supply terminal Vcc of the IC 11 via the power switch 13. The voltage of the capacitor C charged in a short time via the resistor R is input to the voltage detector 15. The output (A) of the voltage detector 15 is input to the reset terminal of the counter 16 and the set terminal S of the RS flip-flop 17. On the other hand, the output (CY) of the counter 16 is input to the reset terminal R of the SR flip-flop 17. The Q output (B) of the RS flip-flop 17 is input to the enable terminal of the oscillator 18, and the oscillation output (D) of the oscillator 18 is input to the clock terminal of the counter 16. Then, the / Q (that is, inverted Q) output (C) of the SR flip-flop 17 is input to the reset terminal R of the IC 11.
[0022]
Next, the operation of the power-on reset circuit 10 shown in FIG. 1 will be described with reference to the operation explanatory diagrams of FIGS. First, a case will be described with reference to FIG. 2 where the power supply switch 13 is turned on to gradually increase the power supply voltage Vcc, which is the output of the power supply 12 constituted by a regulator, for example. 2, (a) is the power supply voltage Vcc, (b) is the output A of the voltage detector 15, (c) is the Q output B of the RS flip-flop 17, and (d) is the output of the RS flip-flop 17. The / Q output C, (e) is the clock output D of the oscillator 18 and (f) is the output (carry) CY of the counter 16.
[0023]
As shown in FIG. 2A, the power supply voltage Vcc gradually increases and is applied to the power supply terminal of the IC 11. However, since the voltage is extremely low initially, the IC 11 remains inactive. The output of the voltage detector (detector) 15 is also undefined as shown in FIG. The RC time constant circuit on the input side of the voltage detector 15 hardly functions because the time constant is small (one or both of the resistance value of the resistor R and the capacitance of the capacitor C are small).
[0024]
Next, when the power supply voltage Vcc exceeds the first threshold value Vth1, the voltage detector 15 starts operating and outputs H (high level). At this time, there is no guarantee that the next stage RS flip-flop 17 is still operating. However, as the power supply voltage Vcc increases, the RS flip-flop 17 starts operating and is set. That is, the Q output B of the RS flip-flop 17 becomes H and the / Q output C becomes L (low level) (see FIGS. 2C and 2D). At this moment, the reset operation to the IC 11 is started. Also, the enable signal to the oscillator 18 becomes H by the Q output of the RS flip-flop 17, so that the oscillator 18 starts operating (see FIG. 2E).
[0025]
When the power supply voltage Vcc exceeds the second threshold value Vth2, the voltage detector 15 outputs L. At this time, the next stage RS flip-flop 17 keeps latching the set operation. Further, since the reset of the counter 16 is released, the counter 16 starts counting (counting operation). Then, the counter 16 outputs the carry signal CY to the RS flip-flop 17 after a desired time (determined by the frequency of the oscillator 18 and the count number) (see FIG. 2F). As a result, the reset operation for the IC 11 is released, and the normal operation becomes possible. The enable signal to the oscillator 18 (see FIG. 2C) is also disabled, and the operation of the oscillator 18 stops. Thus, power consumption is reduced.
[0026]
Next, the operation when the power supply voltage Vcc of the power supply 12 rises sharply and is applied will be described with reference to the operation explanatory diagram of FIG. In FIG. 3, (a) is the power supply voltage, (b) is the voltage input to the voltage detector 15 via the RC time constant circuit, and (c) is the output A of the voltage detector 15, (d) and (d). e) is the Q output B and / Q output C of the RS flip-flop 17, (f) is the clock output D of the oscillator 18 and (g) is the carry output CY of the counter 16.
[0027]
As shown in FIG. 3B, the voltage input to the voltage detector 15 rises with a delay slightly from the power supply voltage Vcc by the RC time constant circuit. That is, in the case of FIG. 2 described above, the indefinite period and the set period of the RS flip-flop 17 are extremely short. However, the operation thereafter is exactly the same as in the case described above.
[0028]
With the configuration of the power-on reset circuit 10 according to the present invention described above, the IC 11 and the like can be reliably reset regardless of whether the power supply voltage Vcc of the power supply 12 rises gradually or steeply. In addition, since a capacitor C having a large capacitance is not required, it is suitable for use in an IC.
[0029]
Next, a second embodiment of the power-on reset circuit according to the present invention will be described with reference to FIG. FIG. 4 shows a part of a second embodiment of the power-on reset circuit according to the present invention, which is different from the first embodiment. In the second embodiment, an oscillator (not shown) is used as an external input, and a clock supplied from the outside is used, and the clock is supplied to the counter 16 through the gate 20. That is, the enable signal is input to the gate 20 from the RS flip-flop 17, and the clock input is input to the counter 16. The operation is similar to the operation of the first embodiment described above. The second embodiment is suitable for a configuration in which a clock is externally supplied to the IC 11.
[0030]
The configuration and operation of the embodiment of the power-on reset circuit according to the present invention have been described above in detail. However, it should be noted that such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention.
[0031]
【The invention's effect】
As apparent from the above description, the power-on reset circuit according to the present invention has the following practically significant effects. The reset or initialization can be reliably performed without depending on the type or characteristics of the power supply to be used (that is, the rising characteristic of the power supply voltage). Therefore, the versatility of an IC or the like can be improved. Further, the reset time can be changed and selected and set to an optimum value by the clock of the counter and the oscillator. Since a large time constant circuit is not required, it is possible to make an IC and reduce the size. Further, an internal or external clock can be appropriately selected and used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a power-on reset circuit according to the present invention.
FIG. 2 is an operation explanatory diagram in a first case of the power-on reset circuit shown in FIG. 1;
FIG. 3 is an operation explanatory diagram of the power-on reset circuit shown in FIG. 1 in a second case.
FIG. 4 is a configuration diagram of a main part of a second embodiment of the power-on reset circuit according to the present invention.
5A and 5B show a first example of a conventional power-on reset circuit, where FIG. 5A is a circuit configuration diagram and FIG. 5B is an operation explanatory diagram.
6A and 6B show a second example of a conventional power-on reset circuit, where FIG. 6A is a circuit configuration diagram and FIG. 6B is an operation explanatory diagram.
FIG. 7 is a diagram illustrating a problem of a conventional power-on reset circuit.
FIG. 8 is a diagram illustrating a problem of a conventional power-on reset circuit.
[Explanation of symbols]
10 Power-on reset circuit 11 IC
12 Power supply 13 Power switch 15 Voltage detector 16 Counter 17 Flip-flop 18 Oscillator (clock generator)
20 gates

Claims (7)

In a power-on reset circuit that performs initialization when a power supply for driving an IC or the like is turned on,
A voltage detector for detecting the voltage of the power supply; a counter and a flip-flop operation-controlled by the output of the voltage detector; the output of the flip-flop initializes the IC and the like and counts the counter A power-on reset circuit for controlling operation. The power-on reset circuit according to claim 1, wherein the counter counts a clock output of an internal clock oscillator enabled by an output of the flip-flop. 2. The power-on reset circuit according to claim 1, wherein a clock externally supplied to the IC or the like is supplied to the counter via a gate. 4. The power-on reset circuit according to claim 1, wherein the power supply voltage is input to the voltage detector via a time constant circuit having a small time constant. 5. 5. The flip-flop according to claim 1, wherein an output of the voltage detector is supplied to a set terminal, and an output from the counter is supplied to a reset terminal. 3. The power-on reset circuit according to claim 1. The power-on reset circuit according to claim 5, wherein one output of the RS flip-flop is supplied to the IC or the like, and the other output controls supply of the clock to the counter. 2. The voltage detector according to claim 1, wherein when the input voltage exceeds a first threshold, the RS flip-flop is set, and when the input voltage exceeds a second threshold, the RS flip-flop is set. 7. The power-on reset circuit according to 5 or 6.

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