CN107463236B - Reset detection circuit and reset detection method - Google Patents
Reset detection circuit and reset detection method Download PDFInfo
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- CN107463236B CN107463236B CN201710752467.5A CN201710752467A CN107463236B CN 107463236 B CN107463236 B CN 107463236B CN 201710752467 A CN201710752467 A CN 201710752467A CN 107463236 B CN107463236 B CN 107463236B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a reset detection circuit and a reset detection method.A reset request input circuit receives a low-level effective reset request input by a reset pin and outputs the reset request; the latch circuit generates a turn-on control signal or a turn-off control signal of the clock circuit through a second inverter according to the reset request output by the reset request input circuit; the clock circuit generates a clock signal according to the on control signal or turns off the clock signal according to the off control signal; the synchronous evacuation circuit controls the M-bit counter to start working according to the reset request output by the reset request input circuit through the first inverter; the M-bit counter has an operation duration of at least 2 M After a clock period, a reset valid signal is output. By adopting the technical scheme, the stability of reset detection is improved.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a reset detection circuit and a reset detection method.
Background
In the power-on process or reset stage of an electronic product based on an IC (Integrated Circuit ), in order to better control the state of the IC and prevent false triggering or false operation of a CPU (Central Processing Unit, a central processing unit) or other IP (Intellectual Property, a kernel) module, an accurate and reliable reset detection circuit needs to be designed. In general, a reset pin is required on an IC, and the function of the reset pin is to enable effective reset to occur under the condition of no power failure when the IC is suspended, so that the IC is restarted. The existing reset detection circuit is sometimes easy to generate false triggering when being subjected to external electromagnetic interference, so that the IC is abnormal in operation.
It can be seen that the existing reset detection circuit or method has at least the following technical problems: when detecting the reset signal, false triggering is easy to generate, so that the working stability of the IC is reduced due to external electromagnetic interference.
Disclosure of Invention
The embodiment of the invention provides a reset detection circuit and a reset detection method, which are used for solving the technical problem that in the prior art, false triggering is easy to generate when a reset signal is detected, so that the working stability of an IC (integrated circuit) is reduced due to external electromagnetic interference.
In a first aspect, an embodiment of the present invention provides a reset detection circuit, including:
a reset request input circuit, a latch circuit, a clock circuit, a synchronous evacuation circuit, an M-bit counter, a first inverter, and a second inverter;
the output end of the latch circuit is connected with the first control end of the clock circuit through a second inverter, and the output end of the clock circuit is respectively connected with the clock signal input end of the synchronous evacuation circuit and the clock signal input end of the M-bit counter, and the synchronous evacuation circuit is connected with the reset end of the M-bit counter;
the reset request input circuit is used for receiving the low-level effective reset request input by the reset pin and outputting the reset request, the latch circuit is used for generating a turn-on control signal or a turn-off control signal of the clock circuit according to the reset request output by the reset request input circuit, the clock circuit is used for generating the clock signal according to the turn-on control signal or turning off the clock signal according to the turn-off control signal, the synchronous evacuation circuit is used for controlling the M-bit counter to start working according to the reset request output by the reset request input circuit, and the working duration of the M-bit counter at least passes through 2 M After a clock period, a reset valid signal is output.
Optionally, the output end of the M-bit counter is connected to the second control end of the clock circuit, and when the M-bit counter outputs a reset valid signal, the clock circuit turns off the clock signal based on the reset valid signal.
Optionally, the output end of the M-bit counter is connected to the second input end of the latch circuit, and when the reset request output by the reset request input circuit is evacuated before the output end of the M-bit counter is not set, the latch circuit outputs a high-level signal, so as to control the clock circuit to turn off the clock signal.
Optionally, the reset request input circuit includes an enable end, an input end, an output end, a first not gate and an or gate, the input end of the reset request input circuit is connected with the first input end of the or gate, the enable end of the reset request input circuit is connected with the second input end of the or gate through the first not gate, and the output end of the or gate is the output end of the reset request circuit;
when the enabling end is at a high level, a reset function of a reset pin connected with the input end of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective.
Alternatively, when the enable terminal is at a low level, the reset function of the reset pin is disabled, and the reset pin is used as a GPIO (General Purpose Input Output, general purpose input/output) pin.
Optionally, the latch circuit is specifically an SR latch formed by a second not gate, a third not gate and two nand gates;
the first input end of the latch circuit is the R end of the SR latch;
the second input end of the latch circuit is the S end of the SR latch;
the output end of the latch circuit is the Q end of the SR latch.
Optionally, the clock circuit includes a first clock module and a second clock module, and an output end of the first clock module is connected with an input end of the second clock module;
the first control end of the clock circuit is an enabling end of the first clock module, the second control end of the clock circuit is an enabling end of the second clock module, and the output end of the clock circuit is an output end of the second clock module.
Optionally, the synchronous evacuation circuit includes two first D flip-flops and a second D flip-flop connected in sequence;
the output end of the clock circuit is respectively connected with the clock signal input end of the first D trigger and the clock signal input end of the second D trigger;
the Q end of the first D trigger is connected with the D end of the second D trigger, and the output end of the synchronous evacuation circuit is the output end of the second D trigger.
Optionally, the M-bit counter is an M-bit ripple counter, and the M-bit ripple counter is an asynchronous M-bit binary addition counter formed by D flip-flops.
In a second aspect, an embodiment of the present invention provides a reset detection method applied to a reset detection circuit including a reset request input circuit, a latch circuit, a clock circuit, a synchronous evacuation circuit, and an M-bit counter, the method including:
the reset request input circuit receives a low-level effective reset request input by a reset pin and outputs the reset request;
the latch circuit generates a turn-on control signal or a turn-off control signal of the clock circuit through a second inverter according to the reset request output by the reset request input circuit;
the clock circuit generates a clock signal according to the on control signal or turns off the clock signal according to the off control signal;
the synchronous evacuation circuit controls the M-bit counter to start working according to the reset request output by the reset request input circuit through the first inverter;
the M-bit counter has an operation duration of at least 2 M After a clock period, a reset valid signal is output.
Optionally, the output of the M-bit counter is connected to the clock circuit, and the clock circuit turns off the clock signal when the M-bit counter outputs a reset valid signal.
Optionally, the output end of the M-bit counter is connected to the second input end of the latch circuit, and when the reset request output by the reset request input circuit is evacuated before the output end of the M-bit counter is not set, the latch circuit outputs a high-level signal, so as to control the clock circuit to turn off the clock signal.
Optionally, the reset request input circuit includes an enable end, an input end, an output end, a first not gate and an or gate, the input end of the reset request input circuit is connected with the first input end of the or gate, the enable end of the reset request input circuit is connected with the second input end of the or gate through the first not gate, and the output end of the or gate is the output end of the reset request circuit;
when the enabling end is at a high level, a reset function of a reset pin connected with the input end of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective.
Optionally, when the enable terminal is at a low level, the reset function of the reset pin is invalid, and the reset pin is used as a GPIO pin.
One or more technical solutions provided in the embodiments of the present invention at least have the following technical effects or advantages:
by adopting the technical scheme in the embodiment of the invention, the external electromagnetic interference can be effectively filtered, the reliability of the reset detection circuit is improved, the energy consumption of the reset detection circuit is reduced, and the reset pin can be reused, namely the reset pin can be used as GPIO.
Drawings
FIG. 1A is a first schematic diagram of a reset detection circuit according to an embodiment of the present invention;
FIG. 1B is a second schematic diagram of the reset detection circuit according to the embodiment of the present invention;
FIG. 2A is a schematic diagram of a reset request input circuit according to an embodiment of the present invention;
FIG. 2B is a schematic diagram of a latch circuit according to an embodiment of the present invention;
FIG. 2C is a schematic diagram of a clock circuit according to an embodiment of the present invention;
fig. 2D is a schematic diagram of a synchronous evacuation circuit according to an embodiment of the present invention;
FIG. 2E is a schematic diagram of an M-bit counter according to an embodiment of the present invention;
FIG. 2F is a schematic diagram of a specific logic circuit of the reset detection circuit according to an embodiment of the present invention;
fig. 3 is a flowchart of a reset detection method according to an embodiment of the present invention.
Detailed Description
In order to solve the technical problems, the general idea of the technical scheme in the embodiment of the invention is as follows:
a reset detection circuit and reset detection method, reset detection circuit includes reset request input circuit, latch circuit, clock circuit, synchronous withdraw circuit, M bit counter, first inverter and second inverter;
the output end of the latch circuit is connected with the first control end of the clock circuit through a second inverter, and the output end of the clock circuit is respectively connected with the clock signal input end of the synchronous evacuation circuit and the clock signal input end of the M-bit counter, and the synchronous evacuation circuit is connected with the reset end of the M-bit counter;
the latch circuit is used for generating a turn-on control signal or a turn-off control signal of a clock circuit according to the reset request output by the reset request input circuit, the clock circuit is used for generating a clock signal according to the turn-on control signal or turning off the clock signal according to the turn-off control signal, and the synchronization is realizedThe evacuation circuit is used for controlling the M-bit counter to start working according to the reset request output by the reset request input circuit, and the working duration of the M-bit counter at least passes through 2 M After a clock period, a reset valid signal is output.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
Referring to fig. 1A, a first embodiment of the present invention provides a reset detection circuit, including:
a reset request input circuit 10, a latch circuit 20, a clock circuit 30, a synchronous evacuation circuit 40, an M-bit counter 50, a first inverter 60, and a second inverter 70;
an input terminal of the reset request input circuit 10 is connected to a reset pin (not shown in fig. 1), an output terminal of the reset request input circuit 10 is connected to a first input terminal of the latch circuit 20, an output terminal of the reset request input circuit 10 is connected to a reset terminal of the synchronous evacuation circuit 40 through the first inverter 60, an output terminal of the latch circuit 20 is connected to a first control terminal of the clock circuit 30 through the second inverter 70, an output terminal of the clock circuit 30 is connected to a clock signal input terminal of the synchronous evacuation circuit 40 and a clock signal input terminal of the M-bit counter 50, respectively, and the synchronous evacuation circuit 40 is connected to a reset terminal of the M-bit counter 50;
wherein the reset request input circuit 10 is configured to receive an active low reset request input by the reset pin and output the reset request, the latch circuit 20 is configured to generate an on control signal or an off control signal of the clock circuit 30 according to the reset request output by the reset request input circuit 10, the clock circuit 30 is configured to generate the clock signal according to the on control signal or turn off the clock signal according to the off control signal, the synchronous evacuation circuit 40 is configured to control the M-bit counter to start operating according to the reset request output by the reset request input circuit, and the operation duration of the M-bit counter 50 is at least 2 M After a clock period, a reset valid signal is output.
The reset pin may be a reset pin on the IC chip, and the reset detection circuit may be a detection circuit connected to the reset pin and applied to the inside of the IC chip.
Referring to fig. 1B, in order to further reduce power consumption of the clock, the clock circuit 30 may further have a second control terminal, the output terminal of the M-bit counter 50 is connected to the second control terminal of the clock circuit 30, and when the M-bit counter 50 outputs a reset valid signal, the clock circuit 30 turns off the clock signal according to the reset valid signal;
an output terminal of the M-bit counter 50 is connected to a second input terminal of the latch circuit 20, and when the reset request output from the reset request input circuit is evacuated before the output terminal of the M-bit counter is not set, the latch circuit 20 outputs a high level signal, thereby controlling the clock circuit to turn off the clock signal. In particular, if the duration of the reset request is short, e.g. less than 2 M The two inputs of the latch circuit 20 are both high for a clock cycle, i.e. the reset request is evacuated before the output of the M-bit counter 50 is not set, and the latch circuit 20 outputs a high signal, thereby controlling the clock circuit 30 to turn off the clock signal.
In order to enable the reset pin to have a multiplexing function, for example, the reset pin may be used as a multiplexing GPIO, and the reset request input circuit 10 may adopt the structure used in fig. 2A; of course, if the reset pin is not required to have a multiplexing function, the reset request input circuit may employ only an existing circuit capable of transmitting a reset signal.
Referring to fig. 2A, the reset request input circuit 10 may include an enable terminal pad_en, an input terminal pad_in, an not gate 101, and an or gate 102, the input terminal pad_in of the reset request input circuit is connected to a first input terminal of the or gate 102, the enable terminal pad_en of the reset request input circuit is connected to a second input terminal of the or gate 102 through the first not gate 101, and an output terminal of the or gate 102 is an output terminal vld_in of the reset request circuit;
when the enabling end PAD_EN is at a high level, a reset function of a reset pin connected with the input end PAD_IN of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective;
when the enabling terminal PAD_EN is at a low level, the reset function of the reset pin is invalid, and the reset pin is used as a GPIO pin.
Referring to fig. 2B, for the latch circuit 20, an SR latch may be specifically employed, and specifically, the latch circuit 20 includes an SR latch composed of a second not gate 201, a third not gate 202, and two not gates 203 and 204;
a first input of the latch circuit 20 is connected to the R-terminal of the SR latch through a second not gate 201; a second input of the latch circuit 20 is connected to the S terminal of the SR latch through a third not gate 202; the output of latch circuit 20 is the Q of the SR latch.
Referring to fig. 2C, for clock circuit 30, the clock circuit may be specifically a clock management unit CMU,
the clock circuit 30 includes a first clock module G0 and a second clock module G1, where an output end GCK of the first clock module G0 is connected to an input end GCK of the second clock module G1;
the first control end of the clock circuit 30 is an enable end E of the first clock module G0, the second control end of the clock circuit 30 is an enable end E of the second clock module G1, and the output end GCK of the clock circuit 30 is an output end sm_clk of the second clock module G1.
Referring to fig. 2D, the synchronized evacuation circuit 40 includes two first D flip-flops 401 and a second D flip-flop 402 connected in sequence;
the output end of the clock circuit is respectively connected with the clock signal input end of the first D trigger SYNC0_REG and the clock signal input end of the second D trigger SYNC 1_REG;
the Q terminal of the first D trigger sync0_reg is connected to the D terminal of the second D trigger sync1_reg, and the output terminal pad_syng of the synchronous evacuation circuit is the output terminal of the second D trigger sync1_reg.
For the M-bit counter 50, it may be specifically an M-bit ripple counter, which is an asynchronous M-bit binary addition counter composed of D flip-flops. The number of bits of the ripple counter can be determined by specific IC requirements, so as to determine the filtering length of the reset detection circuit.
Referring to fig. 2E, the specific structure of the M-bit ripple counter includes M D flip-flops, where m=n. Specifically, the input terminal D of each D flip-flop and its output terminal
The input end of the first-stage D trigger is connected with the output end SM_CLK of the clock circuit, and the output end of the first-stage D trigger is +>
Is connected with the input end of the D flip-flop of the subsequent stage, and the output end of the D flip-flop of the last stage is +.>
Is the output pad_rstg of the entire ripple counter.
Referring to fig. 2F, an overall logic circuit diagram of a reset detection circuit according to an embodiment of the present invention is provided. The operation principle of the reset detection circuit will be further described with reference to the circuit diagram.
If PAD_EN is set to 0, then the reset pin may be used as a GPIO pin, and any transition of PAD_IN may not cause VLD_IN to transition from 1 to 0.
If PAD_EN is set to be 1, the GPIO pin is changed into a reset pin, and when no reset request is generated, the reset pin is IN a pull-up state, and VLD_IN is at a high level; it passes through an inverter so that both flip-flops in the synchronous evacuation circuit 40 are in a reset state, and thus its output pad_synj is 0; PAD_SYNJ will put M-bit counter 50 in reset, and therefore its output
At high level, G1 in the clock circuit remains on and no reset occurs; looking again at latch circuit 20, both its S and R terminals are inputThe input is high, SJ and RJ are low after passing through the inverter, so the outputs Q and QN of the two NAND gates are high, wherein the Q output is turned off the clock of the whole circuit through G0 in the clock circuit 30 after passing through the inverter, and G1 is turned on but not SM_CLK.
If PAD_EN is set to 1 and the reset pin has a low level input, the reset detection circuit begins to operate as follows:
first vld_in will jump low;
meanwhile, the R terminal of the latch circuit 20 jumps to a low level, the RJ jumps to a high level, and the QN remains high, so the Q jumps to a low level to be output, and the G0 of the clock circuit 30 is opened through the inverter, and the sm_clk is released; looking again at the synchronous evacuation circuit 40, since vld_in is synchronously evacuated from the reset state by the high-to-low transition, pad_synj causes M-bit counter 50 to be evacuated from the reset state after two sims_clk;
at this time, the clock of the M-bit counter 50 is valid and reset is invalid, and counting is started;
if the low input of the reset pin is for a time sufficient to enable the most significant BIT RPL_BIT [ n-1] of M-BIT counter 50]The Q-terminal count of (2) is high
To low, an active PAD_RSTJ (active low) is issued, while G1 of clock circuit 30 is turned off, SIM_CLK is turned off, M-bit counter 50 stops counting, +.>
Remains low. Taking n=5 as an example, the low level input of the reset pin needs to last at least 32 sim_clk periods to generate a jump from high to low pad_rstj;
if the low level input of the reset pin does not last long enough, vld_in is evacuated before the Q terminal of rpl_bit [ n-1] is not set, then R and S of latch circuit 20 are both high, the Q output thereof will also become high, G0 IN clock circuit 30 will also be turned off, sim_clk will disappear, and synchronous evacuation circuit 40 and M-BIT counter 50 will also be asynchronously reset, the entire reset detection circuit will return to its initial state, and no jump from high to low of pad_rstj will occur IN the entire process;
the evacuation situation after the jump from high to low occurs IN pad_rstj, G1 of clock circuit 30 is turned off, sim_clk is turned off, and compared with the fact that the low level of the reset pin does not last long enough, vld_in is set at the Q terminal of rpl_bit [ n-1] during evacuation (from 0 to 1), and pad_rstj is IN the low level reset active state, which is not described here.
From the above embodiment, it is known that the synchronous evacuation circuit 40 with the clock being the system clock is added above pad_rstj to ensure that the whole system can ensure synchronous evacuation of the reset when the valid asynchronous reset occurs on the reset pin.
Referring to fig. 3, a second embodiment of the present invention provides a reset detection method applied to a reset detection circuit, the reset detection circuit including a reset request input circuit, a latch circuit, a clock circuit, a synchronous evacuation circuit, and an M-bit counter, the method including:
s101, a reset request input circuit receives a low-level effective reset request input by a reset pin and outputs the reset request;
s102, the latch circuit generates a turn-on control signal or a turn-off control signal of the clock circuit through a second inverter according to the reset request output by the reset request input circuit;
s103, the clock circuit generates a clock signal according to the on control signal or turns off the clock signal according to the off control signal;
s104, the synchronous evacuation circuit controls the M-bit counter to start working according to the reset request output by the reset request input circuit through the first inverter;
s105, the M-bit counter operation duration is at least 2 M After a clock period, a reset valid signal is output.
The reset detection circuit applied in the above reset detection method may adopt the circuit configuration in fig. 1A.
Referring still to fig. 1B, to reduce power consumption of the clock, an output of the M-bit counter may be connected to a clock circuit, which turns off the clock signal when the M-bit counter outputs a reset valid signal; the output end of the M-bit counter is connected with the second input end of the latch circuit, when the reset request output by the reset request input circuit is evacuated before the output end of the M-bit counter is not set, the latch circuit outputs a high-level signal, and therefore the clock circuit is controlled to close the clock signal.
In order to enable the reset pin to have a multiplexing function, for example, the reset pin may be used as a multiplexing GPIO, and the reset request input circuit 10 may adopt the structure used in fig. 2A; of course, if the reset pin is not required to have a multiplexing function, the reset request input circuit may employ only an existing circuit capable of transmitting a reset signal.
Still referring to fig. 2A, the reset request input circuit 10 may include an enable terminal pad_en, an input terminal pad_in, an not gate 101, and an or gate 102, where the input terminal pad_in of the reset request input circuit is connected to a first input terminal of the or gate 102, and the enable terminal pad_en of the reset request input circuit is connected to a second input terminal of the or gate 102 through the first not gate 101, and an output terminal of the or gate 102 is an output terminal vld_in of the reset request circuit;
when the enabling end PAD_EN is at a high level, a reset function of a reset pin connected with the input end PAD_IN of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective;
when the enabling terminal PAD_EN is at a low level, the reset function of the reset pin is invalid, and the reset pin is used as a GPIO pin.
For the reset request input circuit, the latch circuit, the clock circuit, the synchronous evacuation circuit and the M-bit counter in the reset detection circuit, the specific structures thereof can be the structures described in the embodiment, and are not described herein.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
by adopting the technical scheme in the embodiment of the invention, the reliability of the reset detection circuit is improved, the energy consumption of the reset detection circuit is reduced, and the reset pin can be reused, namely, the reset pin can be used as GPIO.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (12)
1. A reset detection circuit, comprising:
the synchronous evacuation circuit comprises a first D trigger and a second D trigger which are sequentially connected, wherein the output end of the clock circuit is respectively connected with the clock signal input end of the first D trigger and the clock signal input end of the second D trigger, the Q end of the first D trigger is connected with the D end of the second D trigger, the output end of the synchronous evacuation circuit is the output end of the second D trigger, the M-bit counter is an M-bit ripple counter, and the M-bit ripple counter is an asynchronous M-bit binary addition counter formed by the D triggers;
the output end of the latch circuit is connected with the first control end of the clock circuit through a second inverter, and the output end of the clock circuit is respectively connected with the clock signal input end of the synchronous evacuation circuit and the clock signal input end of the M-bit counter, and the synchronous evacuation circuit is connected with the reset end of the M-bit counter;
the reset request input circuit is used for receiving the low-level effective reset request input by the reset pin and outputting the reset request, the latch circuit is used for generating a turn-on control signal or a turn-off control signal of the clock circuit according to the reset request output by the reset request input circuit, the clock circuit is used for generating the clock signal according to the turn-on control signal or turning off the clock signal according to the turn-off control signal, the synchronous evacuation circuit is used for controlling the M-bit counter to start working according to the reset request output by the reset request input circuit, and the working duration of the M-bit counter at least passes through 2 M After a clock period, a reset valid signal is output.
2. The circuit of claim 1, wherein:
the output end of the M-bit counter is connected with the second control end of the clock circuit, and when the M-bit counter outputs a reset effective signal, the clock circuit turns off the clock signal based on the reset effective signal.
3. The circuit of claim 2, wherein:
the output end of the M-bit counter is connected with the second input end of the latch circuit, when the reset request output by the reset request input circuit is evacuated before the output end of the M-bit counter is not set, the latch circuit outputs a high-level signal, and therefore the clock circuit is controlled to close the clock signal.
4. The circuit of claim 1, wherein:
the reset request input circuit comprises an enabling end, an input end, an output end, a first NOT gate and an OR gate, wherein the input end of the reset request input circuit is connected with the first input end of the OR gate, the enabling end of the reset request input circuit is connected with the second input end of the OR gate through the first NOT gate, and the output end of the OR gate is the output end of the reset request circuit;
when the enabling end is at a high level, a reset function of a reset pin connected with the input end of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective.
5. The circuit as recited in claim 4, wherein:
when the enabling end is in a low level, the reset function of the reset pin is invalid, and the reset pin is used as a GPIO pin.
6. A circuit as claimed in claim 3, wherein:
the latch circuit is specifically an SR latch formed by a second NOT gate, a third NOT gate and two NAND gates;
the first input end of the latch circuit is the R end of the SR latch;
the second input end of the latch circuit is the S end of the SR latch;
the output end of the latch circuit is the Q end of the SR latch.
7. The circuit as recited in claim 6, wherein:
the clock circuit comprises a first clock module and a second clock module, and the output end of the first clock module is connected with the input end of the second clock module;
the first control end of the clock circuit is an enabling end of the first clock module, the second control end of the clock circuit is an enabling end of the second clock module, and the output end of the clock circuit is an output end of the second clock module.
8. A reset detection method applied to the reset detection circuit according to any one of claims 1 to 7, wherein the reset detection circuit includes a reset request input circuit, a latch circuit, a clock circuit, a synchronous evacuation circuit, and an M-bit counter, the method comprising:
the reset request input circuit receives a low-level effective reset request input by a reset pin and outputs the reset request;
the latch circuit generates a turn-on control signal or a turn-off control signal of the clock circuit through a second inverter according to the reset request output by the reset request input circuit;
the clock circuit generates a clock signal according to the on control signal or turns off the clock signal according to the off control signal;
the synchronous evacuation circuit controls the M-bit counter to start working according to the reset request output by the reset request input circuit through the first inverter;
the M-bit counter has an operation duration of at least 2 M After a clock period, a reset valid signal is output.
9. The method as recited in claim 8, wherein:
the output of the M-bit counter is connected with the clock circuit, and when the M-bit counter outputs a reset effective signal, the clock circuit turns off the clock signal.
10. The method of claim 9, wherein:
the output end of the M-bit counter is connected with the second input end of the latch circuit, when the reset request output by the reset request input circuit is evacuated before the output end of the M-bit counter is not set, the latch circuit outputs a high-level signal, and therefore the clock circuit is controlled to close the clock signal.
11. The method as recited in claim 8, wherein:
the reset request input circuit comprises an enabling end, an input end, an output end, a first NOT gate and an OR gate, wherein the input end of the reset request input circuit is connected with the first input end of the OR gate, the enabling end of the reset request input circuit is connected with the second input end of the OR gate through the first NOT gate, and the output end of the OR gate is the output end of the reset request circuit;
when the enabling end is at a high level, a reset function of a reset pin connected with the input end of the reset request input circuit and used for inputting a reset signal to the reset request input circuit is effective.
12. The method of claim 11, wherein:
when the enabling end is in a low level, the reset function of the reset pin is invalid, and the reset pin is used as a GPIO pin.
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| CN109004920B (en) * | 2018-05-29 | 2023-08-15 | 苏州大学 | Novel signal falling edge detection circuit |
| CN109884516B (en) * | 2019-01-29 | 2021-01-12 | 中国科学院微电子研究所 | Asynchronous reset trigger verification circuit and integrated circuit verification device |
| CN110492884B (en) * | 2019-09-11 | 2024-02-13 | 长春思拓电子科技有限责任公司 | Advanced half-ratio prediction electronic system |
| CN111736678B (en) * | 2020-06-12 | 2022-06-10 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
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