CN117435016B - Design method of reset circuit - Google Patents
Design method of reset circuit Download PDFInfo
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- CN117435016B CN117435016B CN202311312619.1A CN202311312619A CN117435016B CN 117435016 B CN117435016 B CN 117435016B CN 202311312619 A CN202311312619 A CN 202311312619A CN 117435016 B CN117435016 B CN 117435016B
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- Prior art keywords
- reset
- register
- rst
- sync
- output
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000013461 design Methods 0.000 title claims abstract description 13
- 230000001360 synchronised effect Effects 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a design method of a reset circuit, which comprises the following steps: s1, when the IP performs reset operation, resetting a source phase through an AND gate, and then outputting a sync_rst after synchronous release; s2, the output end of the register ① is inverted to the output end of the register ③ or is used as a gating signal EN, and the output end of the register ② is used as an output rst_sync of the whole reset circuit; s3, pulling clk_out low when the output of the register ① passes through an inverter as a gating signal, after a certain period, outputting the released rst_sync by the register ②, and opening clk_out immediately after the gating signal output by the register ③; s4, taking clk_out and rst_sync as clock input and reset of the IP. By using the two outputs clk_out and rst_sync of the reset circuit as the reset and clock inputs of the IP block, it is ensured that the block is completely released during operation, and the reliability of the block is ensured, and the release order between the blocks in the chip can be determined by releasing the reset through parameter configuration.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a design method of a reset circuit.
Background
In the current soc chip, synchronous reset and asynchronous reset are generally classified, wherein the synchronous reset is to reset the trigger when waiting for the next clock edge, and the asynchronous reset can be performed without waiting for the clock edge. As SOC integration increases, strict reset timing may need to be maintained between modules, for example, some confidential data needs to be cleared, or data in the modules needs to be protected, and before reset, the data needs to be stored in flash or ram for resetting, and so on.
The reset accuracy is crucial to a chip or a system, the most basic purpose is to enable the chip or the system to enter an initial state for confirming stability, avoid the chip or the system from entering a random state to halt after being electrified, influence the functional accuracy and stability of the whole chip or the system, and the application provides an asynchronous reset circuit and an implementation method thereof, wherein the asynchronous reset circuit is disclosed in China patent CN 100549909C, and an uncertain phase relation between a clock rising edge and a reset signal jump edge is changed into a determined phase relation under the action of two clock cycles through latching of two stages of registers, so that the effect of improving the asynchronous reset reliability is achieved, but the scheme does not provide a method for controlling reset time sequence among all modules of an SOC.
Disclosure of Invention
(One) solving the technical problems
Aiming at the defects of the prior art, the invention provides a design method of a reset circuit, which can be applied to the reset circuit under a complex scene, and the resources occupied by the circuit can be matched according to the configured parameters, so that the design method is applicable to chips with different scales.
(II) technical scheme
In order to achieve the above purpose, the present invention provides the following technical solutions: a design method of a reset circuit comprises the following steps:
S1, when the IP performs reset operation, different reset sources are arranged outside, the reset sources are phase-locked through an AND gate, and then sync_rst is output after synchronous release;
s2, the output end of the register ① is inverted to the output end of the register ③ or is used as a gating signal EN, and the output end of the register ② is used as an output rst_sync of the whole reset circuit;
S3, pulling clk_out low when the output of the register ① passes through an inverter as a gating signal, after a certain period, outputting the released rst_sync by the register ②, and opening clk_out immediately after the gating signal output by the register ③;
S4, clk_out and rst_sync are used as clock input and reset of the IP, and correct inversion of logic level in the module is ensured through clock switching.
Preferably, the reset source in step S1 is a hard reset hw_rst from the top layer or a reset sw_rst from a software configuration.
Preferably, the reset synchronization unit adopted in the step S4 has a definite timing synchronization relationship between the reset signal and the module clock.
(III) beneficial effects
Compared with the prior art, the invention provides a design method of a reset circuit, which has the following beneficial effects:
The design method of the reset circuit ensures that the reset is completely released when the module works by using two outputs clk_out and rst_sync of the reset circuit as reset and clock input of the IP module, thus ensuring the reliability of the module, and the release order among the modules in the chip can be determined by parameter configuration to release the reset, for example, on a communication chip, some packet formats have time sequence requirements, namely, the module can be used for outputting ideal clk and reset.
Drawings
FIG. 1 is an overall block diagram of a reset circuit in the present invention;
FIG. 2 is a flow chart of the operation of the reset circuit of the present invention;
FIG. 3 is a schematic diagram of an asynchronous reset and synchronous release circuit configuration-1 according to the present invention;
FIG. 4 is a schematic diagram of a reset synchronization unit configuration-1.1 according to the present invention;
FIG. 5 is a schematic diagram of a gating clock circuit configuration-3 according to the present invention;
FIG. 6 is a schematic diagram of the delay circuit configuration-2 of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-6, the present invention provides a design method of a reset circuit, which can be applied to a reset circuit under a complex scenario, and the resources occupied by the circuit can be equally allocated according to the configured parameters, and the design method is suitable for chips with different scales, and the whole reset circuit comprises an asynchronous reset synchronous release circuit figure-1, a reset synchronous unit figure-1.1, a delay circuit figure-2 and a Gate circuit Gate figure-3, wherein the asynchronous reset synchronous release circuit figure-1 realizes asynchronous reset synchronous release and the output of the reset synchronous unit figure-1.1 is subjected to beat processing to delay release as required, the delay circuit figure-2 is composed of a plurality of shift registers, the Gate circuit Gate figure-3 is a Gate formed by a latch, and a clock enable signal after the latch and a system clk_in phase are output as the whole circuit.
It should be noted that, the output of the reset synchronization unit is taken as one of the enabling inputs of the clock, clk_en_1, the output of the reset synchronization unit passes through the delay circuit figure-2, the output of the output is taken as the output rst_sync of the whole reset circuit at the position of the register ②, the register ① of the delay circuit outputs clk_en_1 and the last register ③ outputs clk_en as the enabling signal of the gate circuit figure-3, thus ensuring that the time sequence of the clock output is controllable.
Furthermore, the number of registers can be configured according to parameters (dashed lines in the figure), because the D-latch is level triggered, and when clk=1, data flows to Q through the D-latch; when clk=0, Q remains unchanged, so that the glitch caused by the gate signal EN can be eliminated.
The realization flow of the whole circuit is as follows:
S1, when the IP performs reset operation, different reset sources can exist outside, for example, hard reset hw_rst from the top layer, reset sw_rst from software configuration and the like, the reset sources are subjected to AND gate phase, and then sync_rst is output after synchronous release;
S2, the output end of the register ① is inverted to the output end of the register ③ or is used as a gating signal EN, the output end of the register ② is used as an output rst_sync of the whole reset circuit, clk_out is pulled down when the output of the register ① passes through an inverter to be used as a gating signal, after a certain period, the register ② outputs the released rst_sync, and the clk_out is opened next to the gating signal output by the register ③;
S3, clk_out and rst_sync are used as clock input and reset of the IP, correct overturn of logic level in the module is ensured through clock switching, and the adopted reset synchronous unit enables a reset signal and the module clock to have a definite time sequence synchronous relation, so that the problem of metastable state under the asynchronous reset condition is avoided, and the chip has higher reliability.
The two outputs clk_out and rst_sync of the reset circuit must be used as the reset and clock inputs of the IP block in combination, thus ensuring that the block is completely released during operation, thus ensuring reliability of the block, and the release order between the blocks in the chip can be determined by parameter configuration, for example, on the communication chip, some packet formats have time sequence requirements, i.e. the block can be used to output ideal clk and reset.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (3)
1. The design method of the reset circuit is characterized by comprising the following steps:
S1, when the IP performs reset operation, different reset sources are arranged outside, the reset sources are phase-locked through an AND gate, and then sync_rst is output after synchronous release;
s2, the output end of the register ① is inverted to the output end of the register ③ or is used as a gating signal EN, and the output end of the register ② is used as an output rst_sync of the whole reset circuit;
S3, pulling clk_out low when the output of the register ① passes through an inverter as a gating signal, after a certain period, outputting the released rst_sync by the register ②, and opening clk_out immediately after the gating signal output by the register ③;
S4, clk_out and rst_sync are used as clock input and reset of the IP, and correct inversion of logic level in the module is ensured through clock switching.
2. The method according to claim 1, wherein the reset source in step S1 is a hard reset hw_rst from the top layer or a reset sw_rst from a software configuration.
3. The method according to claim 2, wherein the reset synchronization unit adopted in the step S4 makes the reset signal have a definite timing synchronization relationship with the module clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311312619.1A CN117435016B (en) | 2023-10-11 | 2023-10-11 | Design method of reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311312619.1A CN117435016B (en) | 2023-10-11 | 2023-10-11 | Design method of reset circuit |
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| Publication Number | Publication Date |
|---|---|
| CN117435016A CN117435016A (en) | 2024-01-23 |
| CN117435016B true CN117435016B (en) | 2024-04-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311312619.1A Active CN117435016B (en) | 2023-10-11 | 2023-10-11 | Design method of reset circuit |
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| Country | Link |
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| CN (1) | CN117435016B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009080634A (en) * | 2007-09-26 | 2009-04-16 | Victor Co Of Japan Ltd | Reset clock control circuit |
| CN114546083A (en) * | 2020-11-26 | 2022-05-27 | 中移物联网有限公司 | Reset synchronizer circuit and clock gating method thereof |
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2023
- 2023-10-11 CN CN202311312619.1A patent/CN117435016B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009080634A (en) * | 2007-09-26 | 2009-04-16 | Victor Co Of Japan Ltd | Reset clock control circuit |
| CN114546083A (en) * | 2020-11-26 | 2022-05-27 | 中移物联网有限公司 | Reset synchronizer circuit and clock gating method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于片上系统的时钟复位设计;任思伟等;半导体光电;20170415(02);第293-298页 * |
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| CN117435016A (en) | 2024-01-23 |
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