CN114546083A - Reset synchronizer circuit and clock gating method thereof - Google Patents

Reset synchronizer circuit and clock gating method thereof Download PDF

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Publication number
CN114546083A
CN114546083A CN202011344954.6A CN202011344954A CN114546083A CN 114546083 A CN114546083 A CN 114546083A CN 202011344954 A CN202011344954 A CN 202011344954A CN 114546083 A CN114546083 A CN 114546083A
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China
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clock
rst
reset
clk
reset signal
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CN202011344954.6A
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CN114546083B (en
Inventor
马帅
乔文平
肖青
孙东昱
王政宏
刘勇
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China Mobile Communications Group Co Ltd
China Mobile IoT Co Ltd
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China Mobile Communications Group Co Ltd
China Mobile IoT Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a reset synchronizer circuit and a clock gating method thereof, wherein the circuit comprises: the input end of the gating unit inputs an original reset signal rst _ n _ in, a clock signal clk and a synchronous reset signal rst _ n, and the output end of the gating unit outputs a gating clock rst _ n _ clk; the original reset signal rst _ n _ in is asynchronous to a clock signal clk; the reset end of the register inputs rst _ n _ in, and the clock end of the register inputs a gated clock rst _ n _ clk. According to the technical scheme, the clock signal clk of the reset synchronizer is gated by the original reset signal rst _ n _ in and the synchronous reset signal rst _ n, and the generated gated clock rst _ n _ clk only has two clock signal rising edges after reset release, so that the dynamic power consumption of the synchronous register is reduced.

Description

Reset synchronizer circuit and clock gating method thereof
Technical Field
The invention relates to the technical field of integrated circuits and circuit systems, in particular to a reset synchronizer circuit and a clock gating method thereof.
Background
In the prior art, in a circuit for realizing asynchronous reset synchronous release, a register clock is always in an open state when rst _ n is 1, the reset synchronization actually only needs two clock edges after the reset release to be effective, and redundant clock jumps can cause large dynamic power consumption in the register.
Disclosure of Invention
The invention provides a reset synchronizer circuit, which is characterized in that an original reset signal rst _ n _ in and a synchronous reset signal rst _ n are adopted to gate a clock signal clk of a reset synchronizer, and the generated gated clock rst _ n _ clk only has two clock signal rising edges after reset release, so that the dynamic power consumption of a synchronous register is reduced.
In order to solve the above technical problem, an embodiment of the present invention provides the following technical solutions:
a reset synchronizer circuit comprising:
the input end of the gating unit inputs an original reset signal rst _ n _ in, a clock signal clk and a synchronous reset signal rst _ n, and the output end of the gating unit outputs a gating clock rst _ n _ clk; the original reset signal rst _ n _ in is asynchronous to a clock signal clk;
the reset end of the register inputs rst _ n _ in, and the clock end of the register inputs a gated clock rst _ n _ clk.
Optionally, the gate control unit includes a three-input or gate and an inverter;
an original reset signal rst _ n _ in is input to the input end of the inverter;
the output end of the inverter, the clock signal clk and the synchronous reset signal rst _ n are input to the input end of the three-input OR gate, and the output end of the three-input OR gate outputs the gated clock rst _ n _ clk.
Optionally, the register includes a first-level register and a second-level register, and the first-level register is connected to the second-level register.
Optionally, VDD is input to a power input end of the first-stage register, and an output end of the first-stage register outputs a first-stage synchronous reset signal rst _ n _ syn1 of an original reset signal rst _ n _ in.
Optionally, the data input end of the second-stage register inputs a first-stage synchronous reset signal rst _ n _ syn1 of the original reset signal rst _ n _ in, and the output end of the second-stage register outputs the synchronous reset signal rst _ n.
Optionally, the outputting of the three-input or gate as a gated clock outputs a first valid clock edge, including:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at the first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at the high level to obtain a first effective clock edge of the gated clock.
Optionally, the outputting of the three-input or gate as a gated clock outputs a second valid clock edge, including:
at the second clock rising edge, the synchronous reset signal rst _ n changes to high level, the output of the three-input or gate outputs high level as the gated clock rst _ n _ clk, and the second effective clock edge of the gated clock is obtained.
The embodiment of the invention also provides a clock gating method of the reset synchronizer circuit, which is applied to the reset synchronizer circuit and comprises the following steps:
the reset synchronizer circuit three-input OR gate generates gating clocks which are only effective on two clock rising edges after reset release according to an input original reset signal rst _ n _ in, a synchronous reset signal rst _ n and a clock signal clk.
Optionally, generating a gated clock that is valid only on two clock rising edges after the reset release includes:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at the first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at a high level to generate a first effective clock edge of the gated clock.
Optionally, generating a gated clock that is valid only on two clock rising edges after the reset release includes:
at the second clock rising edge, the synchronous reset signal rst _ n changes to high level, the output of the three-input or gate outputs high level as the gated clock rst _ n _ clk, and the second effective clock edge of the gated clock is obtained.
The embodiment of the invention has the following beneficial effects:
according to the technical scheme, the clock signal clk of the reset synchronizer is gated by the original reset signal rst _ n _ in and the synchronous reset signal rst _ n, and the generated gated clock has two clock signal rising edges only after reset release, so that the dynamic power consumption of the synchronous register is reduced.
Drawings
FIG. 1 is a schematic diagram of a reset synchronizer circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a reset synchronizer waveform provided by an embodiment of the present invention;
fig. 3 is a flowchart illustrating a clock timing method of a reset synchronizer according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an embodiment of the present invention provides a reset synchronizer circuit, including:
the input end of the gating unit inputs an original reset signal rst _ n _ in, a clock signal clk and a synchronous reset signal rst _ n, and the output end of the gating unit outputs a gating clock rst _ n _ clk; the original reset signal rst _ n _ in is asynchronous to a clock signal clk;
the reset end of the register inputs rst _ n _ in, and the clock end of the register inputs a gated clock rst _ n _ clk.
According to the embodiment of the invention, the clock signal clk of the reset synchronizer is gated by the original reset signal rst _ n _ in and the synchronous reset signal rst _ n, and the generated gated clock rst _ n _ clk only has two clock signal rising edges after reset release, so that the dynamic power consumption of the synchronous register is reduced.
In an alternative embodiment of the present invention, the gate control unit includes a three-input or gate 300 and an inverter 400;
an original reset signal rst _ n _ in is input to the input end of the inverter 400;
the input end of the three-input or gate 300 inputs the output end of the inverter 400, the clock signal clk and the synchronous reset signal rst _ n, and the output end of the three-input or gate 300 outputs the gated clock rst _ n _ clk.
In this embodiment of the present invention, the valid signal is input through the input terminal of the three-input or gate 300, and the gated clock rst _ n _ clk is output through the output terminal of the three-input or gate 300.
According to an alternative embodiment of the present invention, the register includes a first level register 100 and a second level register 200, and the first level register 100 is connected to the second level register 200.
The first level registers 100 and the second level registers 200 of this embodiment of the invention are set to be synchronous.
In an alternative embodiment of the present invention, VDD is input to the power input terminal of the first stage register 100, and the output terminal of the first stage register 100 outputs the first stage synchronous reset signal rst _ n _ syn1 of the original reset signal rst _ n _ in.
In an alternative embodiment of the present invention, the data input end of the second stage register 200 inputs the first stage synchronous reset signal rst _ n _ syn1 of the original reset signal rst _ n _ in, and the output end of the second stage register 200 outputs the synchronous reset signal rst _ n.
In an alternative embodiment of the present invention, the outputting of the three-input or gate as the first valid clock edge of the gated clock output comprises:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at the first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at the high level to obtain a first effective clock edge of the gated clock.
In an alternative embodiment of the present invention, the outputting of the three-input or gate as the gated clock outputs the second valid clock edge, including:
at the second clock rising edge, the synchronous reset signal rst _ n goes high, and the output of the three-input or gate 300 outputs high as the gated clock rst _ n _ clk, obtaining the second valid clock edge.
Specifically, the above embodiments of the present invention can be implemented by the following implementation manners:
as shown in fig. 2, when the original reset signal rst _ n _ in is 0, the synchronous reset signal rst _ n is also 0 at this time, and the gated clock rst _ n _ clk is fixed to 0;
1) when the original reset signal rst _ n _ in is released to be 1, the gated clock rst _ n _ clk is consistent with the clock signal clk, and at the first clock rising edge, the first stage reset synchronous signal rst _ n _ sync1 becomes 1, thereby generating the first valid clock edge of the gated clock.
2) At the second clock rising edge, the synchronous reset signal rst _ n becomes 1, and at the same time, the synchronous reset signal rst _ n becomes 1, which in turn controls the gated clock rst _ n _ clk to become 1 through the gate control unit, thereby generating a second valid clock edge.
An embodiment of the present invention further provides a clock gating method for a reset synchronizer circuit, which is applied to the reset synchronizer circuit described above, and as shown in fig. 3, the method includes:
step S1: the reset synchronizer circuit three-input or gate 300 generates a gated clock which is only valid on two clock rising edges after reset release according to the input original reset signal rst _ n _ in, the synchronous reset signal rst _ n and the clock signal clk.
In an alternative embodiment of the present invention, in step S1, generating a gated clock that is valid only on two clock rising edges after the release of the reset includes:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at a first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at a high level to generate a first effective clock edge of the gated clock.
In an alternative embodiment of the present invention, in step S1, generating a gated clock that is valid only on two clock rising edges after the release of the reset includes:
at the second clock rising edge, the synchronous reset signal rst _ n goes high, and the output of the three-input or gate 300 outputs high as the gated clock rst _ n _ clk, obtaining the second valid clock edge.
In the above embodiment of the present invention, only two rising edges of the gated clock rst _ n _ clk are valid in the whole process, so that the first-stage register 100 and the second-stage register 200 only have dynamic power consumption at the two rising edges, thereby greatly reducing the dynamic power consumption of the synchronous register compared with the prior art.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A reset synchronizer circuit, comprising:
the input end of the gating unit inputs an original reset signal rst _ n _ in, a clock signal clk and a synchronous reset signal rst _ n, and the output end of the gating unit outputs a gating clock rst _ n _ clk; the original reset signal rst _ n _ in is asynchronous to a clock signal clk;
the reset end of the register inputs rst _ n _ in, and the clock end of the register inputs a gated clock rst _ n _ clk.
2. The reset synchronizer circuit of claim 1 wherein the gating cell comprises a three input or gate and an inverter;
an original reset signal rst _ n _ in is input to the input end of the inverter;
the output end of the inverter, a clock signal clk and a synchronous reset signal rst _ n are input into the input end of the three-input OR gate, and the output end of the three-input OR gate outputs a gated clock rst _ n _ clk.
3. The reset synchronizer circuit according to claim 2 wherein said registers comprise a first level register and a second level register, said first level register coupled to said second level register.
4. The reset synchronizer circuit of claim 3,
VDD is input to the power supply input end of the first-stage register, and the output end of the first-stage register outputs a first-stage synchronous reset signal rst _ n _ syn1 of an original reset signal rst _ n _ in.
5. The reset synchronizer circuit according to claim 3 wherein the data input of the second stage register inputs the first stage synchronous reset signal rst _ n _ syn1 of the original reset signal rst _ n _ in and the output of the second stage register outputs the synchronous reset signal rst _ n.
6. The reset synchronizer circuit of claim 2 wherein the output of the three input or gate outputs the first valid clock edge as a gated clock, comprising:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at the first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at the high level to obtain a first effective clock edge of the gated clock.
7. The reset synchronizer circuit of claim 2 wherein the output of the three input or gate outputs the first valid clock edge as a gated clock, comprising:
at the second clock rising edge, the synchronous reset signal rst _ n becomes high level, the output of the three-input or gate is used as the gated clock rst _ n _ clk to output high level, and the second effective clock edge of the gated clock is obtained.
8. A clock gating method of a reset synchronizer circuit, applied to the reset synchronizer circuit according to any one of claims 1 to 7, the method comprising:
the reset synchronizer circuit three-input OR gate generates gating clocks which are only effective on two clock rising edges after reset release according to an input original reset signal rst _ n _ in, a synchronous reset signal rst _ n and a clock signal clk.
9. The method of clock gating of a reset synchronizer circuit of claim 8 wherein generating a gated clock that is valid only on two clock rising edges after a reset release comprises:
the gated clock rst _ n _ clk is fixed to be at a low level, the original reset signal rst _ n _ in jumps from the low level to a high level, and at the first clock rising edge of the gated clock rst _ n _ clk and the clock signal clk, the first-stage synchronous reset signal rst _ n _ sync1 changes to be at a high level to generate a first effective clock edge of the gated clock.
10. The method of clock gating of a reset synchronizer circuit of claim 8 wherein generating a gated clock that is valid only on two clock rising edges after a reset release comprises:
at the second clock rising edge, the synchronous reset signal rst _ n changes to high level, the output of the three-input or gate outputs high level as the gated clock rst _ n _ clk, and the second effective clock edge of the gated clock is obtained.
CN202011344954.6A 2020-11-26 2020-11-26 Reset synchronizer circuit and clock gating method thereof Active CN114546083B (en)

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Cited By (2)

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CN116126116A (en) * 2023-02-03 2023-05-16 芯动微电子科技(武汉)有限公司 Clock reset circuit, method, device, system-in-chip and storage medium
CN117435016A (en) * 2023-10-11 2024-01-23 无锡摩芯半导体有限公司 Design method of reset circuit

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Publication number Priority date Publication date Assignee Title
CN116126116A (en) * 2023-02-03 2023-05-16 芯动微电子科技(武汉)有限公司 Clock reset circuit, method, device, system-in-chip and storage medium
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CN117435016B (en) * 2023-10-11 2024-04-16 无锡摩芯半导体有限公司 Design method of reset circuit

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