JP3024566B2 - Semiconductor integrated circuit design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design system, and more particularly to a flip-flop (F / F).
And a method for designing a semiconductor integrated circuit for facilitating initialization of a semiconductor integrated circuit .

[0002]

2. Description of the Related Art Recently, in a semiconductor integrated circuit, a flip-flop (F / F) of a succeeding stage is output based on output data of a flip-flop (F / F) of a preceding stage in order to reduce power consumption and area or improve speed. An asynchronous circuit having a deep logic for generating a clock to be input is employed.

Two methods have been devised as a method for initializing the asynchronous circuit having a deep logic.

The above-described asynchronous circuit having a deep logic has a flip-flop (hereinafter, referred to as F / F) 2 to which a data signal 19 and a clock signal 20 are inputted as shown in FIG.
, An OR circuit that receives the clock signal generation signal 5 from the F / F 2 as an input, and outputs an asynchronous clock signal 4 to a flip-flop (hereinafter, referred to as F / F) 1 at a subsequent stage, and an output of the F / F 1 There is provided an AND circuit which takes an AND of the signal 7 and outputs a clock signal 7 to a flip-flop (F / F) 6 at a subsequent stage. In the figure, 21 is a data signal input to the F / F1, and 22 is the F / F
A data signal input to F6, and 23 is an output signal from F / F6.

In the first initialization method, the F / Fs 1 and 6 without the reset and set terminals shown in FIG. 8 are replaced with the F / Fs 1 and 6 provided with the reset and set terminals shown in FIG.
F10, and reset signal or set signal 17 of the reset terminal and set terminal of the changed F / F10.
Is directly controlled from the external reset terminal 18 and input.
This is a method of performing circuit initialization by switching F10 to a reset or set state.

A second initialization method uses the F / Fs 1, 6 without the reset and set terminals shown in FIG.
, And a signal pattern for initializing the F / Fs 1 and 6 as shown in FIG.

In FIG. 10, (a) shows F / F2 of FIG.
3 shows the waveform of the data signal 19 to be input to the. (B)
9 is a waveform of a clock signal of F / F2 shown in FIG. FIG. 10C shows waveforms of the output signal 5 of the F / F 2 and the clock signal 4 of the F / F 1 shown in FIG.

In FIG. 10, the clock signal 20 rises at time t ₁ and the output signal 5 changes from indefinite at time t ₁ to θ.
To change, and changes in θ from indeterminate clock signal 4 is also a time t ₁ of the F / f1, changes to the data signal 19 is "1" at time t _2, the "1" in the clock signal 20 is time t ₃ When changing the output signal of the F / F2 5 and F / F1 of the clock signal 4 is changed to "1" at time t _3. In the same way,
It changes to "0" at the time t _5.

In FIG. 10, (d) shows F / F of FIG.
The input signal waveform of the data signal 21 of F1 is shown, and (e) is the output signal of F / F1 and the clock signal waveform of F / F6.

In FIG. 10, the exit of the F / F1 changes from indefinite to θ at time t ₃ , and changes from “0” to “1” at time t ₇ .

In FIG. 10, (f) is the data signal 22 of the F / F6, and (g) is the output signal 23 of the F / F6. In FIG. 10, the data output signal 23 of the F / F 6
When the clock signal 8 of the F / F 6 changes from “0” to “1” at the time t ₇ , the data output signal 23 of the F / F 6 changes from indefinite to “0”.

As described above, without changing to the F / F provided with the reset or set terminal, the F / F
In order to initialize / F, a huge and complicated pattern signal is required.

[0013]

As shown in FIG. 9, an F / F provided with a reset terminal and a set terminal is changed, and the reset terminal and the set terminal of the F / F are directly controlled from an external terminal. In the case of the method of initializing / F, F
Since a control terminal for controlling the reset or set terminal of / F is required, the number of signal pins increases.

As shown in FIG. 10, in the initialization method in which the F / F is provided with a signal pattern for initialization without changing to the F / F provided with the reset or set terminal, the clock signal of the F / F is different. Is controlled by the F / F output signal, there is a problem that an enormous and complicated signal pattern is required to operate all the F / F clock signals with signals from external terminals.

An object of the present invention is to provide a method for designing a semiconductor integrated circuit that can easily initialize a F / F with a small signal pattern without increasing the number of signal pins in the semiconductor integrated circuit .

[0016]

In order to achieve the above object, a semiconductor integrated circuit designing method according to the present invention performs a search process, a replacement process, and an initialization process to design a semiconductor integrated circuit. a circuit design method, a semiconductor integrated circuit comprises a circuit arrangement of an asynchronous semiconductor integrated circuit of the asynchronous circuitry, controls the clock signal of the subsequent flip-flop based on an output signal from the preceding flip-flop has been constructed as a circuit configuration, the search process, the input clock signal has preceding
Controlled by flip-flop output data, reset signal
First with a circuit configuration that does not have an input terminal of the No. flip <br/> is intended to perform a search processing flop, the replacement process, the retrieved said first flip-flop, a reset signal replacing the second flip-flop having an input terminal, which performs a process of forming the circuit, before
The initialization process performs a process of initializing the replaced second flip-flop based on the output signal of the power-on reset generation block. Also the search
The processing further has a reset signal input terminal, and
The set signal input terminal is the output of the previous flip-flop.
Third flip having a circuit configuration controlled by force data
Performs flop search processing, and initializes
The processing further includes searching the third flip-flop.
Before the reset signal input terminal of the
・ Reset signal is activated by reset generation block signal.
To insert a combinational circuit that becomes active.
is there.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams illustrating a semiconductor integrated circuit to be designed having an asynchronous circuit configuration.

The method for designing a semiconductor integrated circuit according to the present invention comprises:
A search process S1, a replacement process S2, and an initialization process S3 are performed to design a semiconductor integrated circuit. Here, the semiconductor integrated circuit to be designed has an asynchronous circuit configuration, and the semiconductor integrated circuit having the asynchronous circuit configuration controls a clock signal of a subsequent flip-flop based on an output signal from a preceding flip-flop. Is built as

Specifically, first, in search processing S ₁ ,
A flip-flop (hereinafter referred to as F
/ F). In the detection method, as a first condition, the F / F1 in which the reset or set terminal shown in FIG. 2 is not provided and the clock signal 4 is controlled by the output signal 5 of the F / F is detected. In order to initialize the F / F 1, the F / F that generates the clock signal 2 is used.
Must be controlled. F / F6
In order to initialize the F / F as the relationship that the clock signal 4 is controlled by the output signal 7 of the F / F 1 in which the clock signal 4 is controlled by the output signal 5 of the F / F 2 becomes deeper as shown in FIG. Requires a huge signal pattern.

As a second condition, reset or set
The F / F in which the signal 7 is controlled by the output signal 5 of the F / F 2
3 is detected. This F / F3 is also the F / F3 detected under the first condition.
Like / F1, controlling an output signal of F / F2 to initialize F / F3 with reset / set signal 7 of F / F3 requires an enormous signal pattern.

[0021] Next, in the replacement process S ₂ as shown in Figure 4, it converts the F / F1 detected by the first condition of the reset or set with F / F10.

[0022] Finally, in the initialization process S ₃ as shown in Figure 5, a reset or set with F / F in the first condition
F / F reset or set signal 11 converted to 19
, The output signal 13 of the power-on reset generation block 12 is input.

When the reset or set signal 7 is controlled by the output of the F / F 2 as shown in FIG. 3 , the output of the power-on reset generation block 12 is output before the reset or set signal 7 as shown in FIG. A NOR 15 which automatically activates the reset / set signal 14 of the F / F 3 by the signal 13 is inserted.

Next, the circuit operation of FIGS. 5 and 6 will be described with reference to the timing chart of FIG. As shown in FIG. 7A, the power supply starts rising at t1 as shown in the power supply waveform, and V2 at t2.
Ascend to DD. FIG. 7B shows the waveform of the output signal 13 of the power-on reset signal generation block 12. The output signal 13 rises to VDD at t2, starts falling at t3, and becomes 0 at t4, similarly to the power supply.

As shown in FIG. 7C, the F / F1 of FIG.
With the waveform of the output signal of 0, the output signal 13 of the power-on reset signal generation block 12 of FIG. 7A is input to the reset signal of the F / F 10, the F / F 10 is reset, and the output signal of the F / F 10 is undefined from t3. It becomes 0 at t5 from the state.

As shown in FIG. 7D, NOR1 of FIG.
5, the output signal 13 of the power-on reset signal generation block 12 is input, and the output signal 14 of the NOR 15 starts rising at t3 and becomes VDD at t5. As shown in FIG. 7 (e), the output signal 14 of the NOR 15 is input to the reset of the F / F3 with the output signal 16 of the F / F3 in FIG. 6, and from the undefined state at t5 to 0 at t6,
Initialized.

[0027]

As described above, according to the present invention, an F / F which is difficult to initialize is detected from a semiconductor integrated circuit, and the detected F / F is reset or the F / F without a set terminal is reset or set. Converted to F / F with terminal and detected F
Since the F / F is directly initialized by inputting the output signal of the power-on reset generation block to the reset or set terminal of / F, the circuit can be easily initialized with a small number of signal patterns without increasing the number of external signal pins. The conversion can be performed, and therefore, the semiconductor integrated circuit can be easily designed.

[Brief description of the drawings]

FIG. 1 shows a semiconductor integrated circuit design according to an embodiment of the present invention.
It is a flowchart which shows a method .

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit to be designed having an asynchronous circuit configuration that is difficult to initialize.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit to be designed having an asynchronous circuit configuration that is difficult to initialize.

4 is a circuit diagram showing a circuit obtained by converting the F / F shown in FIG. 2 into an F / F with reset.

FIG. 5 is a circuit diagram showing a circuit converted into a circuit that can be easily initialized.

FIG. 6 is a circuit diagram showing a circuit converted into a circuit that can be easily initialized.

FIG. 7 is a timing chart of the circuits shown in FIGS. 5 and 6;

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is a circuit diagram showing a conventional example.

FIG. 10 is a timing chart showing a conventional example.

[Explanation of symbols]

1 F / F 2 which is difficult to initialize 2 F / F clock signal generation F / F 3 F / F which is difficult to initialize 4 Asynchronous clock signal 5 Output signal of clock signal generation F / F 6 Generated from output signal of F / F F / F 7 F / F output signal with clock signal to be input 8 Clock signal 9 Asynchronous reset signal 10 F / F with reset 11 Reset signal 12 Power-on reset signal generation block 13 Power-on reset signal generation block output signal 14 Reset signal after conversion 15 NOR 16 Output signal of F / F3 17 Reset signal 18 Reset terminal 19 Data signal of F / F2 20 Clock signal of F / F2 21 Data signal of F / F1 22 Data signal of F / F6 23 Output signal of F / F6

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit design for performing a search process, a replacement process, and an initialization process to design a semiconductor integrated circuit.
A method, a semiconductor integrated circuit comprises a circuit arrangement of an asynchronous semiconductor integrated circuit of the asynchronous circuit configuration, the circuit configuration for controlling the clock signal of the subsequent flip-flop based on an output signal from the preceding flip-flop has been constructed as the search process, the input clock signal has preceding pretending
Controlled by the flip-flop output data,
And performs a process of searching for the first flip <br/> flop having a circuit configuration with no input, the replacement process, the retrieved said first flip-flop, the input terminal of the reset signal replacing the second flip <br/> flop with, which performs a process of forming the circuit, the initialization process is replaced second flip-flop the output of the power-on-reset generator block A method for designing a semiconductor integrated circuit , comprising performing a process of initializing based on a signal. 2. The search process according to claim 1 , further comprising the step of:
An input terminal, and the input terminal of the reset signal
Configuration controlled by output data of flip-flops
To search for a third flip-flop having
And the initialization process further includes the third free
Before the reset signal input terminal of the flip-flop,
Reset signal by signal of power-on reset generation block
To insert a combinational circuit that activates the signal.
2. The semiconductor device according to claim 1, wherein
Body integrated circuit design method.