JPH11145788A - Flip-flop device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equivalently switch rising/falling edges in accordance with a selection signal by switching a state, where an inputted clock against a clock is outputted and a state where the inputted clock is inverted and outputted, in accordance with the selection signal and operating a flip-flop in which the generated clock output is used as the clock. SOLUTION: The selection signal inputted to a selection terminal 4 is inputted to the other input terminal of an AND circuit 12 via an inverter 11 and is inputted to the other input terminal of an AND circuit 13. The output terminals of the AND circuits 12 and 13 are connected to the input terminal of an OR circuit 14 and the output of the OR circuit 14 is used as the output of a selection circuit 7. A D flip-flop 10 can be operated by switching whether it is operated by the rise edge of the input clock of the clock input terminal 3 or is operated by the fall edge in accordance with the selection signal inputted to the selection terminal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop device for a semiconductor integrated circuit and a semiconductor device.

[0002]

2. Description of the Related Art There are various types of conventional flip-flop devices such as a device configured by a D flip-flop and a device configured by a JK flip-flop.

This flip-flop device is used as a 1-bit storage circuit or a delay element. Conventional flip-flop device 2 shown in FIG.
1 is a D flip-flop that operates at the rising edge (positive edge) of the clock.
The flip-flop device 22 shown in (b) is composed of a D flip-flop that operates at the falling edge (negative edge) of the clock.

The flip-flop device 21 has a data input terminal 23 (input signal name: D), a clock input terminal 25 (input signal name: CK), and an output terminal 27 (output signal name: Q). I have.

The flip-flop device 22 has a data input terminal 24 (input signal name: D), a clock input terminal 26 (input signal name: CK), and an output terminal 28.
(Output signal name: Q).

[0006] The flip-flop device 21 is shown in FIG.
As shown in FIG. 6B, the flip-flop device 22 has a circuit configuration as shown in FIG. 6B.

The operation of the flip-flop device configured as described above will be described. In the flip-flop device 21, as shown in FIG. 7A, by applying a rising edge clock to the clock input terminal 25, the data applied to the input terminal 23 is latched and output to the output terminal 27.

Further, in the flip-flop device 22, as shown in FIG. 7B, by applying a falling edge clock to a clock terminal 26, data applied to an input terminal 24 is latched and output to an output terminal 28. Is output.

[0009]

However, at the time of circuit design, it is determined whether to use the flip-flop device 21 which operates on the rising edge clock or the flip-flop device 22 which operates on the falling edge clock. Therefore, the polarity of the edge clock cannot be easily changed after the layout of the circuit design or the completion of the semiconductor device (for example, an integrated circuit).

It is very important to adjust the clock skew after the layout of the circuit design and the timing of the external interface, or to adjust the clock skew and the timing of the external interface due to variations in the process and mounting after the semiconductor device is completed. There is a problem that the timing adjustment by changing the polarity of the edge clock cannot be easily performed.

An object of the present invention is to provide a flip-flop device which can easily change the polarity of an edge clock even after layout of a circuit design or completion of a semiconductor device.

[0012]

According to the present invention, a flip-flop that operates at a rising edge or a falling edge is used to equivalently switch the rising or falling edge of the flip-flop. is there.

According to the present invention, the polarity of the edge clock can be easily changed even after the layout of the circuit design or the completion of the semiconductor device.

[0014]

According to a first aspect of the present invention, there is provided a flip-flop device in which output data changes in response to input data and a clock, wherein the input clock is output in response to the clock. A selection circuit is provided for switching between a state of inverting and outputting a clock according to a selection signal, and a flip-flop which operates using a clock output generated at an output of the selection circuit as a clock.

According to a second aspect of the present invention, there is provided a semiconductor device including the flip-flop device according to the first aspect, wherein a selection terminal of the selection circuit is connected to an external connection terminal.
Hereinafter, the present invention will be described based on specific embodiments.

(Embodiment) An integrated circuit which is a semiconductor device incorporating a flip-flop device of the present invention is configured as follows.

FIG. 1 shows a flip-flop device 1 according to the present invention.
As shown in the figure, the flip-flop device 2 shown in the conventional example
The clock signal is input to the clock signal input side of the rising edge operation D flip-flop 10 used in 1 through the selection circuit 7.

As shown in FIG. 2, the flip-flop device 1 is represented by a logical symbol, and has a data input terminal 2 (input signal name: D) and a clock input terminal 3 (input signal name: CK). And output terminal 5 (output signal name: Q)
And a selection terminal 4 (input signal name: CKSEL).

In the selection circuit 7, the clock signal input to the clock input terminal 3 is input to one input terminal of the AND circuit 12 and is input to one input terminal of the AND circuit 13 via the inverter 8. The selection signal input to the selection terminal 4 is input to the other input terminal of the AND circuit 12 via the inverter 11 and the AND circuit 1
3 is input to the other input terminal. AND circuit 12,
Each of the output terminals 13 is connected to the input terminal of the OR circuit 14, and the output of the OR circuit 14 is used as the output of the selection circuit 7.

The clock input terminal 3 of the selection circuit 7 is
A clock signal (signal name: CK) shown in (a) is input, and a clock signal whose logic is inverted by the inverter 8 is supplied to one input terminal of the AND circuit 13 as shown in FIG. .

As shown in FIG. 3C, when the selection signal (signal name: CKSEL) is LOW, the output of the AND circuit 13 is LOW, and the clock signal input to the AND circuit 12 is output from the AND circuit 12. The clock signal is output from the selection circuit 7 as shown in FIG.

In the flip-flop device 1, when the selection signal is L
In the OW state, the data at the data input terminal 2 is latched at the rising edge P1 of the output signal of the output 6 of the selection circuit 7, that is, at the rising edge P2 of the input clock of the clock input terminal 3.

When the selection signal (signal name: CKSEL) is switched to HI as shown in FIG.
The output of the circuit 12 becomes LOW, and the clock signal input to the input terminal of the AND circuit 13 is output from the AND circuit 13, and the clock signal is inverted from the input clock of the clock input terminal 3 as shown in FIG. A signal is output from the selection circuit 7.

In the flip-flop device 1, the selection signal is H
In the state I, the data at the data input terminal 2 is latched at the rising edge P3 of the output signal of the output 6 of the selection circuit 7, that is, at the falling edge P4 of the input clock of the clock input terminal 3.

As described above, although the flip-flop device 1 uses the D flip-flop 10 which operates at the rising edge, the input clock of the clock input terminal 3 is input in response to the selection signal input to the selection terminal 4. It is possible to switch between the operation at the rising edge P2 and the operation at the falling edge P4.

FIG. 4 shows the truth values of the flip-flop device 1. Further, in this integrated circuit 15, since the selection terminal 4 of the selection circuit 7 is connected to the external connection terminal 16,
By designating a selection signal to be input to the external connection terminal 16 without changing the circuit even after the layout of the circuit design or the completion of the semiconductor device, the circuit operates at the rising edge of the input clock or rises or falls. Whether the operation is performed at the falling edge can be easily switched, and the timing can be adjusted by changing the polarity of the edge clock.

In this embodiment, the case where the selection circuit is provided in the flip-flop device which operates at the rising edge of the clock has been described. However, the case where the selection circuit is provided in the flip-flop device which operates at the falling edge of the clock. Has the same effect.

In this embodiment, the case where a selection circuit is provided in a flip-flop device constituted by D flip-flops has been described. Even so, it has the same effect.

In this embodiment, the case where the flip-flop device 1 is included in the integrated circuit 15 which is a semiconductor device has been described. However, the same effect is obtained even when the flip-flop device 1 is a single device.

[0030]

As described above, according to the flip-flop device of the present invention, the state of outputting a clock input with respect to a clock and the state of inverting and outputting the input clock with respect to a clock are determined according to a selection signal. By providing the selection circuit for switching and the flip-flop that operates using the output of the selection circuit as a clock, the rising edge clock operation or the falling edge clock operation can be switched according to the selection signal input to the selection circuit. .

According to the semiconductor device of the present invention, the flip-flop device provided with the selection circuit is included in the semiconductor device, and the selection terminal of the flip-flop device is connected to the external connection terminal of the semiconductor device. Even after completion of the semiconductor device or after completion of the semiconductor device, whether to operate at the rising edge or falling edge of the input clock without changing the circuit, according to the selection signal input to the external connection terminal The switching can be easily performed, and an excellent flip-flop device can be provided.

Further, it is not necessary to determine whether to use a flip-flop device that operates at the rising edge of the clock or a flip-flop device that operates at the falling edge of the clock in the circuit design stage as in the related art. Even after the layout of the circuit design or the completion of the semiconductor device, the polarity of the edge clock can be easily changed, and the timing adjustment can be facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a flip-flop device according to an embodiment of the present invention.

FIG. 2 is a logical symbol diagram of the flip-flop device of the embodiment.

FIG. 3 is a time chart of the selection circuit of the embodiment.

FIG. 4 is a diagram showing truth values of the flip-flop device according to the embodiment;

FIG. 5 is a logical symbol diagram of a conventional flip-flop device.

FIG. 6 is a circuit diagram of a conventional flip-flop device.

FIG. 7 is a diagram showing truth values of a conventional flip-flop device;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Flip-flop device 2 Input terminal 3 Clock input terminal 4 Selection terminal 5 Output terminal 6 Output of selection circuit 7 Selection circuit 8 Inverter 9 Output of inverter 8 10 D flip-flop 11 Inverter 12 AND circuit 13 AND circuit 14 OR circuit 15 Integrated circuit 16 External connection terminal

Claims (2)

[Claims] 1. A flip-flop device in which output data changes in response to input data and a clock, wherein a selection signal indicates a state in which a clock input to the clock is output and a state in which the input clock is inverted and output. And a flip-flop that operates using a clock output generated at the output of the selection circuit as a clock. 2. A semiconductor device comprising the flip-flop device according to claim 1, wherein a selection terminal of the selection circuit is connected to an external connection terminal.