CN111510122A - Power-on reset device of multi-power system - Google Patents
Power-on reset device of multi-power system Download PDFInfo
- Publication number
- CN111510122A CN111510122A CN202010295207.1A CN202010295207A CN111510122A CN 111510122 A CN111510122 A CN 111510122A CN 202010295207 A CN202010295207 A CN 202010295207A CN 111510122 A CN111510122 A CN 111510122A
- Authority
- CN
- China
- Prior art keywords
- reset
- power supply
- power
- module
- digital circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a power-on reset device of a multi-power system, and relates to a new generation of information technology. The scheme is provided for solving the problem that each digital circuit module in the prior art has strong dependence on the power supply sequence of the power supply. The reset control modules in all the secondary power supply channels respectively receive a pre-reset signal and a reset reference signal; and outputting a secondary reset signal to the corresponding digital circuit module in the same power supply channel after delaying the preset time only when the input pre-reset signal and the reset reference signal meet the preset logic. The digital delay and control circuit has the advantages that through the design of the invention with digital delay and control, the problem that the reset sequence of the internal digital circuit module is difficult to control due to uncertain power-on sequence of the chip external power supply in the chip multi-digital circuit module and a multi-power supply system is solved, so that the reset sequence and time of different digital circuit modules can be controlled. And the reset minimum interval time of different digital circuit modules can be programmed, so that the stability and controllability of a reset system are ensured.
Description
Technical Field
The invention relates to a new generation of information technology, in particular to a power-on reset device of a multi-power-supply system.
Background
With the development of integrated circuit technology, the chip integration level is higher and higher, the functions are more and more, and thus the structure for supplying power to the chip is more and more complicated. Particularly, for a digital chip and a digital-analog hybrid chip, in order to meet the requirement of multifunctional operation of a chip system, circuits with different functions have different power-on timing requirements, and the timing control of a multi-power system is very difficult.
For a highly integrated chip, more than two power supplies are usually required, and the circuits powered by these power supplies do not operate independently, but rather, it is desirable to have a certain sequential timing control of their resets. However, the power supply for supplying power from the outside of the chip may supply power to all power supplies of the chip simultaneously, or the power supply sequence of the power supplies may be uncertain, so that the method for generating the multi-power reset signal inside the chip is particularly important. If the reset system is not reliable, the entire chip may be in an abnormal operating state.
A conventional multi-power reset circuit is shown in fig. 1, and the resetting of different digital circuits is completely dependent on the respective power supplies. If the reset sequence of each digital circuit has a requirement in sequence, the power-on sequence of the power supply must have a corresponding requirement, which brings inconvenience to the power supply design of the power supply.
Fig. 2 is an improvement of the "multi-power-supply power-on and power-off reset circuit" in the patent on the conventional multi-power-supply system, which on one hand reduces the need for multiple voltage reference modules and on the other hand prevents the main reset signal from lagging behind the generation of other reset signals. Compared with the conventional reset circuit of fig. 1, the reset circuit of fig. 2 requires a redesign of the reset module to generate or receive control of the control signal. Moreover, there is a disadvantage in that the timings of different reset signals cannot be realized as required. For a multi-power system, if each power supply adopts the same reset mode, the reset sequence of the system completely depends on the power supply sequence of an external power supply, and each digital module of the multi-power system cannot be reset according to the sequence set by the system.
In an actual digital multi-power system, there may exist different digital circuits that need to be reset at different times, such as resetting a system control register first, then resetting a clock to generate a relevant digital circuit, and finally resetting a digital circuit related to a digital algorithm. However, the external power source will present a great challenge to the reset system in case of different power-on sequences.
Disclosure of Invention
The invention aims to provide a power-on reset device of a multi-power system, which can realize the function of resetting an internal digital circuit module as required without depending on the power-on sequence of an external power supply.
The invention relates to a power-on reset device of a multi-power system, which comprises a voltage reference module, a primary power supply channel and a plurality of secondary power supply channels, wherein the voltage reference module is used for providing a power supply voltage for a power supply system; all the power supply channels respectively comprise a reset module and a corresponding digital circuit module; the voltage reference module collects the input voltage of the main power supply channel and outputs voltage reference to all the reset modules, and the reset module of the main power supply channel outputs a main reset signal to the corresponding digital circuit module; all the secondary power supply channels respectively comprise a reset control module; a first input end of the reset control module receives a pre-reset signal output by a reset module in the same power supply channel, and a second input end of the reset control module receives a reset reference signal; and outputting a secondary reset signal to the corresponding digital circuit module in the same power supply channel after delaying the preset time only when the input pre-reset signal and the reset reference signal meet the preset logic.
The power-on reset device of the multi-power system has the advantages that through the design of the invention with digital delay and control, the problem that the reset sequence of an internal digital circuit module is difficult to control due to uncertain power-on sequence of a chip external power supply in a chip multi-digital circuit module and the multi-power system is solved, so that the reset sequence and time of different digital circuit modules can be controlled. And the reset minimum interval time of different digital circuit modules can be programmed, so that the stability and controllability of a reset system are ensured.
The reset reference signal is a main-stage reset signal or a previous-stage reset signal. In that two input modes of the reset reference signal are provided.
The reset control module comprises a logic circuit, a delay control register and a delay circuit; the first pin of the logic circuit is a first input end of the reset control module, the second pin of the logic circuit is a second input end of the reset control module, and the output end of the logic circuit is connected with the reset end of the delay circuit; the input end of the delay control register is connected with the second input end of the logic circuit and the first input end of the delay circuit, and the output end of the delay control register is connected with the second input end of the delay circuit; the output end of the delay circuit is the output end of the reset control module. Provides a specific structure of a reset control module.
Drawings
Fig. 1 is a circuit diagram of a multi-power-supply power-on reset device in the prior art.
Fig. 2 is a circuit schematic of another prior art multiple power supply power-on-reset apparatus.
Fig. 3 is a schematic circuit diagram of a first embodiment of the power-on reset apparatus according to the present invention;
fig. 4 is a schematic circuit diagram of a reset control module commonly used in the power-on reset apparatus according to the present invention;
FIG. 5 is a timing diagram of a primary power source powering up earlier than other secondary power sources in accordance with one embodiment of the present invention;
FIG. 6 is a timing diagram of the primary power source powering up later than the other secondary power sources in accordance with an embodiment of the present invention.
Fig. 7 is a schematic diagram of an expansion circuit of the power-on reset apparatus according to the first embodiment of the present invention.
Fig. 8 is a schematic circuit diagram of a second embodiment of the power-on reset apparatus according to the present invention;
fig. 9 is a schematic diagram of an expansion circuit of the power-on reset apparatus according to the second embodiment of the present invention.
Reference numerals:
s0-main power, S1-Sn-first secondary power to nth secondary power;
rst 0-a main level reset module, Rst 0-Rstn-a first secondary reset module to an nth secondary reset module;
u0-main level digital circuit module, U1-Un-first level digital circuit module to nth level digital circuit module;
rstc 1-Rstcn-first reset control module to nth reset control module;
ref-voltage reference module;
DE L AY-delay circuit.
Detailed Description
Example one
As shown in fig. 1, the power-on reset device of a multi-power system according to the present invention is exemplified by a typical three-power three-digital circuit module, but the specific number of the power-on reset device can be adjusted without creative work based on experimental means of those skilled in the art, and therefore, the power-on reset device should not be taken as a specific limitation to the protection scope of the present invention. The power supply system specifically comprises a voltage reference module Ref, a primary power supply channel, a first secondary power supply channel and a second secondary power supply channel. The voltage reference module Ref is used for outputting a reference voltage.
The primary power channel includes at least a primary power supply S0, a primary reset module Rst0, and a primary digital circuit module U0. The main reset module Rst0 receives the reference voltage and samples the voltage of the main power supply S0 to determine whether the power-on of the main power supply S0 is completed, and outputs a main reset signal to the main digital circuit module U0 when the power-on is completed. The primary digital circuit block U0 is powered by a primary power supply S0.
The first secondary power supply channel includes at least a first secondary power supply S1, a first secondary reset module Rst1, a first reset control module Rstc1, and a first secondary digital circuit module U1. The first secondary reset module Rst1 receives the reference voltage and samples the voltage of the first secondary power supply S1 to determine whether the first secondary power supply S1 is powered on, and outputs a pre-reset signal to the first reset control module Rst1 when the power on is completed. The first reset control module Rstc1 further inputs a main reset signal of the main reset module Rst0, and outputs a corresponding first secondary reset signal to the first secondary digital circuit module U1 after a set delay time after the pre-reset signal and the main reset signal satisfy a preset logic relationship.
The second secondary power supply channel at least comprises a second secondary power supply S2, a second secondary reset module Rst2, a second reset control module Rstc2 and a first secondary digital circuit module U2. The second secondary reset module Rst2 receives the reference voltage and samples the voltage of the second secondary power supply S2 to determine whether the second secondary power supply S2 is powered on, and outputs a pre-reset signal to the second reset control module Rst2 when the power on is completed. The second reset control module Rstc2 further inputs a first secondary reset signal, and outputs a corresponding second secondary reset signal to the second secondary digital circuit module U2 after a preset delay time after the pre-reset signal and the first secondary reset signal satisfy a preset logic relationship.
The first reset control module Rstc1, the second reset control module Rstc2 and other reset control modules of the present invention all adopt the same structure, as shown in fig. 4. Includes a logic circuit, a delay control register and a delay circuit. The first pin of the logic circuit is a first input end of the reset control module, the second pin of the logic circuit is a second input end of the reset control module, and the output end of the logic circuit is connected with the reset end of the delay circuit. The input end of the delay control register is connected with the second input end of the logic circuit and the first input end of the delay circuit, and the output end of the delay control register is connected with the second input end of the delay circuit. The output end of the delay circuit is the output end of the reset control module.
The specific delay length may be implemented by setting parameters in the delay control register. Suppose that the first secondary digital circuit module U1 needs to wait at least t2 time after the main digital circuit module U0 completes resetting before completing resetting to enter the working state; meanwhile, it is assumed that the second-stage digital circuit module U2 needs to wait at least t3 time after the reset of the first-stage digital circuit module U1 is completed to complete the reset to enter the operating state. The delay time of the first reset control module Rstc1 may be set to t2 and the delay time of the second reset control module Rstc2 may be set to t 3.
If the primary power source S0 is earlier than the other two secondary power sources in the power-up sequence of the three power sources, three reset signal sequences as shown in fig. 5 can be obtained. It can be seen that the power-on reset of the system is sequentially a main-level reset signal, a first-level reset signal and a second-level reset signal from '0' to '1'. And the time for completing the reset of the first secondary digital circuit module U1 is more than t2 after the time interval for completing the reset of the primary digital circuit module U0, and the time for completing the reset of the second secondary digital circuit module U2 is t3 after the time interval for completing the reset of the first secondary digital circuit module U1.
If the primary power source S0 is later than the other two secondary power sources in the power-up sequence of the three power sources, the three reset signal sequences shown in fig. 6 can be obtained. It can be seen that the power-on reset of the system is still sequentially a main reset signal, a first secondary reset signal and a second secondary reset signal from "0" to "1". And the reset results are similar to fig. 5: the time for completing the reset of the first secondary digital circuit module U1 is equal to t2 after the reset completion time interval of the main digital circuit module U0, and the time for completing the reset of the second secondary digital circuit module U2 is equal to t3 after the reset completion time interval of the first secondary digital circuit module U1.
In practical applications, the power-up condition of the primary power source S0 is much more important than the power-up condition of the other secondary power sources. It can thus be demonstrated that the reset timing specific to each digital circuit block, which is required by the skilled person, can still be obtained based on the same setting parameters, regardless of whether the timing of the main power supply S0 has changed.
In this embodiment, the preset logic may be that when the main reset signal or the previous reset signal is "1" and the preset reset signal is also "1", the secondary reset signal outputs "1". Those skilled in the art are conventional for the application and conversion of high and low levels in logic circuits. In this embodiment, "0" and "1" are only used to intuitively express the technical solution of the present invention, and should not be taken as a specific limitation of the protection scope.
When the number of power supplies and corresponding digital circuit modules exceeds three, the same concept of the present invention can be infinitely expanded, as shown in fig. 7. All the power supply channels respectively comprise a reset module and a corresponding digital circuit module. The voltage reference module collects input voltage of the main power supply channel and outputs voltage reference to all the reset modules, and the reset modules of the main power supply channel output main reset signals to the corresponding main digital circuit modules. All secondary power supply channels respectively comprise a reset control module. The first input end of the reset control module receives a pre-reset signal output by the reset module in the same power supply channel, and the second input end of the reset control module receives a reset reference signal. And outputting a secondary reset signal to the corresponding digital circuit module in the same power supply channel after delaying the preset time only when the input pre-reset signal and the reset reference signal meet the preset logic. The working principle is similar to the typical structure of a three-power three-digital circuit module, and the expected reset time sequence can be obtained only by presetting the delay time in each secondary power supply channel.
The reset reference signal is derived from the previous stage reset signal in this embodiment.
Example two
As shown in fig. 8, a typical structure of a three-power-supply three-digital circuit block is also provided as an example, and the only difference from the structure of the three-power-supply three-digital circuit block described in the first embodiment is that the reset reference signal of the second reset control block Rstc2 is derived from the main-stage reset signal of the main-stage reset block Rst 0. The working principle is basically the same as that of fig. 3, and only the reference object judged logically changes, and the preset reset time sequence is not substantially affected. The reset time sequence preset by each digital circuit module is still realized by setting the delay time through the reset control module in each secondary power supply channel.
When the typical structure of the three-power three-digital circuit module is exceeded, the present embodiment also provides a specific circuit structure that can be infinitely expanded, as shown in fig. 9. The difference from the first embodiment is that the reset reference signal of each reset control module is derived from the main reset signal of the main reset module Rst 0. The working principle is basically the same as that of fig. 7, but the reference object judged logically changes, and the preset reset time sequence is not substantially affected. The reset time sequence preset by each digital circuit module is still realized by setting the delay time through the reset control module in each secondary power supply channel.
The power-on reset device of the multi-power-supply system disclosed by the invention has the advantages that the reset completion sequence of each digital circuit module in the system is controllable no matter how the self power-on sequence of a plurality of power supplies is, and even the minimum interval time required for completing reset among different digital circuit modules can be programmed. The circuit design of a multi-power system is greatly facilitated, the stability and the reliability of resetting of the multi-power system are guaranteed, and great convenience is brought to chip power supply and control. The reset module in the prior art does not need to be redesigned, and the method has wide universality.
It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.
Claims (3)
1. A power-on reset device of a multi-power supply system comprises a voltage reference module, a primary power supply channel and a plurality of secondary power supply channels; all the power supply channels respectively comprise a reset module and a corresponding digital circuit module; the voltage reference module collects the input voltage of the main power supply channel and outputs voltage reference to all the reset modules, and the reset module of the main power supply channel outputs a main reset signal to the corresponding digital circuit module;
the system is characterized in that all secondary power supply channels respectively comprise a reset control module; a first input end of the reset control module receives a pre-reset signal output by a reset module in the same power supply channel, and a second input end of the reset control module receives a reset reference signal; and outputting a secondary reset signal to the corresponding digital circuit module in the same power supply channel after delaying the preset time only when the input pre-reset signal and the reset reference signal meet the preset logic.
2. A power-on reset apparatus for multiple power supply systems according to claim 1, wherein said reset reference signal is a main reset signal or a previous reset signal.
3. A power-on reset device for multi-power system as claimed in claim 1, wherein said reset control module comprises a logic circuit, a delay control register and a delay circuit; the first pin of the logic circuit is a first input end of the reset control module, the second pin of the logic circuit is a second input end of the reset control module, and the output end of the logic circuit is connected with the reset end of the delay circuit;
the input end of the delay control register is connected with the second input end of the logic circuit and the first input end of the delay circuit, and the output end of the delay control register is connected with the second input end of the delay circuit; the output end of the delay circuit is the output end of the reset control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010295207.1A CN111510122A (en) | 2020-04-15 | 2020-04-15 | Power-on reset device of multi-power system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010295207.1A CN111510122A (en) | 2020-04-15 | 2020-04-15 | Power-on reset device of multi-power system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111510122A true CN111510122A (en) | 2020-08-07 |
Family
ID=71871088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010295207.1A Pending CN111510122A (en) | 2020-04-15 | 2020-04-15 | Power-on reset device of multi-power system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111510122A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821068A (en) * | 2021-09-18 | 2021-12-21 | 四川创安微电子有限公司 | Multi-power system management circuit and method in chip |
| CN114020518A (en) * | 2021-10-30 | 2022-02-08 | 深圳曦华科技有限公司 | Method and related device for power-on time sequence control |
| CN114326500A (en) * | 2021-12-27 | 2022-04-12 | 昂纳信息技术（深圳）有限公司 | Power supply circuit, FPGA circuit and optical module |
| CN116054798A (en) * | 2023-01-09 | 2023-05-02 | 成都电科星拓科技有限公司 | Method and device for eliminating time sequence metastable state in multi-voltage domain power-on and power-off reset |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2718635Y (en) * | 2004-03-03 | 2005-08-17 | 中兴通讯股份有限公司 | Multi-power source charging sequential control circuit |
| CN101873125A (en) * | 2009-04-22 | 2010-10-27 | 北京芯技佳易微电子科技有限公司 | Reset circuit |
| CN203178909U (en) * | 2013-04-03 | 2013-09-04 | 北京昆腾微电子有限公司 | Power-on and power-off reset circuit for multiple feed |
-
2020
- 2020-04-15 CN CN202010295207.1A patent/CN111510122A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2718635Y (en) * | 2004-03-03 | 2005-08-17 | 中兴通讯股份有限公司 | Multi-power source charging sequential control circuit |
| CN101873125A (en) * | 2009-04-22 | 2010-10-27 | 北京芯技佳易微电子科技有限公司 | Reset circuit |
| CN203178909U (en) * | 2013-04-03 | 2013-09-04 | 北京昆腾微电子有限公司 | Power-on and power-off reset circuit for multiple feed |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821068A (en) * | 2021-09-18 | 2021-12-21 | 四川创安微电子有限公司 | Multi-power system management circuit and method in chip |
| CN114020518A (en) * | 2021-10-30 | 2022-02-08 | 深圳曦华科技有限公司 | Method and related device for power-on time sequence control |
| CN114326500A (en) * | 2021-12-27 | 2022-04-12 | 昂纳信息技术（深圳）有限公司 | Power supply circuit, FPGA circuit and optical module |
| CN114326500B (en) * | 2021-12-27 | 2024-03-12 | 昂纳科技(深圳)集团股份有限公司 | Power supply circuit, FPGA circuit and optical module |
| CN116054798A (en) * | 2023-01-09 | 2023-05-02 | 成都电科星拓科技有限公司 | Method and device for eliminating time sequence metastable state in multi-voltage domain power-on and power-off reset |
| CN116054798B (en) * | 2023-01-09 | 2024-04-30 | 成都电科星拓科技有限公司 | Method and device for eliminating time sequence metastable state in multi-voltage domain power-on and power-off reset |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111510122A (en) | Power-on reset device of multi-power system | |
| US6600345B1 (en) | Glitch free clock select switch | |
| US6784699B2 (en) | Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time | |
| JPH05289770A (en) | Method and device for synchronization | |
| US8179181B2 (en) | Power-mode-aware clock tree and synthesis method thereof | |
| JP2009528015A (en) | Self-correcting digital pulse width modulator (DPWM) | |
| JPH0375976A (en) | Semiconductor integrated circuit device | |
| KR100594317B1 (en) | A low power consumption shift register and operating method for the shift register | |
| CN112269123A (en) | Universal configurable chip test circuit | |
| JPH11272353A (en) | Clock supply circuit and data transfer circuit | |
| CN115639897B (en) | Real-time voltage control module | |
| US7742469B2 (en) | Data input circuit and semiconductor device utilizing data input circuit | |
| CN115242224A (en) | Multi-clock glitch-free switching circuit and switching method | |
| US10924091B2 (en) | Immediate fail detect clock domain crossing synchronizer | |
| CN109547005B (en) | Conversion circuit | |
| JPH06350415A (en) | Module clock signal genarating circuit and electronics system | |
| RU170236U1 (en) | RESERVED MULTI-CHANNEL COMPUTER SYSTEM | |
| CN115657572B (en) | Design method for modular SoC chip power management system controller | |
| JP3039441B2 (en) | Synchronous edge detection method between different clocks and synchronous edge detection method between different clocks | |
| KR101025734B1 (en) | Command control circuit for semiconductor integrated device | |
| CN109074338B (en) | Integrated circuit device | |
| CN113504809B (en) | Dynamic switching method, device and system for multipath clocks | |
| US8897324B2 (en) | Timebase peripheral | |
| KR20100082834A (en) | Clock circuit with clock transfer capability and method | |
| CN113110727A (en) | Loongson 3A4000 power supply system, design method and processor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200807 |
|
| RJ01 | Rejection of invention patent application after publication |