CN2718635Y - Multi-power source charging sequential control circuit - Google Patents
Multi-power source charging sequential control circuit Download PDFInfo
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- CN2718635Y CN2718635Y CN 200420005667 CN200420005667U CN2718635Y CN 2718635 Y CN2718635 Y CN 2718635Y CN 200420005667 CN200420005667 CN 200420005667 CN 200420005667 U CN200420005667 U CN 200420005667U CN 2718635 Y CN2718635 Y CN 2718635Y
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Abstract
The utility model discloses a multi-power source charging sequential control circuit, comprising a multi-grade charging time delay parameter regulating circuit and a waveform shaping circuit. After passing through the multi-grade charging time delay parameter regulating circuit and the waveform shaping circuit, a main power source generates the enabling control signal of a first grade charging power source conversion module and the power source output signal which is utilized as the input source of the following grade charging control circuit. Consequently, the different control signals which are generated in the time sequence are used to control the enabling control terminal of each grade power source conversion module. Compared with the existing circuit, in the circuit of the utility model, the structure of the circuit is simplified, the cost of the circuit is reduced, and the realizability of the circuit is enhanced, which is helpful for the user to increase or reduce the control signals according to the respective requirement. Additionally, the user can regulate flexibly the charging time interval of the different power sources, and the actual application of the integrated circuits is promoted.
Description
Technical field
The utility model circuit relates to the electric sequence control method of veneer integrated chip, and the kind of especially powering is many, electric sequence is strict and the band integrated chip Board Power up control circuit of requirement is arranged the interval time that powers on.
Background technology
Along with the raising of process manufacturing technology and the improvement of chip structure, be power consumption and the raising travelling speed that reduces integrated chip (IC), the IC chip is more and more higher to the requirement of power supply, become multiple feed by single power supply power supply, become lower many level decentralized power supply by unified single power supply, each power supply also becomes priority and powers on by powering on jointly, to powering on mutually between the electric sequence of each power supply and power supply higher requirement also there is interval time, for guaranteeing the operate as normal of each chip, avoid chip to damage, each chip power sequential control design just seems extremely important.
For reducing cost, alleviate the complexity of power supply design, usually system or power module provide single primary power (VCC power supply) for printed circuit board, as 3.3V, this power supply converts required 2.5V, 1.8V, 1.5V or the lower power supply of each chip in the plate to by different power modules again in plate.3.3V and under the control of other lower level power supply by control circuit separately, conducting sequentially, the output correspondent voltage is for each chip operation.
Existing electric sequence control technology has four kinds, and first kind is Enable Pin (CNT) the control electric sequence that utilizes power module; Second kind is to control by the time constant of adjusting the power supply soft-start circuit to power on; The third utilizes programmable logic device (PLD) or special chip to produce control timing; The 4th kind is the electrifying timing sequence control circuit that utilizes electronic switch control.
First kind is utilized the Enable Pin (CNT) of power module to control the technology that powers on, and is the CNT end that utilizes power module, and the CNT of the power module that powers on after going to control with the power supply that powers on earlier is to reach the requirement that powers on.This technology for the supply voltage that powers on earlier be by after the converted electric power-feeding structure of supply voltage that powers on, refer to that just the supply voltage that powers on earlier is taken from the power supply that powers on after the supply, then can't adopt this method.
Control the technology that powers on by adjusting power supply slow start-up time of constant for second kind, be used for the situation that a plurality of power supplys are provided by each separate power supplies module, but because the start-up time and the power-on time of each module have nothing in common with each other, and each start-up parameter correlativity is little, controllability is relatively poor, and is especially difficult especially to the control at interval of different electrical power power-on time.
The third technology is to utilize programmable logic device (PLD) or special chip to produce control timing, these two kinds of methods all will be carried out the sequential programming to chip, make programmable logic device (PLD) or special chip go to control the Enable Pin of each power transfer module, or control the grid of each MOSFET pipe by programmed method generation control corresponding sequential and control level.This method is controlled by the chip development, and cost is higher, the circuit complexity; Programmable logic device (PLD) mostly is the ISP online programmable greatly in addition, in the specific design production run, must power on earlier and could programme veneer it, usually to finishing, programming needs the long period from Board Power up, this pin that just requires to be connected to MOSFET tube grid or each controllable electric power Enable Pin (CNT) must be in closed condition and can not be unknown state before the programming device programming, otherwise may enable the output of level turn-on power because of the control pin is in, violate chip power order or power-on time at interval, caused chip impaired.Therefore in design, must increase accessory circuit, before satisfying MOSFET pipe and power module programming, close requirement, further increase the complicacy and the cost of circuit control.
The 4th kind of electrifying timing sequence control circuit for example please number be 02205297.6 Chinese patent in the patent, this circuit adopts the electric sequence of electronic switch and each power supply of MOSFET management and control system, do not make full use of existing power module great majority and have the control end of enabling situation, used more on-off element and MOSFET pipe, the circuit structure complexity, cost is higher.
Summary of the invention
The technical matters that the utility model solves is the defective that overcomes above-mentioned prior art, and a kind of power-on time strong many power supply electrifyings sequencing circuit of controllability at interval is provided.
Many power supply electrifyings sequencing circuit described in the utility model comprises multistage delay parameter regulating circuit and the waveform shaping circuit of powering on; The described delay parameter regulating circuit that powers on is used to control back one-level power-on time at interval, described waveform shaping circuit is used to regulate the output waveform of described delay parameter regulating circuit, what make it to satisfy power transfer module at the corresponding levels enables the input end requirement, and produces the power supply input of back one-level electric sequence control; Primary power via described power on delay parameter regulating circuit and shaping circuit after, what produce that the first order powers on power transfer module enables control signal and power supply output signal, utilize this power supply output signal as back one-level electrifying control circuit input source, produce the control end that enables that different time control signal is successively controlled power transfer module at different levels thus.
Described primary power is the system power supply of veneer.
The described delay parameter regulating circuit that powers on is made up of resistance and capacitances in series.
Described waveform shaping circuit is made up of a plurality of logic gates.
Described waveform shaping circuit also comprises the level circuit for reversing.
Described level circuit for reversing is a logic inverter.
Adopt the utility model circuit to compare with existing circuit, simplified circuit structure, reduce circuit cost, improve the realizability of circuit, help the user and increase or reduce control signal according to separately needs, adjust the power-on time interval of different electrical power neatly, promoted integrated circuit application in practice.
Description of drawings
Fig. 1 is the utility model theory diagram;
Fig. 2 is the utility model embodiment block diagram;
The step input-output characteristic curve of the RC delay circuit that Fig. 3 the utility model embodiment is used;
Fig. 4 is an integrated chip feed circuit instance graph of the present utility model.
Embodiment
Below in conjunction with accompanying drawing and instantiation, the enforcement of the utility model circuit is described in further detail.
In the power supply of multicircuit power supply, for each road power supply electric sequence and power-on time space requirement are arranged, utilize first electrifying control circuit output signal as back electrifying control circuit input source, produce different time control signal successively thus and remove to control the control end that enables of each power transfer module, thereby reach control multiple power supplies sequence power-on requirement.
The integrated chip (IC) that powers on successively with need 3.3V (VCC that system provides), 2.5V, 1.8V, a 1.5V in the utility model is an example, and each power supply electrifying time interval is not more than 10ms.
Fig. 1 is the utility model circuit electrifying control circuit synoptic diagram, delay parameter regulating circuit and waveform shaping circuit are formed by powering on, system power supply is as the delay parameter regulating circuit input source that powers on that powers at first among the figure, produce corresponding signal after the waveform shaping circuit shaping, that exports corresponding controlled source modular converter enables control signal and next stage power supply electrifying control circuit input source signal.
Fig. 2 is the utility model practical circuit figure, R1 among the figure, C1 constitutes first order delay parameter regulating circuit, ' with door 1 ' with ' with door 2 ' composition first order waveform shaping circuit, R2, C2 constitutes second level delay parameter regulating circuit, ' with door 3 ' with ' with door 4 ' composition second level waveform shaping circuit, R3, C3 constitutes third level delay parameter regulating circuit, ' with door 5 ' with ' with door 6 ' composition third level waveform shaping circuit, the power supply that first order delay parameter regulating circuit provides with system is as input, ' go up power supply module Enable Pin control signal as elder generation with the output of door 1 ', ' with the delay parameter regulating circuit input source signal of door 2 ' output as the back one-level, back each control circuit of level and first order control circuit are identical.Control signal 3 is through ' not gate 1 ' carries out the level counter-rotating, and it is effective to become low level.Wave shaping here and level circuit for reversing are not limited to logic ' with door ' or ' not gate ', also can adopt other similar circuit, enable the input end requirement as long as can satisfy power transfer module.Control signal 1-3 is connected to power transfer module respectively and enables the control end (see figure 4), the conducting of controlling these power modules with close.
In the utility model circuit, when system power-up, the VCC power supply continues charging by 1 pair of capacitor C 1 of resistance R earlier, and A point current potential constantly raises, and A point current potential and power supply VCC, resistance R 1, capacitor C 1 and duration of charging relation are calculated as follows:
R, C are respectively resistance R 1 and capacitor C 1 value, U
iBeing the VCC magnitude of voltage, is definite value here, t1 initial value integral time, U
CBe the voltage initial value, in the utility model circuit, t1, U
CInitial value is 0.Therefore formula 1 can be reduced to:
Δ t is the U that powers on of system
AReach a certain level time.
Along with time integral, A point current potential constantly raises, and works as U
AReach with door 1 high level and prescribe a time limit down, with door 1 output high level, i.e. Fig. 3 is seen in B level point high jump.Control signal 1 is effective, enables corresponding power transfer module output.
U
BAfter level uprises, the C level point also uprises, and begins the delay circuit that R2, C2 form is charged, when the C level point reaches high-level threshold with door 3, control signal 2 is effective, enable corresponding power module output, the E point begins electric capacity 3 is charged, and reaches the high-level threshold of door 5 when the E level point, control signal 3 is effective, enable corresponding power module output, control signal 3 is that low level is effective, so its output terminal is realized the level counter-rotating by logic NOT.D point and calculating time delay of F point uprise beginning with C point and E level point respectively, still adopt formula 2 to calculate, at this moment μ
iBe respectively C point and E point voltage value.When more power module need be controlled, can with door 6 after connect more RC delay circuit and logic gates realized.
By formula 2 as can be known, change R, C value, can change the charging rate of RC delay circuit, thereby control the ON time of each power transfer module, determine each power transfer module ON time at interval.
Fig. 3 is the input-output characteristic curve with door 1, supposition is 0.7VCC with the high-level threshold of door 1 among the figure, along with C1 charging among Fig. 2, A point current potential constantly rises, when the A level point reached 0.7VCC (being A point among Fig. 3), the B point became high level, when capacitor C 1 charging reaches VCC value (being B point among Fig. 3), electric capacity stops charging, remains on this current potential later on.
In the present embodiment, adopt 10K and 1u value respectively as resistance R 1, capacitor C 1, then 1 effective time delay of control signal is 7ms.
Fig. 4 is for needing the integrated circuit part of power supply, control each power transfer module Enable Pin respectively from the control signal of Fig. 2, the conducting of controlling each power supply with close, in this circuit, power at first owing to VCC (3.3V) power supply, as long as the charging rate of control R1, C1 just can guarantee the power-on time interval of 3.3V and 2.5V, so the 3.3V power supply can directly provide, and do not need to use MOSFET management and control system, when after the 3.3V power supply is, powering on power supply, need to control by the MOSFET pipe.
In actual applications, can as requested, select concrete resistance, electric capacity and waveform shaping circuit according to shown in Figure 2, to reach the electric sequence requirement of multiple power supplies.
The above only is the utility model preferred example, and in order to restriction the utility model, not all within spirit of the present utility model and principle, institute changes, is equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (6)
1. power supply electrifying sequencing circuit more than a kind is characterized in that, described circuit comprises multistage delay parameter regulating circuit and the waveform shaping circuit of powering on; The described delay parameter regulating circuit that powers on is used to control back one-level power-on time at interval, described waveform shaping circuit is used to regulate the output waveform of described delay parameter regulating circuit, what make it to satisfy power transfer module at the corresponding levels enables the input end requirement, and produces the power supply input of back one-level electric sequence control; Primary power via described power on delay parameter regulating circuit and shaping circuit after, what produce that the first order powers on power transfer module enables control signal and power supply output signal, utilize this power supply output signal as back one-level electrifying control circuit input source, produce the control end that enables that different time control signal is successively controlled power transfer module at different levels thus.
2. many power supply electrifyings sequencing circuit according to claim 1 is characterized in that, described primary power is the system power supply of veneer.
3. many power supply electrifyings sequencing circuit according to claim 1 and 2 is characterized in that, the described delay parameter regulating circuit that powers on is made up of resistance and capacitances in series.
4. many power supply electrifyings sequencing circuit according to claim 1 and 2 is characterized in that described waveform shaping circuit is made up of a plurality of logic gates.
5. many power supply electrifyings sequencing circuit according to claim 4 is characterized in that described waveform shaping circuit also comprises the level circuit for reversing.
6. many power supply electrifyings sequencing circuit according to claim 5 is characterized in that, described level circuit for reversing is a logic inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420005667 CN2718635Y (en) | 2004-03-03 | 2004-03-03 | Multi-power source charging sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420005667 CN2718635Y (en) | 2004-03-03 | 2004-03-03 | Multi-power source charging sequential control circuit |
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| CN2718635Y true CN2718635Y (en) | 2005-08-17 |
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| CN 200420005667 Expired - Lifetime CN2718635Y (en) | 2004-03-03 | 2004-03-03 | Multi-power source charging sequential control circuit |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995930A (en) * | 2009-08-18 | 2011-03-30 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN102355126A (en) * | 2011-09-21 | 2012-02-15 | 北京星网锐捷网络技术有限公司 | Method for controlling synchronous power on of power supplies and control equipment |
| CN102571074A (en) * | 2010-12-08 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Voltage sequence output circuit |
| CN102567036A (en) * | 2010-12-20 | 2012-07-11 | 西安奇维测控科技有限公司 | Method using FPGA (field programmable gate array) for controlling DSP (digital signal processor) program load running |
| CN103728896A (en) * | 2012-10-10 | 2014-04-16 | 杭州华三通信技术有限公司 | Method and device for controlling power-on sequence of multiple channels of power supplies |
| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
| CN106298760A (en) * | 2016-09-14 | 2017-01-04 | 青岛海信电器股份有限公司 | The method that power supply chip and overcurrent protection thereof recover |
| CN107135514A (en) * | 2016-02-26 | 2017-09-05 | 大唐移动通信设备有限公司 | Electric control method and device on a kind of BBU of base station machine frame |
| CN109254549A (en) * | 2018-08-31 | 2019-01-22 | 上海集成电路研发中心有限公司 | A kind of FPGA network and its working method |
| CN110445484A (en) * | 2019-07-09 | 2019-11-12 | 湖北三江航天红峰控制有限公司 | A kind of power supply delays electrification circuit and design method |
| CN111510122A (en) * | 2020-04-15 | 2020-08-07 | 华南理工大学 | Power-on reset device of multi-power system |
| CN112015114A (en) * | 2020-08-17 | 2020-12-01 | 上海集成电路研发中心有限公司 | Automatic control circuit for time sequence of multi-path power supply |
| CN112305985A (en) * | 2019-07-31 | 2021-02-02 | 谷歌有限责任公司 | Power sequencing in active silicon interposer |
-
2004
- 2004-03-03 CN CN 200420005667 patent/CN2718635Y/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101995930B (en) * | 2009-08-18 | 2013-11-20 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN101995930A (en) * | 2009-08-18 | 2011-03-30 | 索尼公司 | Power supply unit, processing system and distribution method of id identification number |
| CN102571074A (en) * | 2010-12-08 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Voltage sequence output circuit |
| CN102571074B (en) * | 2010-12-08 | 2016-05-25 | 国网山东省电力公司济宁供电公司 | Voltage sequence output circuit |
| CN102567036A (en) * | 2010-12-20 | 2012-07-11 | 西安奇维测控科技有限公司 | Method using FPGA (field programmable gate array) for controlling DSP (digital signal processor) program load running |
| CN102355126A (en) * | 2011-09-21 | 2012-02-15 | 北京星网锐捷网络技术有限公司 | Method for controlling synchronous power on of power supplies and control equipment |
| CN103728896A (en) * | 2012-10-10 | 2014-04-16 | 杭州华三通信技术有限公司 | Method and device for controlling power-on sequence of multiple channels of power supplies |
| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
| CN107135514A (en) * | 2016-02-26 | 2017-09-05 | 大唐移动通信设备有限公司 | Electric control method and device on a kind of BBU of base station machine frame |
| CN106298760A (en) * | 2016-09-14 | 2017-01-04 | 青岛海信电器股份有限公司 | The method that power supply chip and overcurrent protection thereof recover |
| CN106298760B (en) * | 2016-09-14 | 2019-03-08 | 青岛海信电器股份有限公司 | The method that power supply chip and its overcurrent protection restore |
| CN109254549A (en) * | 2018-08-31 | 2019-01-22 | 上海集成电路研发中心有限公司 | A kind of FPGA network and its working method |
| CN110445484A (en) * | 2019-07-09 | 2019-11-12 | 湖北三江航天红峰控制有限公司 | A kind of power supply delays electrification circuit and design method |
| CN112305985A (en) * | 2019-07-31 | 2021-02-02 | 谷歌有限责任公司 | Power sequencing in active silicon interposer |
| CN111510122A (en) * | 2020-04-15 | 2020-08-07 | 华南理工大学 | Power-on reset device of multi-power system |
| CN112015114A (en) * | 2020-08-17 | 2020-12-01 | 上海集成电路研发中心有限公司 | Automatic control circuit for time sequence of multi-path power supply |
| CN112015114B (en) * | 2020-08-17 | 2021-11-19 | 上海集成电路研发中心有限公司 | Automatic control circuit for time sequence of multi-path power supply |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140303 Granted publication date: 20050817 |