CN104242885A - Reset circuit and circuit resetting method - Google Patents
Reset circuit and circuit resetting method Download PDFInfo
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- CN104242885A CN104242885A CN201410461058.6A CN201410461058A CN104242885A CN 104242885 A CN104242885 A CN 104242885A CN 201410461058 A CN201410461058 A CN 201410461058A CN 104242885 A CN104242885 A CN 104242885A
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Abstract
The invention provides a reset circuit and a circuit resetting method. The circuit resetting method comprises the steps of inputting a gate controlled switch signal and a resetting signal; receiving the gate controlled switch signal and the resetting signal and performing a logic 'or' operation on the gate controlled switch signal and the resetting signal to output corresponding signals; delaying the output signals and outputting the signals; keeping or shutting off an output clock signal according to the output signals and an external clock signal. The output clock is shut off in the stage when the reset circuit repeals the resetting signal, the synchronous timing closure difficulty is reduced, the circuit can be changed simply, the workload is small, and the risk is low.
Description
Technical field
The present invention relates to reset control technology field, particularly relate to a kind of reset circuit and circuit reset method.
Background technology
Along with the operating frequency of digit chip is more and more higher, to chip timing Design, personnel have higher requirement.Because chip needs the frequency gets higher of work, not only the timing closure of clock circuit becomes difficulty, and the reset circuit design of comparatively easily convergence is in the past also difficult all the more.And, in digit chip, major part adopts asynchronous reset effective, the method for designing that synchronous reset is cancelled, so circuit realiration engineer needs the reset signal of the reset terminal of each register of close inspection whether to meet the time resetting and set up and reset maintenance relative to the time on clock edge when reset is cancelled, once not meet the time resetting and set up and reset maintenance, chip may be caused normally to work.
Summary of the invention
In view of the above problems, the invention provides and a kind ofly overcome the problems referred to above or the reset circuit solved the problem at least partly and circuit reset method.
The invention provides a kind of reset circuit, described reset circuit comprises: OR circuit, for receiving gate switching signal and reset signal, and carries out logical "or" computing to described gate controlled switch signal and described reset signal, to export corresponding signal; Delay circuit, exports after the signal for described OR circuit being exported postpones again; Clock gating circuit, the clock signal for the signal that exports according to described delay circuit and outside keeps or turns off the clock signal exporting operating circuit to.
Wherein, latch, for receiving and latching the signal exported by described delay circuit; AND circuit, the clock signal for the signal that exports described latch and described outside carries out logic "and" operation, to keep or to turn off the clock signal exporting described operating circuit to.
Wherein, when described gate controlled switch signal or described reset signal are useful signal, described OR circuit exported effective closedown clock signal and export described clock gating circuit to after described delay circuit time delay a period of time, and described clock gating circuit receives described effective closedown clock signal to turn off the clock signal exporting described operating circuit to; When described gate controlled switch signal and described reset signal are invalid signals, described OR circuit exported invalid closedown clock signal and export described clock gating circuit to after described delay circuit time delay a period of time, and described clock gating circuit receives described invalid closedown clock signal to keep exporting to the clock signal of described operating circuit.
The present invention also provides a kind of circuit reset method, and described method comprises: input gate switching signal and reset signal; Receive gate switching signal and reset signal, and logical "or" computing is carried out to export corresponding signal to described gate controlled switch signal and described reset signal; The signal of described output is carried out time delay; Keep according to the signal of described time delay and the clock signal of outside or turn off the clock signal exported.
Wherein, the clock signal of the described signal according to described time delay and outside keeps or turns off the step of clock signal exported comprising: receive and latch the signal of described time delay; Logic "and" operation is carried out to the signal of described latch and the clock signal of described outside, to keep or to turn off the clock signal exported.
Wherein, when described gate controlled switch signal or described reset signal are useful signal, export effective closedown clock signal and export after time delay a period of time, turning off according to the clock signal of described outside and the effective closedown clock signal of described time delay the clock signal exported; When described gate controlled switch signal and described reset signal are invalid signals, export invalid closedown clock signal and export after described delay circuit time delay a period of time, keeping the clock signal exported according to the closedown clock signal of the clock signal of described outside and the invalid of described time delay.
A kind of reset circuit provided by the invention and circuit reset method, delay circuit is increased between OR circuit and clock gating circuit, by the gate controlled switch signal of OR circuit computing and reset signal bear results and after the time delay of delay circuit, export door control clock circuit to, to keep or to turn off the clock signal exported.Thus, make the stage that reset circuit is cancelling reset signal turn off the clock exported, reduce synchronous reset timing closure difficulty, and simple to the change of circuit, workload is little, risk is little.
Accompanying drawing explanation
Fig. 1 is the high-level schematic functional block diagram of the reset circuit in embodiment of the present invention;
Fig. 2 is the structural representation of the clock gating circuit in embodiment of the present invention;
Fig. 3 is the signal timing diagram in embodiment of the present invention;
Fig. 4 is the schematic flow sheet of the circuit reset method in embodiment of the present invention.
Label declaration:
Reset single channel 10
OR circuit 11
Input 110,111
Delay circuit 12
Clock gating circuit 13
Latch 130
AND circuit 131
Input 130a, 130b, 131a, 131b, 132
Operating circuit 14
Embodiment
By describing technology contents of the present invention, structural feature in detail, realized object and effect, accompanying drawing is coordinated to be explained in detail below in conjunction with execution mode.
ACE bus protocol: ACE agreement is the consistency Extended Protocol (ACE) of ARM company AMBA 4 bus, can be implemented in that to realize data between multiple CPU processor completely the same, can utilize high-speed cache better and simplify software development.
Cache: cache memory (cache) is the memory be present between main memory and CPU, be made up of static storage chip (SRAM), capacity is smaller but speed is more much higher than main memory, close to the speed of CPU.
Refer to Fig. 1, be the high-level schematic functional block diagram of the reset circuit in embodiment of the present invention, this reset circuit 10 comprises OR circuit 11, delay circuit 12, clock gating circuit 13 and operating circuit 14.This reset circuit 10 has been provided external timing signal, such as, and clock signal of system, and external reset signal and gate controlled switch signal.This external reset signal is used to initial work circuit, such as this operating circuit 14.Particularly, this OR circuit 11 is connected successively with this delay circuit 12, clock gating circuit 13 and operating circuit 14.Outside clock signal is applied to the input 132 of this clock gating circuit 13, and gate controlled switch signal and outside reset signal are applied to the input 110,111 of this OR circuit 11 respectively.
This OR circuit 11 receives this gate controlled switch signal and this reset signal, and logical "or" computing is carried out to this gate controlled switch signal and this reset signal, clock signal is closed to export, that is, any one signal in this gate controlled switch signal and this reset signal can control when being useful signal to close clock signal.Wherein, the corresponding useful signal of this closedown clock signal (effective gate controlled switch signal or effective reset signal).
This delay circuit 12 exports clock gating circuit 13 to after postponing for the cut out clock signal this OR circuit 11 produced again, to guarantee that reset signal cancels rear (invalid reset signal) and through after a period of time, this closedown clock signal just can be output to this clock gating circuit 13.Wherein, this delay circuit 12 can be formed with the series connection of buffer or register.
This clock gating circuit 13 controls for the clock signal of the closedown clock signal that exports according to this delay circuit 12 and outside the clock signal exporting this operating circuit 14 to, thus keeps or turn off the clock signal of this operating circuit 14.
Please refer to Fig. 2, it is the structural representation of the clock gating circuit in embodiment of the present invention.This clock gating circuit 13 comprises latch 130 and AND circuit 131, outside clock signal is applied to an input 130a of this latch 130 and input 131a of this AND circuit 131 simultaneously, and this closedown clock signal is through after-applied another input 130b to this latch 130 of time-lag action of this delay circuit 12.This latch 130 outputs to another input 131b of this AND circuit 131 after latching this cut out clock signal and this clock signal, this AND circuit 131 exports corresponding clock signal after carrying out logic "and" operation according to the signal that two inputs 131a, 131b input.Particularly, export when clock signal is 1 upon closing and turn off clock signal, export when clock signal is 0 upon closing and keep clock signal.
Referring to Fig. 3, is the signal timing diagram in embodiment of the present invention.The specific works principle of this reset circuit 10 is as described below.Clock signal inputs to this clock gating circuit 13 constantly, when reset signal becomes useful signal and after duration section t1, gate switching signal also becomes useful signal, due to the time-lag action of delay circuit 12, just closedown clock signal is exported to clock gating circuit 13 after the time delay t2 time, therefore, after experiencing the t2 time, this Clock gating gating circuit 13 just controls the clock signal closedown exporting operating circuit 14 to.When after the t3 time, reset signal becomes invalid signals, in the t4 time period because gate controlled switch signal is still useful signal, therefore this OR circuit 11 receives effective gate controlled switch signal and invalid reset signal, exports effective gate controlled switch signal after logical "or" computing.But, due to the time-lag action of delay circuit 12, this effective gate controlled switch signal is delayed by and exports this clock gating circuit 13 to.Therefore, become in the t4 time period (time of delay of delay circuit 12) of invalid signals in reset signal, this clock gating circuit 13 still controls to close the clock signal exporting operating circuit 14 to.When after the t4 time period, when this gate controlled switch signal becomes invalid signals, this OR circuit 11 exports invalid clock shutdown signal to delay circuit 12 according to invalid gate controlled switch signal and invalid reset signal, equally due to the time-lag action of delay circuit 12, after making invalid clock shutdown signal be delayed by the t5 time, just export this clock gating circuit 13 to.Therefore, within the t5 time period, this clock gating circuit 13 still keeps the clock signal exporting operating circuit 14 to be closed condition, and after the t5 time period, receive this invalid clock shutdown signal.This clock gating circuit 13 controls to open the clock signal exporting operating circuit 14 to according to this invalid clock shutdown signal.Therefore, by operation principle as above, this reset circuit 10, when cancelling effective reset signal, can ensure that output clock does not at once overturn recovery, and recovers output clock after a period of time when cancelling effective reset signal and gate-control signal.
Fig. 4 is the schematic flow sheet of the circuit reset method in embodiment of the present invention.
Step S20, input gate switching signal and reset signal;
Step S21, receives gate switching signal and reset signal, and carries out logical "or" computing to export corresponding signal to this gate controlled switch signal and this reset signal;
Step S22, carries out time delay by the signal of this output;
Step S23, keeps according to the signal of this time delay and the clock signal of outside or turns off the clock signal exporting operating circuit to.
Particularly, step S23 is in particular: receive and latch the signal of this time delay, and carrying out logic "and" operation to the signal of this latch and the clock signal of this outside, to keep or to turn off the clock signal to operating circuit exported.
Wherein, when this gate controlled switch signal and/or reset signal are useful signal, export effective clock shutdown signal and time delay a period of time, turn off according to the clock signal of this outside and the effective clock shutdown signal of this time delay the clock signal exported; When this gate controlled switch signal and this reset signal are invalid signals, export invalid clock shutdown signal this time delay a period of time, keep the clock signal exported according to the clock shutdown signal of the clock signal of outside and the invalid of this time delay.
A kind of reset circuit provided by the invention and circuit reset method, delay circuit is increased between OR circuit and clock gating circuit, by the gate controlled switch signal of OR circuit computing and reset signal bear results and after the time delay of delay circuit, export door control clock circuit to, to keep or to turn off the clock signal exported.Thus, make the stage that reset circuit is cancelling reset signal turn off the clock exported, reduce synchronous reset timing closure difficulty, and simple to the change of circuit, workload is little, risk is little.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (6)
1. a reset circuit, is characterized in that, described reset circuit comprises:
OR circuit, for receiving gate switching signal and reset signal, and carries out logical "or" computing to described gate controlled switch signal and described reset signal, to export corresponding signal;
Delay circuit, exports after the signal for described OR circuit being exported postpones again;
Clock gating circuit, the clock signal for the signal that exports according to described delay circuit and outside keeps or turns off the clock signal exporting operating circuit to.
2. reset circuit as claimed in claim 1, it is characterized in that, described clock gating circuit comprises:
Latch, for receiving and latching the signal exported by described delay circuit;
AND circuit, the clock signal for the signal that exports described latch and described outside carries out logic "and" operation, to keep or to turn off the clock signal exporting described operating circuit to.
3. reset circuit as claimed in claim 1 or 2, it is characterized in that, when described gate controlled switch signal or described reset signal are useful signal, described OR circuit exported effective closedown clock signal and export described clock gating circuit to after described delay circuit time delay a period of time, and described clock gating circuit receives described effective closedown clock signal to turn off the clock signal exporting described operating circuit to;
When described gate controlled switch signal and described reset signal are invalid signals, described OR circuit exported invalid closedown clock signal and export described clock gating circuit to after described delay circuit time delay a period of time, and described clock gating circuit receives described invalid closedown clock signal to keep exporting to the clock signal of described operating circuit.
4. a circuit reset method, is characterized in that, described method comprises:
Input gate switching signal and reset signal;
Receive gate switching signal and reset signal, and logical "or" computing is carried out to export corresponding signal to described gate controlled switch signal and described reset signal;
The signal of described output is carried out time delay;
Keep according to the signal of described time delay and the clock signal of outside or turn off the clock signal exported.
5. circuit reset method as claimed in claim 4, is characterized in that, the step of the clock signal that clock signal keeps or shutoff exports of the described signal according to described time delay and outside comprises:
Receive and latch the signal of described time delay;
Logic "and" operation is carried out to the signal of described latch and the clock signal of described outside, to keep or to turn off the clock signal exported.
6. the circuit reset method as described in claim 4 or 5, it is characterized in that, when described gate controlled switch signal or described reset signal are useful signal, export effective closedown clock signal and export after time delay a period of time, turning off according to the clock signal of described outside and the effective closedown clock signal of described time delay the clock signal exported;
When described gate controlled switch signal and described reset signal are invalid signals, export invalid closedown clock signal and export after described delay circuit time delay a period of time, keeping the clock signal exported according to the closedown clock signal of the clock signal of described outside and the invalid of described time delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410461058.6A CN104242885A (en) | 2014-09-11 | 2014-09-11 | Reset circuit and circuit resetting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410461058.6A CN104242885A (en) | 2014-09-11 | 2014-09-11 | Reset circuit and circuit resetting method |
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| Publication Number | Publication Date |
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| CN104242885A true CN104242885A (en) | 2014-12-24 |
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| CN201410461058.6A Pending CN104242885A (en) | 2014-09-11 | 2014-09-11 | Reset circuit and circuit resetting method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105958982A (en) * | 2016-04-26 | 2016-09-21 | 福州瑞芯微电子股份有限公司 | Circuit and method of bring clken signals forward |
| CN108647480A (en) * | 2018-07-16 | 2018-10-12 | 珠海市微半导体有限公司 | A kind of clock network circuit |
| CN110962602A (en) * | 2019-04-15 | 2020-04-07 | 宁德时代新能源科技股份有限公司 | Load holding circuit applied to battery management system |
| CN114546083A (en) * | 2020-11-26 | 2022-05-27 | 中移物联网有限公司 | Reset synchronizer circuit and clock gating method thereof |
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| CN1588639A (en) * | 2004-08-18 | 2005-03-02 | 大唐微电子技术有限公司 | Reset method and reset system for integrated circuit |
| CN101989848A (en) * | 2009-08-03 | 2011-03-23 | 杭州国芯科技股份有限公司 | Clock generating circuit |
| US20120062282A1 (en) * | 2010-09-10 | 2012-03-15 | Samsung Electronics Co., Ltd. | Clock management unit and method of managing a clock signal |
| CN103684423A (en) * | 2012-09-25 | 2014-03-26 | 上海华虹集成电路有限责任公司 | Variable synchronous clock frequency division circuit |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1588639A (en) * | 2004-08-18 | 2005-03-02 | 大唐微电子技术有限公司 | Reset method and reset system for integrated circuit |
| CN101989848A (en) * | 2009-08-03 | 2011-03-23 | 杭州国芯科技股份有限公司 | Clock generating circuit |
| US20120062282A1 (en) * | 2010-09-10 | 2012-03-15 | Samsung Electronics Co., Ltd. | Clock management unit and method of managing a clock signal |
| CN103684423A (en) * | 2012-09-25 | 2014-03-26 | 上海华虹集成电路有限责任公司 | Variable synchronous clock frequency division circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958982A (en) * | 2016-04-26 | 2016-09-21 | 福州瑞芯微电子股份有限公司 | Circuit and method of bring clken signals forward |
| CN105958982B (en) * | 2016-04-26 | 2018-07-20 | 福州瑞芯微电子股份有限公司 | The circuit and method of clock useful signal in advance |
| CN108647480A (en) * | 2018-07-16 | 2018-10-12 | 珠海市微半导体有限公司 | A kind of clock network circuit |
| CN110962602A (en) * | 2019-04-15 | 2020-04-07 | 宁德时代新能源科技股份有限公司 | Load holding circuit applied to battery management system |
| CN110962602B (en) * | 2019-04-15 | 2021-06-15 | 宁德时代新能源科技股份有限公司 | Load holding circuit applied to battery management system |
| CN114546083A (en) * | 2020-11-26 | 2022-05-27 | 中移物联网有限公司 | Reset synchronizer circuit and clock gating method thereof |
| CN114546083B (en) * | 2020-11-26 | 2023-07-21 | 中移物联网有限公司 | Reset synchronizer circuit and clock gating method thereof |
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Address after: 350003 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant after: FUZHOU ROCKCHIP ELECTRONICS CO., LTD. Address before: 350003 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant before: Fuzhou Rockchip Semiconductor Co., Ltd. |
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Application publication date: 20141224 |
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