CN105958982A - Circuit and method of bring clken signals forward - Google Patents
Circuit and method of bring clken signals forward Download PDFInfo
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- CN105958982A CN105958982A CN201610264233.1A CN201610264233A CN105958982A CN 105958982 A CN105958982 A CN 105958982A CN 201610264233 A CN201610264233 A CN 201610264233A CN 105958982 A CN105958982 A CN 105958982A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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Abstract
The invention provides a circuit and a method of bring clken signals forward. The circuit comprises a synchronization unit, a circulating accumulator, a Clken frequency division threshold determining unit, a standard frequency division threshold determining unit, an OR gate, an inverter, an AND gate, and an ICG gating unit. The synchronization unit is connected with a source clock, a frequency division coefficient, the Clken frequency division threshold determining unit, and the standard frequency division threshold determining unit. The circulating accumulator is respectively connected with the source clock, the Clken frequency division threshold determining unit, a standard frequency division threshold determining unit. The Clken frequency division threshold determining unit is used to output clken signals of a row ahead. The OR gate is used to respectively receive power supply domain switch state signals and clock switch control signals, is connected with the Enable end of the ICG gating unit by the inverter and the AND gate, and is used to enable the ICG gating unit to generate clk_out signals. The clken becomes effective ahead of a low frequency clock domain, and then ever module can run in highest efficiency.
Description
Technical field
The present invention relates to a kind of chip technology, particularly to circuit and the side of a kind of clock useful signal in advance
Method.
Background technology
Circuit function in designing along with chip gets more and more, and each module is not to the demand of frequency
The same, such as modules A is the highest can be operated in 200MHz, and module B is the highest can be operated in
100MHz, in traditional solution, only uses a clock, and allows all circuit operate in
Under the clock frequency that in all modules, running frequency is minimum, so can simplify design difficulty.But
In order to allow all modules can be operated in the highest frequency of oneself with raising system entirety in current techniques
Performance, but so increasing chip occur substantial amounts of when being operated in same phase different frequency
Circuit module below clock, but so bring again a new problem, it is simply that the electricity between different frequency
The most how road signal is carried out, and the usual solution of current techniques is to complete letter by handshake mode
Number mutual, such as modules A sends signal to B, first needs to send a request signal in A clock zone,
At the clock acquisition of module B to after the request signal of A, use the clock zone of B to send and receive confirmation letter
Number to A, then the clock acquisition of A clock zone then can send next information after confirmation signal.This
The shortcoming of the mode of kind is exactly clearly that efficiency is the lowest, can not complete the most mutual by each timeticks.
In order to solve this problem, current a kind of new clock zone interactive mode is suggested, and uses exactly
It is mutual that clken (clock is effective) signal carries out the signal between different frequency same phase clock zone, specifically side
Method is to produce clken (clock is an effective) signal when of low-frequency clock generation simultaneously, and this signal send
To high frequency clock domain be used for notifying high frequency clock domain which high frequency clock along time low-frequency clock effective, high
Frequently low frequency clock domain signal is sampled by clock zone on this basis, i.e. completes data interaction.
But current Clken data interaction technology also has one disadvantage in that, it is simply that due to clock generation circuit
After producing the depositor output clken signal of clken, this signal can be connected to a lot of of high frequency clock domain
Depositor input, due to clock generation circuit usually with other circuit in chip layout distant, hold
Easily cause clken signal and cause timing path long because cabling is long, thus easily affect high frequency clock
The highest frequency of territory circuit.
As it is shown in figure 1, be the current latest version high-performance ARM CPU requirement schematic diagram to clock, main
Wanting the sequential of illustratively clken signal, the CLK in figure is high frequency clock, and ACLKM is low frequency
Clock, ACLKENM is clock useful signal, it can be seen that ARM CPU requirement ACLKENM
Need more effective than ACLKM carries previous clk cycle.
Summary of the invention
The technical problem to be solved in the present invention, is to provide circuit and the side of a kind of clock useful signal in advance
Method, comes into force a clken row before low frequency clock domain is effectively, increases by one the most in a transmission path
It is then sent through targeted high frequency clock zone circuit after level depositor sampling, is used for interrupting timing path with this, makes
It does not interferes with the maximum running frequency of high frequency clock domain.
Circuit of the present invention is achieved in that the circuit of a kind of clock useful signal in advance, single including synchronizing
Unit, cycle accumulor device, Clken frequency dividing thresholding judging unit, standard frequency dividing thresholding judging unit or door,
Phase inverter and door and ICG gating unit；
Described lock unit connect source clock, divide ratio, described Clken frequency dividing thresholding judging unit and
Described standard frequency dividing thresholding judging unit；
Described cycle accumulor device connects source clock, described Clken frequency dividing thresholding judging unit and institute respectively
State standard frequency dividing thresholding judging unit；
The clken signal of a described Clken frequency dividing thresholding judging unit output row in advance；
Described or door receives power domain switch state signal and clock switch control signal respectively, and by anti-
Phase device connects described and door, described reconnect with door described in state standard and divide thresholding judging unit and described
The Enable end of ICG gating unit, makes described ICG gating unit produce clk_out signal；
Described ICG gating unit is also connected with source clock.
Further, described Clken frequency dividing thresholding judging unit farther includes the frequency dividing system being sequentially connected with
The number unit that subtracts, comparator unit and level output unit；And divide ratio subtracts one, and unit is also connected with institute
Stating lock unit, described comparator unit is also connected with the output of described cycle accumulor device.
Further, described standard frequency dividing thresholding judging unit farther include the divide ratio unit that subtracts,
First comparator unit, the second comparator unit, low level zero location and level output unit；
The output of described cycle accumulor device connects described first comparator unit and the second comparator list respectively
Unit；
Described divide ratio subtracts one, and unit connects described lock unit and described first comparator unit respectively；
Described second comparator unit connects described low level zero location and described level output unit respectively.
The inventive method is achieved in that a kind of method of clock useful signal in advance, need to provide this
Bright described circuit, described method includes:
(1) described lock unit uses source clock divide ratio carries out two-stage synchronization process and is sent to institute
State standard frequency dividing thresholding judging unit；
Described cycle accumulor device uses source clock to carry out counting and adds up, and accumulated value is started from scratch cumulative, and will
Accumulated value is sent to described standard frequency dividing thresholding judging unit and described Clken divides thresholding judging unit；
(2) after the divide ratio after described standard frequency dividing thresholding judging unit receives accumulated value and synchronizes,
Control described cycle accumulor device and carry out back to zero operation, and be responsible for output output clken and control clock
Enable source signal；
Described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, produces and exports clken
Signal；
(3) described or goalkeeper's power domain on off state and clock switch control two signals and carry out at logic
It is sent to and door through phase inverter after reason；
(4) after exporting with goalkeeper's control signal and thresholding judging unit described in, signal carries out logical AND process
After be sent to the Enable end of described ICG gating unit；
(5) the described ICG gating unit control signal according to Enable end and the source clock of CK end
Produce a clk_out signal；The sequential produced is: when the rising edge of CK end samples Enable be
Gao Shi, can deliver to clk_out outfan by back to back for the clock of a CK signal high level.
Further, in described step (2), reception is tired out by described standard frequency dividing thresholding judging unit
Value added and divide ratio judges, when the value that accumulated value subtracts equal to divide ratio, follows described in control
Ring accumulator carries out cumulative back to zero operation；And when accumulated value is 0, the output of described cycle accumulor device is believed
Number being set to 1, the original state of output clock is zero；
Described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, is frequency dividing system at accumulated value
Output signal is set to during the value that number subtracts one 1, and the original state of output clock is zero, the letter then produced
Number it is exactly clken signal.
Further, in described step (4), described power domain on off state and clock switch control two
Individual signal is all that high level is effective, represents respectively and closes power domain power supply and close clock control, use or
Door achieve any one control for high level effective time, output result be just high, if two control to believe
Number it is all invalid low level, then or door is output as low, is then passed through described phase inverter, makes level reverse.
Further, described Clken frequency dividing thresholding judging unit farther includes the frequency dividing system being sequentially connected with
The number unit that subtracts, comparator unit and level output unit；And divide ratio subtracts one, and unit is also connected with institute
Stating lock unit, described comparator unit is also connected with the output of described cycle accumulor device.
Further, described standard frequency dividing thresholding judging unit farther include the divide ratio unit that subtracts,
First comparator unit, the second comparator unit, low level zero location and level output unit；
The output of described cycle accumulor device connects described first comparator unit and the second comparator list respectively
Unit；
Described divide ratio subtracts one, and unit connects described lock unit and described first comparator unit respectively；
Described second comparator unit connects described low level zero location and described level output unit respectively.
Present invention have the advantage that
1. a clken row before low frequency clock domain is effectively is come into force, then in transmission path by the present invention
It is then sent through targeted high frequency clock zone circuit, when being used for interrupting with this after the sampling of middle increase one-level depositor
Sequence path so that it is do not interfere with the maximum running frequency of high frequency clock domain；
2. the present invention uses the signal of clken alternately, and interactive efficiency is higher；
3, in the present invention, each module can operate in highest frequency.
Accompanying drawing explanation
The present invention is further illustrated the most in conjunction with the embodiments.
Fig. 1 is a kind of high-performance ARM CPU requirement schematic diagram to clock in prior art.
Fig. 2 is the theory structure block diagram that the present invention shifts to an earlier date clock useful signal circuit.
Fig. 3 is that the Clken that the present invention shifts to an earlier date in clock useful signal circuit divides the former of thresholding judging unit
Reason structured flowchart.
Fig. 4 is that the standard that the present invention shifts to an earlier date in clock useful signal circuit divides the former of thresholding judging unit
Reason structured flowchart.
Fig. 5 is the effect explanatory diagram of the present invention.
Detailed description of the invention
Refer to shown in Fig. 2, be a present invention shift to an earlier date clock useful signal the preferable enforcement of circuit
Example, it includes that lock unit 100, cycle accumulor device 200, Clken divide thresholding judging unit
300, standard frequency dividing thresholding judging unit 400 or door 500, phase inverter 600 and door 700 and ICG
Gating unit 800；
Described lock unit 100 connects source clock, divide ratio, described Clken frequency dividing thresholding judgement list
Unit 300 and described standard frequency dividing thresholding judging unit 400；
Described cycle accumulor device 200 connects source clock respectively, described Clken divides thresholding judging unit 300
And described standard frequency dividing thresholding judging unit 400；
The clken signal of a described Clken frequency dividing thresholding judging unit 300 output row in advance；
Described or door 500 receives power domain switch state signal and clock switch control signal respectively, and leads to
Cross phase inverter 600 and connect described with door 700, described reconnect with door 700 described in state standard frequency dividing thresholding
Judging unit 400 and the Enable end of described ICG gating unit 800, make described ICG gating mono-
Unit 800 produces clk_out signal；
Described ICG gating unit 800 is also connected with source clock.
Wherein,
Described source clock is the clock before frequency dividing, is connected to accumulator and ICG gating unit and synchronization
Unit；
Described lock unit 100 is responsible for use source clock and divide ratio is carried out two-stage synchronization process to working as
The clock zone of front source clock；Divide ratio is the ratio of frequency dividing, and such as coefficient is 2 and represents 1/2 times
Frequency dividing, coefficient is 3 expression 1/3 times frequency dividing, and coefficient minima is 2；
Use source clock is responsible for by described cycle accumulor device 200, and to carry out counting cumulative, and accumulated value is started from scratch tired
Add, and accumulated value is sent to described standard frequency dividing thresholding judging unit 400, and sentenced by standard frequency dividing thresholding
The control of disconnected unit 400 carries out cumulative back to zero operation；Cumulative back to zero refer to by accumulated value reset and again from
Zero starts to add up；
Control after the responsible accumulated value receiving cycle accumulor device 200 of described standard frequency dividing thresholding judging unit 400
Cycle accumulor device 200 back to zero processed is also responsible for output output clken and controls the enable source signal of clock,
Cumulative back to zero operation is carried out when controlling cycle accumulor device 200 after the value that accumulated value subtracts equal to divide ratio；
And when accumulated value is 0, output signal is set to 1, the original state of output clock is zero, output signal
ICG gating unit 800 it is sent to again after delivering to carry out logical AND operation with door and other control signals
Enable end；；
Described Clken frequency dividing thresholding judging unit 300 is responsible for receiving the cumulative of described cycle accumulor device 200
Value, and exports clken signal. i.e. accumulated value be divide ratio subtract one value time output signal is set to
1, the original state of output clock is zero, and the signal then produced is exactly clken signal；
Described or door 500 is responsible for that power domain on off state and clock switch are controlled two signals and is patrolled
It is sent to and door 700 after collecting or processing；Wherein, power domain on off state and clock switch control two signals
It is all that high level is effective, represents respectively and close power domain power supply and close clock control, use or door 500
Achieve any one control for high level effective time, output result be just height, if two control signals
It is all invalid low level, or door 500 is output as low. it is then passed through a phase inverter 600, allows level
Reversely；
After described and door 700 is responsible for exporting control signal and thresholding judging unit, signal carries out logical AND
The Enable end of described ICG gating unit 800 it is sent to after process；Wherein,
Described ICG gating unit 800 is responsible for the control signal according to Enable end and the source of CK end
Clock produces a clk_out signal；Generation sequential is: when the rising edge of CK samples Enable be
Gao Shi, can deliver to clk_out outfan by back to back for the clock of a CK signal high level.
As it is shown on figure 3, what described Clken frequency dividing thresholding judging unit 300 farther included to be sequentially connected with
Divide ratio subtracts one unit 301, comparator unit 302 and level output unit 303；And frequency dividing system
Number subtracts one, and unit 301 is also connected with described lock unit 100, and described comparator unit 302 is also connected with described
The output of cycle accumulor device 200.
Wherein, the described divide ratio unit 301 that subtracts is after subtracting one to the divide ratio value after synchronizing
Output is to comparator unit 302；
Described comparator unit 302 is for being responsible for the divide ratio after will subtracting one and cycle accumulor device 200
Output valve (i.e. accumulated value) exports comparative result after comparing, and is used for cycle accumulor unit 200
The generation of clken；When the output valve of divide ratio and cycle accumulor device 200 is equal by equal comparison
Result is sent to cycle accumulor device 200 and carries out cumulative back to zero operation；
Described level output unit 303 is for comparing in cycle accumulor device 200 output valve and low level zero
When relatively result is equal, exporting the high level allowing gated clock open, otherwise output allows gated clock close
Low level.
As shown in Figure 4, described standard frequency dividing thresholding judging unit 400 farther includes divide ratio and subtracts one
Unit the 401, first comparator unit the 402, second comparator unit 403, low level zero location 404
And level output unit 405；The output of described cycle accumulor device 200 connects described first respectively and compares
Device unit 402 and the second comparator unit 403；Described divide ratio subtracts one, and unit 401 connects institute respectively
State lock unit 100 and described first comparator unit 402；Described second comparator unit 403 is respectively
Connect described low level zero location 404 and described level output unit 405.
Wherein, the described divide ratio unit 401 that subtracts is after subtracting one to the divide ratio value after synchronizing
Output is to the first comparator unit 402；
Described first comparator unit 402 is used for the divide ratio after will subtracting one and cycle accumulor device 200
After output valve compares, output comparative result to cycle accumulor device 200 is for the generation of clken；When
Equal comparative result is sent to cycle accumulor time equal by divide ratio and cycle accumulor device 200 output valve
Device 200 carries out cumulative back to zero operation；
Described second comparator unit 403 is for carrying out cycle accumulor device 300 output valve and low level zero
Compare, and comparative result is sent to level output unit 404；
Described level output unit 404 is for comparing in cycle accumulor device 300 output valve and low level zero
When relatively result is equal, exporting the high level allowing gated clock open, otherwise output allows gated clock close
Low level.
Circuit based on the clock useful signal in advance described in the invention described above, it is effective that the present invention shifts to an earlier date clock
The method of signal includes:
(1) described lock unit uses source clock divide ratio carries out two-stage synchronization process and is sent to institute
State standard frequency dividing thresholding judging unit；
Described cycle accumulor device uses source clock to carry out counting and adds up, and accumulated value is started from scratch cumulative, and will
Accumulated value is sent to described standard frequency dividing thresholding judging unit and described Clken divides thresholding judging unit.
(2) after the divide ratio after described standard frequency dividing thresholding judging unit receives accumulated value and synchronizes,
Control described cycle accumulor device and carry out back to zero operation, and be responsible for output output clken and control clock
Enable source signal；Its detailed process controlled is: described standard frequency dividing thresholding judging unit 400 docks
Accumulated value and the divide ratio received judge, when the value that accumulated value subtracts equal to divide ratio, control
Described cycle accumulor device 300 carries out cumulative back to zero operation；And when accumulated value is 0 by described cycle accumulor
The output signal of device 300 is set to 1, and the original state of output clock is zero.
Described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, produces and exports clken
Signal；Specifically: described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, cumulative
Output signal is set to during the value that value subtracts for divide ratio 1, and the original state of output clock is zero, so
The signal of rear generation is exactly clken signal.
(3) described or goalkeeper's power domain on off state and clock switch control two signals and carry out at logic
It is sent to and door through phase inverter after reason.
(4) after exporting with goalkeeper's control signal and thresholding judging unit described in, signal carries out logical AND process
After be sent to the Enable end of described ICG gating unit；Wherein, described power domain on off state and time
Two signals of clock on-off control are all that high level is effective, when representing closedown power domain power supply respectively and close
Clock system, use or door achieve any one control for high level effective time, output result be just height,
If two control signals are all invalid low level, then or door is output as low, it is then passed through described anti-phase
Device, makes level reverse.
(5) the described ICG gating unit control signal according to Enable end and the source clock of CK end
Produce a clk_out signal；The sequential produced is: when the rising edge of CK end samples Enable be
Gao Shi, can deliver to clk_out outfan by back to back for the clock of a CK signal high level.
Again as it is shown in figure 5, as can be seen from the figure: source clock CK after the circuit of the present invention, meeting
Produce two outputs clock useful signal clken and clk_out, clock useful signal clken may be used for
Mutual for clock zone to high frequency clock CK clock zone, clk_out is for low frequency clock domain clk_out
Clock zone is as work clock, and wherein clken can be more effective, with this than clk_out carries the previous CK cycle
For interrupting timing path so that it is do not interfere with the maximum running frequency of high frequency clock domain.
Although the foregoing describing the detailed description of the invention of the present invention, but it is familiar with the technology people of the art
Member should be appreciated that our described specific embodiment is merely exemplary rather than for this
The restriction of bright scope, those of ordinary skill in the art are in the equivalence made according to the spirit of the present invention
Modify and change, all should contain in the scope of the claimed protection of the present invention.
Claims (8)
1. the circuit shifting to an earlier date clock useful signal, it is characterised in that: include lock unit, circulation
Accumulator, Clken frequency dividing thresholding judging unit, standard frequency dividing thresholding judging unit or door, phase inverter,
With door and ICG gating unit；
Described lock unit connect source clock, divide ratio, described Clken frequency dividing thresholding judging unit and
Described standard frequency dividing thresholding judging unit；
Described cycle accumulor device connects source clock, described Clken frequency dividing thresholding judging unit and institute respectively
State standard frequency dividing thresholding judging unit；
The clken signal of a described Clken frequency dividing thresholding judging unit output row in advance；
Described or door receives power domain switch state signal and clock switch control signal respectively, and by anti-
Phase device connects described and door, described reconnect with door described in state standard and divide thresholding judging unit and described
The Enable end of ICG gating unit, makes described ICG gating unit produce clk_out signal；
Described ICG gating unit is also connected with source clock.
The circuit of clock useful signal in advance the most according to claim 1, it is characterised in that: institute
State the Clken frequency dividing thresholding judging unit divide ratio that farther includes the to be sequentially connected with unit that subtracts, compare
Device unit and level output unit；And divide ratio subtracts one unit is also connected with described lock unit, described
Comparator unit is also connected with the output of described cycle accumulor device.
The circuit of clock useful signal in advance the most according to claim 1, it is characterised in that: institute
State standard frequency dividing thresholding judging unit farther include the divide ratio unit that subtracts, the first comparator unit,
Second comparator unit, low level zero location and level output unit；
The output of described cycle accumulor device connects described first comparator unit and the second comparator list respectively
Unit；
Described divide ratio subtracts one, and unit connects described lock unit and described first comparator unit respectively；
Described second comparator unit connects described low level zero location and described level output unit respectively.
4. the method shifting to an earlier date clock useful signal, it is characterised in that: provide such as claim 1 institute
The circuit stated, described method includes:
(1) described lock unit uses source clock divide ratio carries out two-stage synchronization process and is sent to institute
State standard frequency dividing thresholding judging unit；
Described cycle accumulor device uses source clock to carry out counting and adds up, and accumulated value is started from scratch cumulative, and will
Accumulated value is sent to described standard frequency dividing thresholding judging unit and described Clken divides thresholding judging unit；
(2) after the divide ratio after described standard frequency dividing thresholding judging unit receives accumulated value and synchronizes,
Control described cycle accumulor device and carry out back to zero operation, and be responsible for output output clken and control clock
Enable source signal；
Described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, produces and exports clken
Signal；
(3) described or goalkeeper's power domain on off state and clock switch control two signals and carry out at logic
It is sent to and door through phase inverter after reason；
(4) after exporting with goalkeeper's control signal and thresholding judging unit described in, signal carries out logical AND process
After be sent to the Enable end of described ICG gating unit；
(5) the described ICG gating unit control signal according to Enable end and the source clock of CK end
Produce a clk_out signal；The sequential produced is: when the rising edge of CK end samples Enable be
Gao Shi, can deliver to clk_out outfan by back to back for the clock of a CK signal high level.
The method of clock useful signal in advance the most according to claim 4, it is characterised in that:
In described step (2), described standard divides the thresholding judging unit accumulated value to receiving and frequency dividing
Coefficient judges, when the value that accumulated value subtracts equal to divide ratio, controls described cycle accumulor device and enters
Row cumulative back to zero operation；And when accumulated value is 0, the output signal of described cycle accumulor device is set to 1,
The original state of output clock is zero；
Described Clken frequency dividing thresholding judging unit receives the accumulated value of accumulator, is frequency dividing system at accumulated value
Output signal is set to during the value that number subtracts one 1, and the original state of output clock is zero, the letter then produced
Number it is exactly clken signal.
The method of clock useful signal in advance the most according to claim 4, it is characterised in that:
In described step (4), described power domain on off state and clock switch control two signals and are all
High level is effective, represents respectively and closes power domain power supply and close clock control, uses or door achieves and appoints
What one control for high level effective time, output result be just height, if two control signals are all invalid
Low level, then or door is output as low, be then passed through described phase inverter, make level reverse.
The method of clock useful signal in advance the most according to claim 4, it is characterised in that: institute
State the Clken frequency dividing thresholding judging unit divide ratio that farther includes the to be sequentially connected with unit that subtracts, compare
Device unit and level output unit；And divide ratio subtracts one unit is also connected with described lock unit, described
Comparator unit is also connected with the output of described cycle accumulor device.
The method of clock useful signal in advance the most according to claim 4, it is characterised in that: institute
State standard frequency dividing thresholding judging unit farther include the divide ratio unit that subtracts, the first comparator unit,
Second comparator unit, low level zero location and level output unit；
The output of described cycle accumulor device connects described first comparator unit and the second comparator list respectively
Unit；
Described divide ratio subtracts one, and unit connects described lock unit and described first comparator unit respectively；
Described second comparator unit connects described low level zero location and described level output unit respectively.
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| CN112052043A (en) * | 2020-08-10 | 2020-12-08 | 烽火通信科技股份有限公司 | Method, device, equipment and storage medium for adapting memory bank parameters of embedded system |
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|---|---|---|---|---|
| CN112052043A (en) * | 2020-08-10 | 2020-12-08 | 烽火通信科技股份有限公司 | Method, device, equipment and storage medium for adapting memory bank parameters of embedded system |
| CN112052043B (en) * | 2020-08-10 | 2022-07-01 | 烽火通信科技股份有限公司 | Method, device, equipment and storage medium for adapting memory bank parameters of embedded system |
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| CN105958982B (en) | 2018-07-20 |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |