CN101989848A - Clock generating circuit - Google Patents
Clock generating circuit Download PDFInfo
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- CN101989848A CN101989848A CN200910101064XA CN200910101064A CN101989848A CN 101989848 A CN101989848 A CN 101989848A CN 200910101064X A CN200910101064X A CN 200910101064XA CN 200910101064 A CN200910101064 A CN 200910101064A CN 101989848 A CN101989848 A CN 101989848A
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Abstract
The invention provides a clock generating circuit comprising a switching signal generating circuit and a clock regenerating circuit. The switching signal generating circuit generates a clock switching signal according to input original clock signal and frequency division ratio signal and outputs the clock switching signal to the clock regenerating circuit; the clock regenerating circuit generates an output clock according to the input original clock signal and the clock switching signal, the switching signal generating circuit comprises a cycle clock switching signal generating circuit, a 1 to 1frequency division judger and a clock switching option circuit, and the clock regenerating circuit comprises a time sequence adjusting circuit and a gating circuit. The invention ensures that the output clock is directly obtained through the gating circuit by the original clock signal, provides identical delay for different frequency division clock signals, is favorable to the stable operation of the system, shortens the path of the clock circuit and lowers the design difficulty.
Description
Technical field
This method belongs to circuit field, particularly a kind of clock generation circuit.
Background technology
Along with the progress of science and technology, electronic product is more and more to the requirement of internal clocking number, and the requirement of clock distribution scheme is also become increasingly complex.Clock generation circuit is the particularly key components of SOC (system on a chip) (SoC) of integrated circuit, and the quality of clock generation circuit design directly affects the stability of a system and product quality.
At present common clock generation circuit structure as shown in Figure 1, form by several frequency-dividing clocks and selector, the input of selector is each sub-frequency clock signal of original clock signal and original clock signal, the selection signal of selector is the frequency dividing ratio signal, is output as the output clock of desired characteristic frequency.
Clock generation circuit as shown in Figure 1, its shortcoming is: the different sub-frequency clock signal that original clock signal produces is through different clock division circuitss, on the one hand, because the time-delay difference in different clocks frequency dividing circuit path, the clock generating signal edge shake that causes system to export when switching clock is unfavorable for system stability work; On the other hand, the path of clock division circuits is very long, causes the difficulty of chip design to increase.
Summary of the invention
At the deficiencies in the prior art, the present invention proposes a kind of clock generation circuit.
A kind of clock generation circuit, it is characterized in that: comprise that switching signal produces circuit and clock regeneration circuit, described switching signal produces original clock signal and the frequency dividing ratio signal generation clock switch signal of circuit according to input, and the clock switch signal is outputed to clock regeneration circuit; Described clock regeneration circuit is according to the original clock signal and the clock switch signal generation output clock of input.
Wherein, the switching signal of described clock generation circuit produces circuit, it is characterized in that: comprise the cycle clock switching signal and produce circuit, 1: 1 frequency division determining device and clock switch and select circuit, described cycle clock switching signal produces original clock signal and the frequency dividing ratio signal generation cycle clock switching signal of circuit according to input, and exports the cycle clock switching signal to clock switch selection circuit; Described 1: 1 frequency division determining device is judged the frequency dividing ratio signal of input, and 1: 1 frequency dividing ratio useful signal will exporting exports clock switch selection circuit to; When the frequency dividing ratio signal was 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was effectively, and when the frequency dividing ratio signal was not 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was invalid; Described clock switch selects circuit when the frequency division useful signal was effective in 1: 1, and the output perseverance is 1 clock switch signal, when the frequency division useful signal was invalid in 1: 1, and output cycle clock switching signal.
The switching signal of described clock generation circuit produces circuit, and it is characterized in that: can produce frequency dividing ratio is 1: the clock switch signal of n (n is the integer more than or equal to 1); When frequency dividing ratio semaphore request generation frequency dividing ratio is 1: 1 clock, can produce constant effective clock switch signal; When the frequency dividing ratio semaphore request produces 1: during the clock of n (n is the integer greater than 1), can produce Cycle Length is the cycle clock switching signal of n original clock length.
Wherein, described switching signal produces circuit, and it is characterized in that: described clock switch signal has a length in one-period be the significant level of original clock Cycle Length;
Wherein, described switching signal produces circuit, it is characterized in that: whether by judging frequency dividing ratio is to select the constant clock switch signal or the clock switch signal in cycle at 1: 1;
The cycle clock switching signal that the switching signal of described clock generation circuit produces in the circuit produces circuit, it is characterized in that: comprise counter and comparator, described counter input connects original clock signal, receives whenever that under the condition that does not reset a clock just increases a counting; The input of device as a comparison of described counter output count signal; Another road of described comparator is input as the frequency dividing ratio signal, comparator compares count signal and frequency dividing ratio signal, when the identical seasonal cycle clock switching signal of count signal with the frequency dividing ratio signal effective, when count signal and frequency dividing ratio signal not simultaneously, make the cycle clock switching signal invalid; The cycle clock switching signal feeds back to the reset terminal of described counter, when the cycle clock switching signal resets to counter when being effective.
Described cycle clock switching signal produces circuit, it is characterized in that: compare with the frequency dividing ratio signal of input by counter, produce the periodic signal (n is the integer greater than 1) of n frequency division.
Wherein, described cycle clock switching signal produces the comparator of circuit, can be subtracter and NOR gate; Also can be XOR and NOR gate.
The clock regeneration circuit of described clock generation circuit, it is characterized by: comprise time sequence adjusting circuit and gating circuit, described time sequence adjusting circuit is according to the phase place of the phase place adjustment cycle clock switch signal of the original clock signal of input, obtain adjusted clock switch signal and export gating circuit to, described gating circuit carries out logical operation with adjusted clock switch signal and original clock signal, obtains exporting clock at last.
Wherein, being characterized as of described adjusted clock switch signal: when the signal hopping edge occurs in original clock signal and is low level;
Wherein, described gating circuit can for or the door, with the door or combinational logic circuit;
Wherein, described clock regeneration circuit is characterized in that: according to the input the cycle clock switching signal whether effective to the input the original clock pulse carry out by or by the processing, finally exported clock;
Wherein, described clock regeneration circuit is characterized in that: be created in the gate-control signal of clock level as gating circuit by time sequence adjusting circuit, low level is effective; When gate-control signal is effective, make input clock pulse pass through and export on the output terminal of clock mouth; When gate-control signal is invalid, close clock pulse, make the output terminal of clock mouth be maintained fixed low level.
Time sequence adjusting circuit in the clock regeneration circuit of described clock generation circuit is a latch, and the input signal of described latch is clock switch signal and original clock signal, and output signal is adjusted clock switch signal.
Time sequence adjusting circuit in the clock regeneration circuit of described clock generation circuit also can be several delay units that is in series.
A kind of clock generation circuit of the present invention, the advantage that tool is following: original clock signal is through directly obtaining the output clock behind the gating circuit, the different sub-frequency clock signal that is produced is through the path of identical gating circuit, so the time-delay of different sub-frequency clock signals is identical, can not cause system when switching clock, to produce the shake of clock edge, help system stability work; And the path of clock circuit is very short, reduces design difficulty.
Description of drawings:
The structural representation of the existing clock generation circuit of Fig. 1.
The structural representation of Fig. 2 clock generation circuit of the present invention.
Switching signal in Fig. 3 clock generation circuit of the present invention produces the structural representation of circuit.
Switching signal in Fig. 4 clock generation circuit of the present invention produces the structural representation of the clock cycle switching signal generation circuit of circuit.
The structural representation of the clock regeneration circuit in Fig. 5 clock generation circuit of the present invention.
A kind of structural representation of the time sequence adjusting circuit of the clock regeneration circuit in Fig. 6 clock generation circuit of the present invention.
The another kind of structural representation of the time sequence adjusting circuit of the clock regeneration circuit in Fig. 7 clock generation circuit of the present invention.
A signal of Fig. 8 clock generation circuit of the present invention is adjusted exemplary plot.
Another signal of Fig. 9 clock generation circuit of the present invention is adjusted exemplary plot.
Embodiment
Below in conjunction with specific embodiment, the present invention will be further described.
A kind of clock generation circuit, as shown in Figure 2, comprise that switching signal produces circuit and clock regeneration circuit, it is characterized in that: described switching signal produces original clock signal and the frequency dividing ratio signal generation clock switch signal of circuit according to input, and the clock switch signal is outputed to clock regeneration circuit; Described clock regeneration circuit is according to the original clock signal and the clock switch signal generation output clock of input.
The switching signal of described clock generation circuit produces circuit, as shown in Figure 3, comprising the cycle clock switching signal produces circuit, 1: 1 frequency division determining device and clock switch and selects circuit, it is characterized in that: described cycle clock switching signal produces original clock signal and the frequency dividing ratio signal generation cycle clock switching signal of circuit according to input, and exports the cycle clock switching signal to clock switch selection circuit; Described 1: 1 frequency division determining device is judged the frequency dividing ratio signal of input, and 1: 1 frequency dividing ratio useful signal will exporting exports clock switch selection circuit to; When the frequency dividing ratio signal was 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was effectively, and when the frequency dividing ratio signal was not 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was invalid; Described clock switch selects circuit when the frequency division useful signal was effective in 1: 1, and the output perseverance is 1 clock switch signal, when the frequency division useful signal was invalid in 1: 1, and output cycle clock switching signal.
The switching signal of described clock generation circuit produces circuit, and it is characterized in that: can produce frequency dividing ratio is 1: the clock switch signal of n (n is the integer more than or equal to 1); When frequency dividing ratio semaphore request generation frequency dividing ratio is 1: 1 clock, can produce constant effective clock switch signal; When the frequency dividing ratio semaphore request produces 1: during the clock of n (n is the integer greater than 1), can produce Cycle Length is the cycle clock switching signal of n original clock length.
Wherein, described switching signal produces circuit, and it is characterized in that: described clock switch signal has a length in one-period be the significant level of original clock Cycle Length;
Wherein, described switching signal produces circuit, it is characterized in that: whether by judging frequency dividing ratio is to select the constant clock switch signal or the clock switch signal in cycle at 1: 1;
The cycle clock switching signal that the switching signal of described clock generation circuit produces in the circuit produces circuit, as shown in Figure 4, comprise counter and comparator, it is characterized in that: described counter input connects original clock signal, receives whenever that under the condition that does not reset a clock just increases a counting; The input of device as a comparison of described counter output count signal; Another road of described comparator is input as the frequency dividing ratio signal, comparator compares count signal and frequency dividing ratio signal, when the identical seasonal cycle clock switching signal of count signal with the frequency dividing ratio signal effective, when count signal and frequency dividing ratio signal not simultaneously, make the cycle clock switching signal invalid; The cycle clock switching signal feeds back to the reset terminal of described counter, when the cycle clock switching signal resets to counter when being effective.
Described cycle clock switching signal produces circuit, it is characterized in that: compare with the frequency dividing ratio signal of input by counter, produce the periodic signal (n is the integer greater than 1) of n frequency division.
Wherein, described cycle clock switching signal produces the comparator of circuit, can be subtracter and NOR gate; Also can be XOR and NOR gate.
The clock regeneration circuit of described clock generation circuit, as shown in Figure 5, comprise time sequence adjusting circuit and gating circuit, it is characterized by: described time sequence adjusting circuit is according to the phase place of the phase place adjustment cycle clock switch signal of the original clock signal of input, obtain adjusted clock switch signal and export gating circuit to, described gating circuit carries out logical operation with adjusted clock switch signal and original clock signal, obtains exporting clock at last.
Wherein, being characterized as of described adjusted clock switch signal: when the signal hopping edge occurs in original clock signal and is low level;
Wherein, described gating circuit can for or the door, with the door or combinational logic circuit;
Wherein, described clock regeneration circuit is characterized in that: according to the input the cycle clock switching signal whether effective to the input the original clock pulse carry out by or by the processing, finally exported clock;
Wherein, described clock regeneration circuit is characterized in that: be created in the gate-control signal of clock level as gating circuit by time sequence adjusting circuit, low level is effective; When gate-control signal is effective, make input clock pulse pass through and export on the output terminal of clock mouth; When gate-control signal is invalid, close clock pulse, make the output terminal of clock mouth be maintained fixed low level.
Time sequence adjusting circuit in the clock regeneration circuit of described clock generation circuit as shown in Figure 6, can be a latch, and the input signal of described latch is clock switch signal and original clock signal, and output signal is adjusted clock switch signal.
Time sequence adjusting circuit in the clock regeneration circuit of described clock generation circuit as shown in Figure 7, can be several delay units that is in series.
Adopt a signal of clock generation circuit of the present invention to adjust example as shown in Figure 8, adopt another signal of clock generation circuit of the present invention to adjust example as shown in Figure 9.As can be seen, a kind of clock generation circuit of the present invention, the advantage that tool is following: original clock signal is through directly obtaining the output clock behind the gating circuit, the different sub-frequency clock signal that is produced is through the path of identical gating circuit, so the time-delay of different sub-frequency clock signals is identical, can not cause system when switching clock, to produce the shake of clock edge, help system stability work; And the path of clock circuit is very short, reduces design difficulty.
Should be understood that; the above is one embodiment of the present of invention only, is not limited field of the present invention, for the person of ordinary skill of the art; any modification of being made within every the spirit and principles in the present invention, be equal to and replace or improve, all should be included within protection scope of the present invention.
Claims (9)
1. clock generation circuit, it is characterized in that: comprise that switching signal produces circuit and clock regeneration circuit, described switching signal produces original clock signal and the frequency dividing ratio signal generation clock switch signal of circuit according to input, and the clock switch signal is outputed to clock regeneration circuit; Described clock regeneration circuit is according to the original clock signal and the clock switch signal generation output clock of input.
2. the switching signal of clock generation circuit as claimed in claim 1 produces circuit, it is characterized in that: comprise the cycle clock switching signal and produce circuit, 1: 1 frequency division determining device and clock switch and select circuit, described cycle clock switching signal produces original clock signal and the frequency dividing ratio signal generation cycle clock switching signal of circuit according to input, and exports the cycle clock switching signal to clock switch selection circuit; Described 1: 1 frequency division determining device is judged the frequency dividing ratio signal of input, and 1: 1 frequency dividing ratio useful signal will exporting exports clock switch selection circuit to; When the frequency dividing ratio signal was 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was effectively, and when the frequency dividing ratio signal was not 1: 1 frequency division, 1: 1 frequency dividing ratio useful signal of frequency division determining device output in 1: 1 was invalid; Described clock switch selects circuit when the frequency division useful signal was effective in 1: 1, and the output perseverance is 1 clock switch signal, when the frequency division useful signal was invalid in 1: 1, and output cycle clock switching signal.
3. the switching signal of clock generation circuit as claimed in claim 2 produces circuit, and it is characterized in that: can produce frequency dividing ratio is 1: the clock switch signal of n (n is the integer more than or equal to 1); When frequency dividing ratio semaphore request generation frequency dividing ratio is 1: 1 clock, can produce constant effective clock switch signal; When the frequency dividing ratio semaphore request produces 1: during the clock of n (n is the integer greater than 1), can produce Cycle Length is the cycle clock switching signal of n original clock length.
4. the switching signal as claim 2 or 3 described clock generation circuits produces circuit, and it is characterized in that: described clock switch signal has a length in one-period be the significant level of original clock Cycle Length.
5. produce circuit as the switching signal of claim 2 or 3 described clock generation circuits, it is characterized in that: whether by judging frequency dividing ratio is to select the constant clock switch signal or the clock switch signal in cycle at 1: 1.
6. the switching signal of clock generation circuit as claimed in claim 2 produces the cycle clock switching signal generation circuit in the circuit, it is characterized in that: comprise counter and comparator, described counter input connects original clock signal, receives whenever that under the condition that does not reset a clock just increases a counting; The input of device as a comparison of described counter output count signal; Another road of described comparator is input as the frequency dividing ratio signal, comparator compares count signal and frequency dividing ratio signal, when the identical seasonal cycle clock switching signal of count signal with the frequency dividing ratio signal effective, when count signal and frequency dividing ratio signal not simultaneously, make the cycle clock switching signal invalid; The cycle clock switching signal feeds back to the reset terminal of described counter, when the cycle clock switching signal resets to counter when being effective.
7. the switching signal of clock generation circuit as claimed in claim 6 produces the cycle clock switching signal generation circuit in the circuit, it is characterized in that: compare with the frequency dividing ratio signal of input by counter, produce the periodic signal (n is the integer greater than 1) of n frequency division.
8. the clock regeneration circuit of clock generation circuit as claimed in claim 1, it is characterized by: comprise time sequence adjusting circuit and gating circuit, described time sequence adjusting circuit is according to the phase place of the phase place adjustment cycle clock switch signal of the original clock signal of input, obtain adjusted clock switch signal and export gating circuit to, described gating circuit carries out logical operation with adjusted clock switch signal and original clock signal, obtains exporting clock at last.
9. the clock regeneration circuit of clock generation circuit as claimed in claim 8, it is characterized in that: be created in the gate-control signal of clock level as gating circuit by time sequence adjusting circuit, low level is effective; When gate-control signal is effective, make input clock pulse pass through and export on the output terminal of clock mouth; When gate-control signal is invalid, close clock pulse, make the output terminal of clock mouth be maintained fixed low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910101064XA CN101989848A (en) | 2009-08-03 | 2009-08-03 | Clock generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910101064XA CN101989848A (en) | 2009-08-03 | 2009-08-03 | Clock generating circuit |
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| CN101989848A true CN101989848A (en) | 2011-03-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910101064XA Pending CN101989848A (en) | 2009-08-03 | 2009-08-03 | Clock generating circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242885A (en) * | 2014-09-11 | 2014-12-24 | 福州瑞芯微电子有限公司 | Reset circuit and circuit resetting method |
| CN104811187A (en) * | 2014-01-27 | 2015-07-29 | Ls产电株式会社 | Method for generating clock for system operating at rising edge |
| CN105406841A (en) * | 2015-11-20 | 2016-03-16 | 芜湖锐芯电子科技有限公司 | High-precision clock phase control circuit |
| CN105676943B (en) * | 2015-12-31 | 2018-08-17 | 广州中大微电子有限公司 | I/Q demodulation clock circuits in a kind of SoC chip |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
-
2009
- 2009-08-03 CN CN200910101064XA patent/CN101989848A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811187A (en) * | 2014-01-27 | 2015-07-29 | Ls产电株式会社 | Method for generating clock for system operating at rising edge |
| CN104242885A (en) * | 2014-09-11 | 2014-12-24 | 福州瑞芯微电子有限公司 | Reset circuit and circuit resetting method |
| CN105406841A (en) * | 2015-11-20 | 2016-03-16 | 芜湖锐芯电子科技有限公司 | High-precision clock phase control circuit |
| CN105676943B (en) * | 2015-12-31 | 2018-08-17 | 广州中大微电子有限公司 | I/Q demodulation clock circuits in a kind of SoC chip |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
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Application publication date: 20110323 |