CN105676943B - I/Q demodulation clock circuits in a kind of SoC chip - Google Patents
I/Q demodulation clock circuits in a kind of SoC chip Download PDFInfo
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- CN105676943B CN105676943B CN201511033927.6A CN201511033927A CN105676943B CN 105676943 B CN105676943 B CN 105676943B CN 201511033927 A CN201511033927 A CN 201511033927A CN 105676943 B CN105676943 B CN 105676943B
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- counter
- delay
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- branch
- multigroup
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses I/Q demodulation clock circuits in a kind of SoC chip, include I clock generation circuits, time delay module and counter and control circuit module, the time delay module includes multigroup branch switch and delay unit, the output end of the I clock generation circuits is connected to delay unit by branch switch, the output end of the input terminal that multigroup delay unit is sequentially connected in series and exports to counter and control circuit module, the counter and control circuit module is connect with multigroup branch switch control terminal respectively.The present invention reduces circuit using branch switch and runs power consumption, utilize time delay module adjustment phase place, therefore the circuit structure is without improving working frequency and addition phase correction module, and it is limited without bandwidth, circuit structure is simple and can be simplified and optimized to circuit by the methods of module reuse, redundancy section cutting, and chip cost of implementation is reduced.The present invention can be widely applied to electronic circuit field as I/Q demodulation clocks circuit in a kind of SoC chip and method.
Description
Technical field
The present invention relates to electronic circuit field, I/Q demodulation clock circuits in especially a kind of SoC chip.
Background technology
SoC is the abbreviation of System on Chip, i.e. system on chip.As its name suggests, be exactly by system core part, it is such as micro-
Processor, Analog IP core, digital IP kernel and memory etc., are integrated on one chip.Numerous integrated electricity with specific function
In the set to chip piece of road so that SoC chip has the advantages such as small-sized, light weight, multi-functional, high speed and low cost, extensively
Applied to communication, traffic, the fields such as logistics.
Barkhausen criterion is to ensure that the primary condition of loop oscillation, and the loop gain of negative-feedback circuit must satisfy following
Condition：
When the loop gain of negative-feedback circuit meets above-mentioned condition, loop can generate oscillation, conversely, cannot.
I/Q is modulated（Orthogonal modulation）, it is that signal source is divided into two parts, is modulated respectively with carrier wave, two carrier signals
Intersection.I/Q demodulation is to also need the carrier signal that two intersect to be demodulated.I/Q modulation /demodulation is widely used in radio frequency letter
Number phase control system, radar, the applications such as base station receiver.In I/Q modem procedues, the carrier signal of two intersections, we
Referred to as i/q signal, the circuit main method for generating i/q signal at this stage have, two frequency sharing circuits, polyphase structure RC filters
Deng.
Two frequency sharing circuits are exactly to pass through trigger or other circuit structures so that signal often triggers 2 periodic circuit outputs 1
A periodic signal so that signal frequency halves.Therefore the usual circuit needs of orthogonal signalling are generated using two frequency sharing circuits to be operated in
On twice of circuit working signal, and need to carry out phasing to improve precision.
Polyphase structure RC filters, which are mainly connected using resistance with capacitive cross, constitutes ring, this structure constraint in bandwidth,
And signal has decaying.Required capacitance resistance number needs specific simultaneously are determined according to working frequency, are not easy to correct.
Invention content
In order to solve the above-mentioned technical problem, the purpose of the present invention is：There is provided in a kind of SoC chip it is simple in structure, easy to control,
The I/Q demodulation clock circuits of low-power consumption.
The technical solution adopted in the present invention is：I/Q demodulation clock circuits in a kind of SoC chip include that I clocks generate
Circuit, time delay module and counter and control circuit module, the time delay module include multigroup delay branch, the delay branch
Road includes branch switch and delay unit, and the output end of the I clock generation circuits is connected to delay list by branch switch
Member, multigroup delay unit being delayed in branch are sequentially connected in series, last group delay branch in multigroup delay branch
Delay unit output end be connected to counter and the input terminal of control circuit module, the counter and control circuit module
Output end is connect with the branch switch control terminal of multigroup delay branch respectively.
Further, the counter includes with control circuit module：
Register, for storing control information；
Counter is counted for the number in running order delay unit；
Time delay module reset cell, the working condition for resetting delay unit；
Phase correction block carries out phasing for controlling whether；
Preset count unit is used for memory counter preset value；
Operating mode control unit, by control time delay module according to counter preset value work or according to counter based on
Numerical value is adjusted into Mobile state.
Further, when the operating mode control unit works for controlling time delay module according to counter preset value, institute
It states operating mode control unit and multigroup branch switch being delayed in branch is controlled according to counter preset value respectively.
Further, the operating mode control unit is used to control time delay module according to the count value of counter into Mobile state
When adjustment, the branch switch that the operating mode control unit controls in multigroup delay branch is opened successively until counter and control
The input terminal input signal and the output signal of I clock generation circuits of circuit module processed are reversed.
Further, the storage control information in the register includes 1 resetting position, 1 bit correction position, 1 Working mould
Formula position and 4 digit counter presetting bits.
Further, the time delay module includes 30 groups of delay branches.
Further, the I clock generation circuits generate the oscillating current of 13.56MHz.
The beneficial effects of the invention are as follows：Circuit is reduced using branch switch and runs power consumption, using time delay module adjustment phase place,
Therefore the circuit structure is limited without improving working frequency and addition phase correction module, and without bandwidth, circuit structure it is simple and
Circuit can be simplified and optimized by the methods of module reuse, redundancy section cutting, reduces chip cost of implementation.
Description of the drawings
Fig. 1 is electrical block diagram of the present invention；
Fig. 2 is the counter and control circuit module circuit diagram of a specific embodiment of the invention.
Specific implementation mode
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
Referring to Fig.1, I/Q demodulation clock circuits in a kind of SoC chip, include I clock generation circuits, time delay module and meter
Number device and control circuit module, the time delay module include multigroup delay branch, and the delay branch includes branch switch
And delay unit, the output end of the I clock generation circuits are connected to delay unit, multigroup delay branch by branch switch
Delay unit in road is sequentially connected in series, and the delay unit output end of last group delay branch in multigroup delay branch connects
It is connected to counter and the input terminal of control circuit module, the output end of the counter and control circuit module prolongs with multigroup respectively
The branch switch control terminal of Shi Zhilu connects.
The main working process that circuit of the present invention generates I/Q clocks is, when generating stable I using the equivalent circuit of crystal oscillator
Clock, while using the I clocks of generation as the initial clock of Q clocks.Constantly delay unit is added to Q clocks and counted so that when Q
The phase difference of clock and I clocks constantly increases, by judge counter and control circuit module input terminal input signal whether
Reversely, i.e., I/Q clock skews reach 180 °.Counter results divided by 2 can be obtained by this time if phase difference reaches 180 °
I/Q clock phases differ 90 ° of required delay unit numbers.It realizes in circuit divided by 2 function is mainly by register
Result move to right a realization.Assuming that obtaining the delay unit number n needed for 90 ° of phase difference, n is added for initial Q clocks
A delay unit can be obtained and differ 90 ° of Q clocks with I clock phases.And at this moment the control circuit of top receives I/Q clock phases
Whether potential difference reaches 180 ° of feedback, and control circuit is not further added by delay unit number, and the constant phase difference of I/Q clocks is at 90 °.
It is further used as preferred embodiment, the counter includes with control circuit module：
Register, for storing control information；
Counter is counted for the number in running order delay unit；
Time delay module reset cell, the working condition for resetting delay unit；
Phase correction block carries out phasing for controlling whether；
Preset count unit is used for memory counter preset value；
Operating mode control unit, by control time delay module according to counter preset value work or according to counter based on
Numerical value is adjusted into Mobile state.
Above-mentioned counter can be realized with each unit in control circuit module with simple selector and d type flip flop, wherein
One specific implementation circuit schematic diagram it is as shown in Figure 2；Operating mode control unit is defeated by multiple two according to counter results
Enter NAND gate and nor gate is realized and controls the break-make of 30 delay units using the data of 5 bit register positions.
It is further used as preferred embodiment, the operating mode control unit is for controlling time delay module according to counting
When device preset value works, the operating mode control unit controls the branch in multigroup delay branch according to counter preset value respectively
Way switch；I.e. preset value makes delay unit number just so that I/Q clock skews are 90 °, is adjusted again without the later stage.
It is further used as preferred embodiment, the operating mode control unit is for controlling time delay module according to counting
When the count value of device is adjusted into Mobile state, the operating mode control unit controls the branch switch in multigroup delay branch successively
Opening is reversed up to the input terminal input signal and the output signal of I clock generation circuits of counter and control circuit module, this
That is clock calibration process.In the process, important intermediate parameters be judge I/Q clock skews whether the parameter more than 180 °
Clock180Deg；When I/Q clock skews are more than 180 °, Clock180Deg 1, on the contrary it is 0；When Clock180Deg is 1
When, it controls counting module and halves, be added on former Q clocks, generate I/Q clocks difference becomes 90 ° of difference for 180 ° from difference, can
As counter preset value.
It is further used as preferred embodiment, the storage control information in the register includes 1 resetting position, 1
Bit correction position, 1 operating mode position and 4 digit counter presetting bits.
Reset（Resetting position, 1）:If 1, then delay unit number is reset；
On-Off (correction bits, 1):If 1, phase is not corrected, and resets delay unit number, makes to prolong
When cell number perseverance be 0；If 0, phase is allowed to be corrected；
CountOrNot（Operating mode position, 1）:If 1, delay unit number is directly disposed as ClockDelay
The value being arranged in register is incremented by processing without being carried out to delay unit；If 0, allow delay unit number constantly incremental, increases
Phase difference between big I/Q clocks.
ClockDelay（Counter presetting bit, 4）：For memory counter preset value.The function is mainly in view of
Directly setting preset value makes delay unit number just so that I/Q clock skews are 90 ° when chip production, without the later stage
It adjusts again.
It is further used as preferred embodiment, the time delay module includes 30 groups of delay branches.
It is further used as preferred embodiment, the I clock generation circuits generate the oscillating current of 13.56MHz.
It is to be illustrated to the preferable implementation of the present invention, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalents or be replaced under the premise of without prejudice to spirit of that invention
It changes, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (6)
1. I/Q demodulation clocks circuit in a kind of SoC chip, it is characterised in that：Include I clock generation circuits, time delay module and
Counter and control circuit module, the time delay module include multigroup delay branch, and the delay branch includes that branch is opened
It closes and delay unit, the output end of the I clock generation circuits is connected to delay unit, multigroup delay by branch switch
Delay unit in branch is sequentially connected in series, the delay unit output end of last group delay branch in multigroup delay branch
Be connected to counter and the input terminal of control circuit module, the output end of the counter and control circuit module respectively with it is multigroup
The branch switch control terminal connection of delay branch；
The counter includes with control circuit module：
Register, for storing control information；
Counter is counted for the number in running order delay unit；
Time delay module reset cell, the working condition for resetting delay unit；
Phase correction block carries out phasing for controlling whether；
Preset count unit is used for memory counter preset value；
Operating mode control unit, for controlling time delay module according to the work of counter preset value or according to the count value of counter
It is adjusted into Mobile state.
2. I/Q demodulation clock circuits in a kind of SoC chip according to claim 1, it is characterised in that：The operating mode
When control unit works for controlling time delay module according to counter preset value, the operating mode control unit is according to counter
Preset value controls the branch switch in multigroup delay branch respectively.
3. I/Q demodulation clock circuits in a kind of SoC chip according to claim 1, it is characterised in that：The operating mode
When control unit is adjusted according to the count value of counter into Mobile state for controlling time delay module, the operating mode control unit
The branch switch controlled in multigroup delay branch opens the input terminal input signal until counter and control circuit module successively
It is reversed with the output signal of I clock generation circuits.
4. I/Q demodulation clock circuits in a kind of SoC chip according to claim 1, it is characterised in that：In the register
Storage control information include 1 resetting position, 1 bit correction position, 1 operating mode position and 4 digit counter presetting bits.
5. I/Q demodulation clock circuits in a kind of SoC chip according to claim 1, it is characterised in that：The time delay module
Include 30 groups of delay branches.
6. I/Q demodulation clock circuits in a kind of SoC chip according to claim 1, it is characterised in that：The I clocks production
Raw circuit generates the oscillating current of 13.56MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511033927.6A CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511033927.6A CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105676943A CN105676943A (en) | 2016-06-15 |
| CN105676943B true CN105676943B (en) | 2018-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201511033927.6A Expired - Fee Related CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
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| CN106767745B (en) * | 2016-12-09 | 2019-07-12 | 清华大学 | A kind of signal processing method of photoelectric sensor angle measuring system |
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|---|---|---|---|---|
| CN1243619A (en) * | 1997-10-09 | 2000-02-02 | 诺基亚电信公司 | Compensation of delay in linearization loop of power amplifier |
| CN1585262A (en) * | 2003-08-18 | 2005-02-23 | 夏普株式会社 | I/Q demodulation circuit |
| CN1592105A (en) * | 2000-12-21 | 2005-03-09 | 恩益禧电子股份有限公司 | Clock and data restoring circuit and its clock control method |
| CN101527564A (en) * | 2008-03-06 | 2009-09-09 | 瑞昱半导体股份有限公司 | Fractional-neuronal frequency divider and method thereof |
| CN101640524A (en) * | 2009-08-27 | 2010-02-03 | 和芯微电子(四川)有限公司 | Spread spectrum clock generating circuit |
| CN101989848A (en) * | 2009-08-03 | 2011-03-23 | 杭州国芯科技股份有限公司 | Clock generating circuit |
| CN103427798A (en) * | 2013-08-21 | 2013-12-04 | 电子科技大学 | Multiphase clock generation circuit |
-
2015
- 2015-12-31 CN CN201511033927.6A patent/CN105676943B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1243619A (en) * | 1997-10-09 | 2000-02-02 | 诺基亚电信公司 | Compensation of delay in linearization loop of power amplifier |
| CN1592105A (en) * | 2000-12-21 | 2005-03-09 | 恩益禧电子股份有限公司 | Clock and data restoring circuit and its clock control method |
| CN1585262A (en) * | 2003-08-18 | 2005-02-23 | 夏普株式会社 | I/Q demodulation circuit |
| CN101527564A (en) * | 2008-03-06 | 2009-09-09 | 瑞昱半导体股份有限公司 | Fractional-neuronal frequency divider and method thereof |
| CN101989848A (en) * | 2009-08-03 | 2011-03-23 | 杭州国芯科技股份有限公司 | Clock generating circuit |
| CN101640524A (en) * | 2009-08-27 | 2010-02-03 | 和芯微电子(四川)有限公司 | Spread spectrum clock generating circuit |
| CN103427798A (en) * | 2013-08-21 | 2013-12-04 | 电子科技大学 | Multiphase clock generation circuit |
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| CN105676943A (en) | 2016-06-15 |
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Granted publication date: 20180817 Termination date: 20201231 |