CN104124945B - Duty ratio calibrating circuit - Google Patents
Duty ratio calibrating circuit Download PDFInfo
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- CN104124945B CN104124945B CN201410353784.6A CN201410353784A CN104124945B CN 104124945 B CN104124945 B CN 104124945B CN 201410353784 A CN201410353784 A CN 201410353784A CN 104124945 B CN104124945 B CN 104124945B
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Abstract
A duty ratio calibrating circuit comprises a semi-cycle delay circuit, a control signal generating circuit and a triggering circuit. The semi-cycle delay circuit is applicable to semi-cycle delay processing of an input clock so as to generate a first delay clock. The control signal generating circuit is applicable to generating of a control signal according to the input clock, and the control signal is in a first level at a trigger edge moment of the input clock, or is in a second level. The triggering circuit is applicable to generating of an output clock according to the first delay clock and the control signal. The state of the output clock is changed into the second level when the trigger edge of the first delay clock arrives and is changed into the first level when the control signal is in the first level. The duty ratio calibrating circuit is short in stabilizing time.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly to a kind of duty-ratio calibrating circuit.
Background technology
The continuous innovation regenerated with designing technique with the technological change of integrated circuit, the operating rate of chip is continued
Improve.Mean harsher time sequence precision at high speed, the clock performance of system is required also accordingly to improve, one of important
Performance indications be clock dutycycle.As a rule, dutycycle be 50 percent clock for data biography
Broadcast the most favourable.
In actual applications, the clock of system to produce often through phaselocked loop or delay locked loop.Because circuit sets
The deviation of technique and simulation model in mismatch that meter itself produces and chip manufacturing proces, produce after frequency multiplication, synchronization when
Clock tends not to ensure that dutycycle is 50 percent.In addition, in the communication process of clock, equally depositing due in distribution link
In the deviation of system and technique, also the dutycycle causing clock is lacked of proper care.Particularly in frequency applications, the imbalance of dutycycle
Even clock can be made can not normally to overturn, thus causing serious timing error.Therefore, in the field strict to duty-cycle requirement
In conjunction, duty-ratio calibrating circuit (DDC, Duty Cycle Corrector) is added to be very necessary.
Duty-ratio calibrating circuit is widely used in Double Data Rate synchronous DRAM, double sampled analog-to-digital conversion
In the circuit such as device, phaselocked loop and clock and data recovery, to produce the clock that dutycycle is 50 percent, thus ensureing
The normal operation of system and the optimal performance of efficiency.In prior art, duty-ratio calibrating circuit is generally carried out using analog form
Calibration.Detection mode in analog duty-ratio calibrating circuit and adjustment mode are all continuous, thus have calibration accuracy high,
The advantage of adjustable frequency wide ranges.However, adopting feedback arrangement analog duty-ratio calibrating circuit, when needing longer stable more
Between, that is, need the long period could output duty cycle be 50 percent clock.
Content of the invention
What the present invention solved is the problem of analog duty-ratio calibrating circuit stabilization time length.
For solving the above problems, the present invention provides a kind of duty-ratio calibrating circuit, including：Half period delay circuit, control
Signal generating circuit and triggers circuit；
Described half period delay circuit is suitable to input clock be carried out with half period delay process to produce the first delayed clock；
Described control signal produces circuit and is suitable to produce control signal according to described input clock, and described control signal is in institute
The triggering stating input clock is the first level along the moment, otherwise for second electrical level；
Described triggers circuit is suitable to produce output clock according to described first delayed clock and described control signal, described defeated
The state going out clock is updated to described second electrical level when the triggering of described first delayed clock is along arrival, in described control signal
It is updated to described first level during for described first level.
Optionally, described control signal generation circuit includes the first d type flip flop and the first not circuit；
The clock end of described first d type flip flop is suitable to receive described input clock, and the data terminal of described first d type flip flop is fitted
In receiving the first data-signal, the control end of described first d type flip flop is suitable to receive described output clock, a described D triggering
The output end of device connects the input of described first not circuit, and described first data-signal is described second electrical level；
The output end of described first not circuit is suitable to produce described control signal.
Optionally, described triggers circuit includes the second d type flip flop；
The clock end of described second d type flip flop is suitable to receive described first delayed clock, the data of described second d type flip flop
End is suitable to receive the second data-signal, and the control end of described second d type flip flop is suitable to receive described control signal, described 2nd D
The output end of trigger is suitable to produce described output clock, and described second data-signal is described second electrical level.
Optionally, described first level is low level, and described second electrical level is high level.
Optionally, described first level is high level, and described second electrical level is low level.
Optionally, described half period delay circuit includes：Status signal generation unit, status unit and (2 × N)
Individual first delay cell, N >=1 and N are positive integer；
The control end of described first delay cell is suitable to receive Regulate signal, and described Regulate signal is suitable to adjust described first
The time delay of delay cell, the initial delay time of described first delay cell determines according to Td ＜ T0 ÷ (2 × N), wherein,
Td is the initial delay time of described first delay cell, and T0 is the cycle of described input clock；
Described (2 × N) individual first delay cell is in be connected in series structure, and the input of first the first delay cell is suitable to
Receive described input clock, the output end of n-th first delay cell is suitable to produce described first delayed clock, and (2 × N) is individual
The output end of the first delay cell is suitable to produce the second delayed clock；
Described status signal generation unit is suitable to produce state letter according to described input clock and described second delayed clock
Number, described status signal is when the rising edge of described input clock and the rising edge synchronization of described second delayed clock arrive
For high level, otherwise for low level；
Described status unit is suitable to produce described Regulate signal according to described status signal, and described Regulate signal is in institute
The time delay controlling described first delay cell when stating status signal for low level increases, and is high level in described status signal
When control described first delay cell time delay keep constant.
Optionally, described status signal generation unit include the second delay cell, 3d flip-flop, four d flip-flop,
Second not circuit and and gate circuit, described 3d flip-flop and described four d flip-flop are trailing edge d type flip flop；
Described second delay cell is suitable to carry out delay disposal to produce the 3rd delayed clock to described input clock；
The clock end of described 3d flip-flop is suitable to receive described input clock, and the data terminal of described 3d flip-flop is even
Connect the data terminal of described four d flip-flop and be suitable to receive described second delayed clock, the output end of described 3d flip-flop is even
Connect the described first input end with gate circuit；
The clock end of described four d flip-flop is suitable to receive described 3rd delayed clock, the output of described four d flip-flop
End connects the input of described second not circuit；
The output end of described second not circuit connects described the second input with gate circuit；
Described and gate circuit output end is suitable to produce described status signal.
Optionally, described first delay cell is phase inverter.
Optionally, described Regulate signal is suitable to adjust the current value that in described phase inverter, tail current source provides.
Optionally, described Regulate signal is suitable to adjust the capacitance of load capacitance in described phase inverter.
Compared with prior art, technical scheme has advantages below：
The duty-ratio calibrating circuit that the present invention provides, when obtaining the first delay by input clock is carried out with half period delay
Clock, and the triggering of the triggering edge using described first delayed clock and described input clock is along the output shape changing triggers circuit
State.The half period being described input clock due to the time of the delayed described input clock of described first delayed clock, thus institute
State the first delayed clock triggering edge and described input clock triggering be described input clock along interval time half period,
That is, the output state of described triggers circuit just changes once every the half period of described input clock, therefore, described
The dutycycle of the output clock that triggers circuit produces is 50 percent.The duty-ratio calibrating circuit that the present invention provides is at most in institute
State in two cycles of input clock and produce described output clock, shorten the stabilization time of duty-ratio calibrating circuit.
In the alternative of the present invention, described duty-ratio calibrating circuit employs d type flip flop and not circuit is realized, due to
Digital circuit is easy to change from a technique to another technique, thus described duty-ratio calibrating circuit can simply be transplanted.
Brief description
Fig. 1 is the structural representation of the duty-ratio calibrating circuit of embodiment of the present invention；
Fig. 2 is a kind of structural representation of duty-ratio calibrating circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2；
Fig. 4 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2；
Fig. 5 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2；
Fig. 6 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2；
Fig. 7 is the structural representation of another kind duty-ratio calibrating circuit provided in an embodiment of the present invention；
Fig. 8 is a kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7；
Fig. 9 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7；
Figure 10 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7；
Figure 11 is another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7；
Figure 12 is a kind of structural representation of half period delay circuit provided in an embodiment of the present invention；
Figure 13 is a kind of structural representation of status signal generation unit provided in an embodiment of the present invention；
Figure 14 is a kind of working timing figure of the status signal generation unit of the embodiment of the present invention；
Figure 15 is another kind of working timing figure of the status signal generation unit of the embodiment of the present invention.
Specific embodiment
Fig. 1 is the structural representation of the duty-ratio calibrating circuit of embodiment of the present invention, described duty-ratio calibrating circuit bag
Include half period delay circuit 11, control signal produces circuit 12 and triggers circuit 13.
Specifically, described half period delay circuit 11 is suitable to input clock CKI be carried out with half period delay process to produce
First delayed clock CKD1.As clock to be calibrated, its dutycycle is random to described input clock CKI, is likely less than hundred
/ five ten it is also possible to be more than 50 percent.Process through described half period delay, described first delayed clock CKD1 is delayed
Equal with the dutycycle of described input clock CKI in described input clock CKI, dutycycle, lag time is described input clock
The half period of CKI, that is, on first rising edge of described first delayed clock CKD1 and first of described input clock CKI
Rise the half period being described input clock CKI along interval time.
Described control signal produces circuit 12 and is suitable to produce control signal CKC, described control according to described input clock CKI
Signal CKC is the first level in the triggering of described input clock CKI along the moment, otherwise for second electrical level.Described first level and
Described second electrical level is relative level, and described first level can be high level, and correspondingly described second electrical level is low level；
Described first level can also be low level, and correspondingly described second electrical level is high level.The triggering edge of described input clock CKI
Can be the rising edge of described input clock CKI or the trailing edge of described input clock CKI, in the embodiment of the present invention
Middle will illustrate.
When described triggers circuit 13 is suitable to produce output according to described first delayed clock CKD1 and described control signal CKC
The state of clock CKO, described output clock CKO is updated to described second when the triggering of described first delayed clock CKD1 is along arrival
Level, the state of described output clock CKO is updated to described first electricity when described control signal CKC is described first level
Flat.The triggering of described first delayed clock CKD1 is identical along type with the triggering of described input clock CKI along type, that is, described defeated
Along the rising edge for described input clock CKI, then the triggering edge of described first delayed clock CKD1 is institute for the triggering entering clock CKI
State the rising edge of the first delayed clock CKD1；The trailing edge for described input clock CKI for the triggering edge of described input clock CKI,
Then the triggering of described first delayed clock CKD1 is along the trailing edge for described first delayed clock CKD1.
The duty-ratio calibrating circuit that technical solution of the present invention provides, because described first delayed clock CKD1 is delayed described defeated
The time entering clock CKI is the half period of described input clock CKI, thus the triggering edge of described first delayed clock CKD1 and
The half period that the triggering of described input clock CKI is described input clock CKI along interval time, thus described output clock
The state of CKO just changes once every the half period of described input clock CKI, therefore, the dutycycle of described output clock CKO
For 50 percent.The duty-ratio calibrating circuit that the present invention provides produces at most within two cycles of described input clock CKI
Described output clock CKO, shortens the stabilization time of duty-ratio calibrating circuit.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With described first level as low level, described second electrical level as high level as a example, Fig. 2 be the embodiment of the present invention provide
A kind of duty-ratio calibrating circuit structural representation, described duty-ratio calibrating circuit include half period delay circuit 21, control
Signal generating circuit 22 and triggers circuit 23.
In the present embodiment, described control signal generation circuit 22 includes the first d type flip flop 221 and the first not circuit
222.The clock end Cl of described first d type flip flop 221 is suitable to receive described input clock CKI；Described first d type flip flop 221
Data terminal D is suitable to receive the first data-signal, and described first data-signal is described second electrical level, i.e. described first data-signal
For high level, generally in digital circuit, high level is power supply voltage signal, low level is ground voltage signal, therefore, described the
The data terminal D of one d type flip flop 221 is suitable to receive supply voltage Vdd；Control end C of described first d type flip flop 221 is suitable to receive
Described output clock CKO；Output end Q of described first d type flip flop 221 connects the input of described first not circuit 222；Institute
The output end stating the first not circuit 222 is suitable to produce described control signal CKC.
The triggering type of described first d type flip flop 221 determines according to the triggering edge of described input clock CKI：Described input
Along the rising edge for described input clock CKI, then described first d type flip flop 221 is rising edge d type flip flop for the triggering of clock CKI；
Along the lower liter edge for described input clock CKI, then described first d type flip flop 221 is lower liter edge for the triggering of described input clock CKI
D type flip flop.
Those skilled in the art know, d type flip flop includes the d type flip flop with control end and the d type flip flop without control end.
Output state without the d type flip flop of control end is only updated to data-signal when triggering is along arrival, and the triggering of the D with control end
The output state of device is not only updated to data-signal when triggering is along arrival, and the level also receiving in its control end is significant level
When be updated to described significant level.In the present embodiment, described first d type flip flop 221 is the d type flip flop with control end, and institute
The significant level stating the control end C reception of the first d type flip flop 221 is low level, and described first data-signal is high level, because
This, the output state of described first d type flip flop 221 is updated to high level when the triggering of described input clock CKI is along arrival, institute
The output state stating the first d type flip flop 221 is updated to low level when described output clock CKO is for low level.
The signal that described first not circuit 222 exports to described first d type flip flop 221 carries out non-process, produces described
Control signal CKC, described control signal CKC is contrary with the state of the signal that described first d type flip flop 221 exports, and that is, described
The signal of one d type flip flop 221 output is high level, then described control signal CKC is low level；Described first d type flip flop 221 is defeated
The signal going out is low level, then described control signal CKC is high level.
Described triggers circuit 23 includes the second d type flip flop 231.The clock end Cl of described second d type flip flop 231 is suitable to receive
Described first delayed clock CKD1；The data terminal D of described second d type flip flop 231 is suitable to receive the second data-signal, and described second
Data-signal is described second electrical level, and that is, described second data-signal is high level, the data terminal D of described second d type flip flop 231
It is suitable to receive described supply voltage Vdd；Control end C of described second d type flip flop 231 is suitable to receive described control signal CKC, that is,
Control end C of described second d type flip flop 231 connects the output end of described first not circuit 222；Described second d type flip flop 231
Output end Q be suitable to produce described output clock CKO.
The triggering type of described second d type flip flop 231 determines according to the triggering edge of described first delayed clock CKD1：Described
First delayed clock CKD1 triggers the rising edge for described first delayed clock CKD1 for the edge, then described second d type flip flop 231 is
Rising edge d type flip flop；The triggering of described first delayed clock CKD1 is along the lower liter edge for described first delayed clock CKD1, then institute
Stating the second d type flip flop 231 is lower liter along d type flip flop.In the present embodiment, by triggering edge and the institute of described input clock CKI
The triggering stating the first delayed clock CKD1 is identical along type, therefore, described second d type flip flop 231 and described first d type flip flop
221 triggering type is the same.
The operation principle of described second d type flip flop 231 is similar with the operation principle of described first d type flip flop 221：Described
2-D trigger 231 is the d type flip flop with control end, and the significant level that control end C of described second d type flip flop 231 receives is
Low level, described second data-signal is high level, and therefore, described output clock CKO is described first delayed clock CKD1's
Triggering is updated to high level along when arriving, and described output clock CKO is updated to low electricity when described control signal CKC is for low level
Flat.
As it was previously stated, the dutycycle of described input clock CKI is likely less than 50 percent it is also possible to be more than 5 percent
Ten；Described first d type flip flop 221 and described second d type flip flop 231 can be rising edge d type flip flop or trailing edge D
Trigger.Therefore, the duty-ratio calibrating circuit shown in Fig. 2 has multiple work schedules.Dutycycle with described input clock CKI
As a example being rising edge d type flip flop less than 50 percent, described first d type flip flop 221 and described second d type flip flop 231, Fig. 3
It is the working timing figure of described duty-ratio calibrating circuit.
Referring to figs. 2 and 3 through the half period delay process of described half period delay circuit 21, during described first delay
The time of the delayed described input clock CKI of clock CKD1 is the half period of described input clock CKI；In described first delayed clock
The rising edge time of CKD1, described output clock CKO is updated to high level；In the rising edge time of described input clock CKI, institute
The output state stating the first d type flip flop 221 is updated to high level；Through the non-process of described first not circuit 222, described control
Signal CKC processed is low level, controls described output clock CKO to be updated to low level；Described output clock CKO input described first
Control end C of d type flip flop 221, makes described control signal CKC be updated to high level, under so that described second d type flip flop 231 is waited
Secondary triggering.
Fig. 4～Fig. 6 is another three kinds of working timing figures of the duty-ratio calibrating circuit shown in Fig. 2, and wherein, Fig. 4 is described defeated
The dutycycle entering clock CKI is to rise more than 50 percent, described first d type flip flop 221 and described second d type flip flop 231
The work schedule of the duty-ratio calibrating circuit shown in along Fig. 2 during d type flip flop；Fig. 4 is that the dutycycle of described input clock CKI is less than
50 percent, described first d type flip flop 221 and described second d type flip flop 231 are accounting for shown in Fig. 2 during trailing edge d type flip flop
The empty work schedule than calibration circuit；Fig. 4 is that the dutycycle of described input clock CKI is touched more than a 50 percent, described D
When to send out device 221 and described second d type flip flop 231 be the work of the duty-ratio calibrating circuit shown in Fig. 2 during trailing edge d type flip flop
Sequence.The work schedule of Fig. 4～Fig. 6 is similar with Fig. 3, will not be described here.
With described first level as high level, described second electrical level as low level as a example, Fig. 7 be the embodiment of the present invention provide
Another kind of duty-ratio calibrating circuit structural representation, described duty-ratio calibrating circuit include half period delay circuit 71, control
Signal generating circuit 72 processed and triggers circuit 73.Described control signal produces circuit 72 and includes the first d type flip flop 721 and first
Not circuit 722, described triggers circuit 73 includes the second d type flip flop 731.Described first d type flip flop 721, described first not gate
The structure of circuit 722 and described second d type flip flop 731 and function module corresponding with Fig. 2 are similar to, and difference is：Described
The data terminal D of the data terminal D of the first d type flip flop 721 and described second d type flip flop 731 receives low-level data, and that is, described first
The data terminal D ground connection of the data terminal D of d type flip flop 721 and described second d type flip flop 731；The control of described first d type flip flop 721
The significant level that control end C of end C and described second d type flip flop 731 receives is high level.
Similar with the duty-ratio calibrating circuit shown in Fig. 2, when the duty-ratio calibrating circuit shown in Fig. 7 also has multiple work
Sequence.50 percent, described first d type flip flop 721 and described 2nd D triggering are less than with the dutycycle of described input clock CKI
As a example device 731 is rising edge d type flip flop, Fig. 8 is the working timing figure of described duty-ratio calibrating circuit.
With reference to Fig. 7 and Fig. 8, process through the half period delay of described half period delay circuit 21, during described first delay
The time of the delayed described input clock CKI of clock CKD1 is the half period of described input clock CKI；In described first delayed clock
The rising edge time of CKD1, described output clock CKO is updated to low level；In the rising edge time of described input clock CKI, institute
The output state stating the first d type flip flop 721 is updated to low level；Through the non-process of described first not circuit 722, described control
Signal CKC processed is high level, controls described output clock CKO to be updated to high level；Described output clock CKO input described first
Control end C of d type flip flop 721, makes described control signal CKC be updated to low level, under so that described second d type flip flop 731 is waited
Secondary triggering.
Fig. 9～Figure 11 is another three kinds of working timing figures of the duty-ratio calibrating circuit shown in Fig. 7, and wherein, Fig. 9 is described defeated
The dutycycle entering clock CKI is to rise more than 50 percent, described first d type flip flop 721 and described second d type flip flop 731
The work schedule of the duty-ratio calibrating circuit shown in along Fig. 7 during d type flip flop；Figure 10 is that the dutycycle of described input clock CKI is little
When 50 percent, described first d type flip flop 721 and described second d type flip flop 731 are trailing edge d type flip flop shown in Fig. 7
The work schedule of duty-ratio calibrating circuit；Figure 11 is that the dutycycle of described input clock CKI is more than 50 percent, described first
D type flip flop 721 and described second d type flip flop 731 are the work of the duty-ratio calibrating circuit shown in Fig. 7 during trailing edge d type flip flop
Sequential.The work schedule of Fig. 9～Figure 11 is similar with Fig. 8, will not be described here.
The duty-ratio calibrating circuit of the embodiment of the present invention employs d type flip flop and not circuit is realized, due to digital circuit
It is easy to change from a technique to another technique, thus described duty-ratio calibrating circuit can simply be transplanted.
Figure 12 is the structural representation of the half period delay circuit of the embodiment of the present invention, and described half period delay circuit includes
Status signal generation unit 121, status unit 122 and (2 × N) individual first delay cell：First delay cell
D11 ..., the first delay cell D1N, the first delay cell D1 (N+1) ..., the first delay cell D1 (2 × N), N >=1 and N is
Positive integer.
Specifically, described first delay cell includes input, output end and control end, described first delay cell
Control end is suitable to receive Regulate signal Ctr, and described Regulate signal Ctr is suitable to adjust the time delay of described first delay cell.
The initial delay time of described first delay cell determines according to Td ＜ T0 ÷ (2 × N), and wherein, Td is that described first delay is single
The initial delay time of unit, T0 is the cycle of described input clock CKI.Described (2 × N) individual first delay cell is in be connected in series
Structure, i.e. the input of output end connection (n+1) individual first delay cell of n-th first delay cells, 1≤n≤(2 ×
N)；The input of first the first delay cell D11 is suitable to receive described input clock CKI, n-th first delay cell D1N
Output end be suitable to produce described first delayed clock CKD1, the output end of (2 × N) individual first delay cell D1 (2 × N) is fitted
In producing the second delayed clock CKD2.
Described status signal generation unit 121 is suitable to according to described input clock CKI and described second delayed clock CKD2
Produce status signal Flag.If the time of the delayed described input clock CKI of described second delayed clock CKD2 is equal to described input
The a cycle of clock CKI, that is, the rising edge of the rising edge of described input clock CKI and described second delayed clock CKD2 is same
Moment arrives, and described status signal Flag is high level；If the delayed described input clock CKI's of described second delayed clock CKD2
Time is less than a cycle of described input clock CKI, and described status signal Flag is low level.
Described status unit 122 is suitable to produce described Regulate signal Ctr according to described status signal Flag.Described
When status signal Flag is low level, that is, the time of the delayed described input clock CKI of described second delayed clock CKD2 be less than institute
State input clock CKI a cycle when, described Regulate signal Ctr controls the time delay of described first delay cell to increase；
When described status signal Flag is high level, i.e. the time of the delayed described input clock CKI of described second delayed clock CKD2
During a cycle equal to described input clock CKI, described Regulate signal Ctr controls the time delay of described first delay cell
Keep constant, thus the time of the delayed described input clock CKI of described first delayed clock CKD1 be the half of described input clock
The individual cycle.
In the present embodiment, described first delay cell can be phase inverter.Carried by adjusting tail current source in phase inverter
For current value, or adjust phase inverter in load capacitance capacitance, all can adjust described first delay cell delay when
Between.Therefore, described status unit 122 can be for controlling electricity according to Regulate signal Ctr that described status signal Flag produces
Pressure or control electric current, data signal is converted to analog signal control.Those skilled in the art know how to believe described state
Number Flag is converted to described Regulate signal Ctr, that is, know the particular circuit configurations of described status unit 122, here is no longer
Repeat.
It should be noted that the half period delay circuit in technical solution of the present invention can be using the circuit knot shown in Figure 12
Structure, it would however also be possible to employ half period delay circuit of the prior art, the present invention is not construed as limiting to this.
Figure 13 is the structural representation of the status signal generation unit 121 of the embodiment of the present invention, and described status signal produces
Unit 121 include the second delay cell 131,3d flip-flop 132, four d flip-flop 133, the second not circuit 134 and
With gate circuit 135, described 3d flip-flop 132 and described four d flip-flop 133 are trailing edge d type flip flop.
When described second delay cell 131 is suitable to described input clock CKI be carried out with delay disposal to produce the 3rd delay
The time of the delayed described input clock CKI of clock CKD3, described 3rd delayed clock CKD3 can be configured according to the actual requirements, only
Will be enough to differentiate the clock edge of described 3rd delayed clock CKD3.Similar with described first delay cell, described second
Delay cell 131 can also be phase inverter.The clock end Cl of described 3d flip-flop 132 is suitable to receive described input clock
CKI；The data terminal D of described 3d flip-flop 132 connects the data terminal D of described four d flip-flop 133 and is suitable to described in reception
Second delayed clock CKD2；Output end Q of described 3d flip-flop 132 connects the described first input end with gate circuit 135.
The clock end Cl of described four d flip-flop 133 is suitable to receive described 3rd delayed clock CKD3；Described four d flip-flop 133
Output end Q connects the input of described second not gate 134 circuit.The output end of described second not circuit 134 connect described with
Second input of gate circuit 135；Described and gate circuit 135 output end is suitable to produce described status signal Flag.
So that the dutycycle of described input clock CKI is less than 50 percent as a example, Figure 14 is that described status signal produces list
The working timing figure of unit.In the trailing edge moment of described input clock CKI, if the trailing edge of described second delayed clock CKD2 is not
Arrive, that is, the time of the delayed described input clock CKI of described second delayed clock CKD2 be less than of described input clock CKI
Cycle, then described 3d flip-flop 132 and described four d flip-flop 133 output level there may be three kinds of combinations：Described
3d flip-flop 132 exports high level, and described four d flip-flop 133 exports high level, i.e. data signal 11；Described 3rd D
Trigger 132 exports low level, and described four d flip-flop 133 exports high level, i.e. digital signaling zero 1；Described 3d flip-flop
132 output low levels, described four d flip-flop 133 exports low level, i.e. digital signaling zero 0.Above-mentioned three kinds of situations, described and door
Circuit 135 all exports low level, and that is, described status signal Flag is low level.In the trailing edge moment of described input clock CKI,
If the trailing edge of described second delayed clock CKD2 arrives, i.e. the delayed described input clock CKI of described second delayed clock CKD2
Time be equal to a cycle of described input clock CKI, then described 3d flip-flop 132 output high level, described 4th D
Trigger 133 exports low level, i.e. data signal 10.Now, described and gate circuit 135 exports high level, i.e. described state letter
Number Flag is high level.
So that the dutycycle of described input clock CKI is more than 50 percent as a example, Figure 15 is that described status signal produces list
The working timing figure of unit.The working timing figure of Figure 15 is similar with the working timing figure of Figure 14, refers to the description to Figure 14, here
Repeat no more.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope limiting is defined.
Claims (9)
1. a kind of duty-ratio calibrating circuit is it is characterised in that include：Half period delay circuit, control signal produce circuit and
Triggers circuit；
Described half period delay circuit is suitable to input clock be carried out with half period delay process to produce the first delayed clock；
Described control signal produces circuit and is suitable to produce control signal according to described input clock, and described control signal is described defeated
The triggering entering clock is the first level along the moment, otherwise for second electrical level；
Described triggers circuit is suitable to produce output clock according to described first delayed clock and described control signal, during described output
The state of clock is updated to described second electrical level when the triggering of described first delayed clock is along arrival, is institute in described control signal
State and during the first level, be updated to described first level；
Described control signal produces circuit and includes the first d type flip flop and the first not circuit；
The clock end of described first d type flip flop is suitable to receive described input clock, and the data terminal of described first d type flip flop is suitable to connect
Receive the first data-signal, the control end of described first d type flip flop is suitable to receive described output clock, described first d type flip flop
Output end connects the input of described first not circuit, and described first data-signal is described second electrical level；
The output end of described first not circuit is suitable to produce described control signal.
2. duty-ratio calibrating circuit as claimed in claim 1 is it is characterised in that described triggers circuit includes the second d type flip flop；
The clock end of described second d type flip flop is suitable to receive described first delayed clock, and the data terminal of described second d type flip flop is fitted
In receiving the second data-signal, the control end of described second d type flip flop is suitable to receive described control signal, described 2nd D triggering
The output end of device is suitable to produce described output clock, and described second data-signal is described second electrical level.
3. duty-ratio calibrating circuit as claimed in claim 1 is it is characterised in that described first level is low level, described the
Two level are high level.
4. duty-ratio calibrating circuit as claimed in claim 1 is it is characterised in that described first level is high level, described the
Two level are low level.
5. the duty-ratio calibrating circuit as described in any one of Claims 1-4 is it is characterised in that described half period delay circuit
Including：Status signal generation unit, status unit and (2 × N) individual first delay cell, N >=1 and N are positive integer；
The control end of described first delay cell is suitable to receive Regulate signal, and described Regulate signal is suitable to adjust described first delay
The time delay of unit, the initial delay time of described first delay cell determines, wherein, Td is according to Td ＜ T0 ÷ (2 × N)
The initial delay time of described first delay cell, T0 is the cycle of described input clock；
Described (2 × N) individual first delay cell is in be connected in series structure, and the input of first the first delay cell is suitable to receive
Described input clock, the output end of n-th first delay cell is suitable to produce described first delayed clock, (2 × N) individual first
The output end of delay cell is suitable to produce the second delayed clock；
Described status signal generation unit is suitable to produce status signal, institute according to described input clock and described second delayed clock
State status signal when the rising edge of described input clock and the rising edge synchronization of described second delayed clock arrive for height
Level, otherwise for low level；
Described status unit is suitable to produce described Regulate signal according to described status signal, and described Regulate signal is in described shape
The time delay controlling described first delay cell when state signal is for low level increases, and is high level time control in described status signal
The time delay making described first delay cell keeps constant.
6. duty-ratio calibrating circuit as claimed in claim 5 is it is characterised in that described status signal generation unit includes second
Delay cell, 3d flip-flop, four d flip-flop, the second not circuit and and gate circuit, described 3d flip-flop and institute
Stating four d flip-flop is trailing edge d type flip flop；
Described second delay cell is suitable to carry out delay disposal to produce the 3rd delayed clock to described input clock；
The clock end of described 3d flip-flop is suitable to receive described input clock, and the data terminal of described 3d flip-flop connects institute
State the data terminal of four d flip-flop and be suitable to receive described second delayed clock, the output end of described 3d flip-flop connects institute
State the first input end with gate circuit；
The clock end of described four d flip-flop is suitable to receive described 3rd delayed clock, and the output end of described four d flip-flop is even
Connect the input of described second not circuit；
The output end of described second not circuit connects described the second input with gate circuit；
Described and gate circuit output end is suitable to produce described status signal.
7. duty-ratio calibrating circuit as claimed in claim 5 is it is characterised in that described first delay cell is phase inverter.
8. duty-ratio calibrating circuit as claimed in claim 7 it is characterised in that described Regulate signal be suitable to adjust described anti-phase
The current value that in device, tail current source provides.
9. duty-ratio calibrating circuit as claimed in claim 7 it is characterised in that described Regulate signal be suitable to adjust described anti-phase
The capacitance of load capacitance in device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410353784.6A CN104124945B (en) | 2014-07-23 | 2014-07-23 | Duty ratio calibrating circuit |
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| CN201410353784.6A CN104124945B (en) | 2014-07-23 | 2014-07-23 | Duty ratio calibrating circuit |
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| CN104124945B true CN104124945B (en) | 2017-02-15 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301354B (en) * | 2015-05-29 | 2021-10-26 | 京微雅格（北京）科技有限公司 | Duty ratio correction device and method |
| CN110324037B (en) * | 2018-03-31 | 2021-08-20 | 华为技术有限公司 | Frequency multiplier, digital phase-locked loop circuit and frequency multiplication method |
| CN108832915B (en) * | 2018-09-13 | 2024-05-14 | 长江存储科技有限责任公司 | Duty cycle calibration circuit |
| EP3855621B1 (en) * | 2019-11-22 | 2022-08-31 | Shenzhen Goodix Technology Co., Ltd. | Duty cycle calibration circuit |
| CN110928824B (en) * | 2019-11-27 | 2021-06-15 | 西安紫光国芯半导体有限公司 | High frequency off-line driver |
| CN114417758B (en) * | 2022-01-28 | 2023-06-20 | 杭州士兰微电子股份有限公司 | Trigger unit for clock gating based on data comparison |
| CN115179695B (en) * | 2022-08-16 | 2024-02-20 | 南京英锐创电子科技有限公司 | Signal detection circuit and tire pressure monitoring system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003121505A (en) * | 2001-10-17 | 2003-04-23 | Sharp Corp | Testing circuit and testing method |
| CN101087132A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Adjustment method of clock fifty percent idle percent based on phone mixing |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
| US7705649B1 (en) * | 2008-04-03 | 2010-04-27 | National Semiconductor Corporation | Duty cycle correction circuit with small duty error and wide frequency range |
-
2014
- 2014-07-23 CN CN201410353784.6A patent/CN104124945B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003121505A (en) * | 2001-10-17 | 2003-04-23 | Sharp Corp | Testing circuit and testing method |
| CN101087132A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Adjustment method of clock fifty percent idle percent based on phone mixing |
| US7705649B1 (en) * | 2008-04-03 | 2010-04-27 | National Semiconductor Corporation | Duty cycle correction circuit with small duty error and wide frequency range |
| CN101478300A (en) * | 2009-01-06 | 2009-07-08 | 东南大学 | Digital clock duty ratio calibrating circuit |
Non-Patent Citations (1)
| Title |
|---|
| "时钟占空比校准电路设计";杜振场;《万方数据库》;20101125;正文第7页至第9页，图2-11 * |
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