CN115412064A - Delay modulation circuit, method, chip and server - Google Patents
Delay modulation circuit, method, chip and server Download PDFInfo
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- CN115412064A CN115412064A CN202110595214.8A CN202110595214A CN115412064A CN 115412064 A CN115412064 A CN 115412064A CN 202110595214 A CN202110595214 A CN 202110595214A CN 115412064 A CN115412064 A CN 115412064A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
Abstract
The invention discloses a delay modulation circuit, a method, a chip and a server, wherein the delay modulation circuit comprises: the delay circuit is used for outputting a first pulse signal subjected to delay processing; the time delay reference unit is used for outputting a corresponding second pulse signal according to the clock signal; the comparison signal generating unit is used for outputting corresponding comparison signals according to the first pulse signals and the second pulse signals; and the control module is used for generating a corresponding control signal according to the comparison signal so as to adjust the delay time of the delay circuit for delay processing according to the control signal. The comparison signal represents the deviation between the first pulse signal and the second pulse signal to generate a corresponding control signal, and the current delay time of the delay circuit is adjusted according to the control signal to reduce the difference between the current delay time and the preset delay time, so that the condition of duty ratio distortion of the first pulse signal generated by the delay circuit is avoided, and the accuracy of the first pulse signal is ensured.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a delay modulation circuit, a delay modulation method, a delay modulation chip and a server.
Background
Clock pulses have irreplaceable roles in signal processing of a chip, and the quality of the clock is one of important factors determining the performance and stability of the chip. With the increase of the complexity and clock frequency of the chip system, the role of Pulse Width Modulation (PWM) is also becoming more important. In one clock period, the proportion of the high level relative to one clock period is called duty ratio, and the product of the duty ratio and the pulse period is the delay time. However, in actual circuit design, due to various irrational factors, duty ratio is distorted and deviates from the proportion of the duty ratio of an ideal clock, and pulse width modulation is a circuit capable of recalibrating the distorted duty ratio to the duty ratio of the ideal clock.
Pulse width modulation is a very efficient technique for controlling analog circuits using the digital output of a microprocessor and is widely used in many fields ranging from measurement, communications to power control and conversion. How to fine-tune the pulse width is a significant challenge in the art.
Disclosure of Invention
The invention mainly aims to provide a delay modulation circuit, a delay modulation method, a chip and a server.
In a first aspect, an embodiment of the present invention provides a delay modulation circuit, including:
the delay circuit is connected with the clock source and the data source and used for outputting a first pulse signal subjected to delay processing according to a clock signal of the clock source and a data signal of the data source; the comparison circuit comprises a delay reference unit and a comparison signal generation unit; the time delay reference unit is connected with the clock source and used for outputting a corresponding second pulse signal according to the clock signal; the comparison signal generating unit is connected with the delay reference unit and the delay circuit and used for outputting a corresponding comparison signal according to the first pulse signal and the second pulse signal; and the control module is connected with the comparison signal generation unit and the delay circuit and used for generating a corresponding control signal according to the comparison signal so as to adjust the delay time of the delay circuit for delay processing according to the control signal.
In a second aspect, an embodiment of the present invention provides a delay modulation method, which is applied to the delay modulation circuit described in the foregoing embodiment, and the method includes:
acquiring a delay modulation starting instruction; acquiring a first pulse signal of a delay circuit and a second pulse signal of a delay reference unit according to a delay modulation starting instruction; generating a comparison signal according to the first pulse signal and the second pulse signal; and generating a corresponding control signal according to the comparison signal so as to adjust the delay time of the delay circuit according to the control signal.
In a third aspect, an embodiment of the present invention provides a chip, where the delay modulation circuit described in the foregoing embodiment is integrated with the chip.
In a fourth aspect, an embodiment of the present invention provides a server, including at least one chip described in the foregoing embodiment.
The first pulse signal of the delay circuit and the second pulse signal of the delay reference unit are obtained, so that the comparison signal generation unit obtains a corresponding comparison signal according to the first pulse signal and the second pulse signal, and the comparison signal is used for representing the deviation between the current delay time and the preset delay time of the delay circuit. The control module generates a corresponding control signal according to the comparison signal to adjust the current delay time of the delay circuit and reduce the deviation between the current delay time and the preset delay time, so that the condition of duty ratio distortion of the first pulse signal generated by the delay circuit is avoided, and the accuracy of the first pulse signal is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a delay modulation circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the delay circuit and the comparison signal generating unit shown in FIG. 1;
fig. 3 is a schematic structural diagram of a delay unit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a delay modulation circuit according to another embodiment of the present invention;
FIG. 5 is a waveform diagram of signals in FIG. 4 when the duty ratio of the first pulse signal is greater than 50%;
FIG. 6 is a waveform diagram of signals in FIG. 4 when the duty cycle of the first pulse signal is less than 50%;
fig. 7 is a schematic structural diagram of a delay modulation circuit according to another embodiment of the present invention;
FIG. 8 is a waveform diagram of signals in FIG. 7 when the duty cycle of the first pulse signal is greater than 50%;
FIG. 9 is a waveform diagram of signals in FIG. 7 when the duty cycle of the first pulse signal is less than 50%;
fig. 10 is a schematic structural diagram of a delay modulation circuit according to still another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
In the following, some embodiments of the present application will be described in detail with reference to the drawings, and features in the following examples and examples may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a delay modulation circuit 1 according to an embodiment of the present invention.
Specifically, the delay modulation circuit 1 includes: a delay circuit 10, a comparison circuit 20 and a control module 30. The delay circuit 10 is connected to the clock source and the Data source, and configured to generate a corresponding pulse signal according to a clock signal Clk-in of the clock source and a Data signal Data-in of the Data source, perform delay processing on the pulse signal, and output a corresponding first pulse signal. The comparison circuit 20 specifically includes a delay reference unit 201 and a comparison signal generation unit 202. The delay reference unit 201 is connected to the clock source to receive the clock signal Clk-in of the clock source and output a corresponding second pulse signal according to the clock signal Clk-in. The input end of the comparison signal generating unit 202 is connected with the output end of the delay reference unit 201 and the output end of the delay circuit 10 to receive the first pulse signal and the second pulse signal and output corresponding comparison signals through the first pulse signal and the second pulse signal.
The first pulse signal is a pulse signal obtained after the preset delay processing by the delay circuit 10, and the second pulse signal is a pulse signal representing the standard delay, so that the comparison signal is used for representing the relationship between the delay time of the preset delay processing and the standard delay.
The input end of the control module 30 is connected to the output end of the comparison signal generating unit 202, and the output end of the control module 30 is connected to the delay circuit 10. After receiving the comparison signal output by the comparison signal generation unit 202, the control module 30 determines the magnitude relationship between the delay time of the preset delay process and the standard delay according to the comparison signal, so as to output a corresponding control signal to the delay circuit 10, and further enable the delay circuit 10 to adjust the delay time of the preset delay process according to the control signal, so as to reduce the deviation between the delay time of the preset delay process and the standard delay.
In some embodiments, referring to fig. 2, the comparison signal generating unit 202 includes a first D flip-flop 2021, which includes a first clock input Clk-1, a first data input D-1, and a first signal output Q-1. The first clock input end Clk-1 is connected to one of the delay circuit 20 and the delay reference unit 201, the first data input end D-1 is connected to the other of the delay circuit 20 and the delay reference unit 201, the first signal output end Q-1 is connected to the control module 30, and the first D flip-flop processes the pulse signal input from the first data input end D-1 according to the pulse signal input from the first clock input end Clk-1 to generate a corresponding comparison signal.
In some embodiments, the delay circuit 10 includes a delay unit 11 and a second D flip-flop 1212. The second D flip-flop 12 uses the clock signal Clk-in as a control signal, and outputs a corresponding initial pulse signal according to the control signal, and the delay unit 11 is configured to perform delay processing on the initial pulse signal output by the second D flip-flop 12 to obtain a first pulse signal.
Specifically, as shown in fig. 2, the second D flip-flop 12 includes a signal second data input terminal D-2, a second clock input terminal Clk-2, a second signal output terminal Q-2, and a clear signal terminal CDN. The second data input end D is connected with a data source, the second clock input end Clk is connected with a clock source, the second signal output end Q is connected with the input end of the delay unit 11, and the clear signal end CDN is connected with the output end of the delay unit 11.
The second D flip-flop 12 reads data of the second data input end D and transmits the data to the second signal output end Q when the clock signal Clk-in received by the second clock input end Clk is at a high level, and shields the data of the second data input end D when the clock signal Clk-in received by the second clock input end Clk is at a low level, and only when a next high level arrives, outputs the current data to the second signal output end Q, so as to control the second D flip-flop 12 to sample data of a data source according to the clock signal Clk-in and output a corresponding initial pulse signal.
The delay unit 11 includes a predetermined number of inverters, and the inverters are connected in series to form a delay chain, so as to perform a delay process on an input initial pulse signal.
The phase inverter comprises a PMOS tube and an NMOS tube, the source electrode of the PMOS tube is connected with a power supply VDD, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and serves as an input end, the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube and serves as an output end, and the source electrode of the NMOS tube is connected with a grounding end.
Usually, the PMOS tube is used as a load tube, and the NMOS tube is used as an input tube. This configuration can greatly reduce power consumption because in both 0, 1 logic states, one of the two transistors is always off. The starting voltage VGS (th) P of the PMOS tube is less than 0, the starting voltage VGS (th) N of the NMOS tube is more than 0, and in order to ensure normal operation, VDD > I VGS (th) P I + VGS (th) N is required, wherein VDD is power supply voltage. If the input is low level (such as 0V), the PMOS tube is conducted, the NMOS tube is cut off, and the output voltage is close to VDD. If the input is high level (such as VDD), the NMOS tube is conducted, the PMOS tube is cut off, and the output voltage is close to 0V.
It can be understood that the larger the number of inverters connected in series in the delay unit 11, the longer the delay time when the initial pulse signal is delayed, and therefore, the number of inverters in the delay unit 11 may be set according to a specific use scenario, which is not limited herein.
In some embodiments, the number of inverters included in the delay reference cell 201 and the number of inverters included in the delay circuit 10 are one odd and one even. The output ends of the units corresponding to the odd inverters are connected with a first clock input end Clk-1 of the first D flip-flop, and the output ends of the units corresponding to the even inverters are connected with a first data input end D-1 of the first D flip-flop. So that the comparison signal generation unit 202 collects the input of the first data input terminal D-1 according to the input of the first clock input terminal Clk-1 and generates the comparison signal.
In some embodiments, the control module 30 generates a corresponding control signal according to the comparison signal, wherein the control signal is specifically a control word signal. The control word signal is used to control the duty cycle of the first pulse signal generated by the delay circuit 10, so that the duty cycle of the generated first pulse signal is the desired duty cycle, that is, the delay time corresponding to the generated first pulse signal is the desired delay time.
For example, referring to fig. 3, the delay unit 11 is sequentially connected with a plurality of inverters a from the input terminal IN to the output terminal OUT, the output terminal of each inverter a is grounded through a variable load capacitor C, and the control word DCTRL is used to adjust the capacitance value of each variable capacitor C. When an input signal passes through the inverters A between the input end IN and the output end OUT, time delay is generated, the time delay can be adjusted by adjusting the size of a load capacitor C at the output end of each inverter A, and the adjustment of the load capacitor C is adjusted by a control word DCTRL, so that the time delay is adjustable.
It can be understood that the delay adjustment may also be implemented by adjusting the current or voltage of the delay unit 11, and a specific implementation manner of the delay adjustment may be selected according to a specific use situation, which is not limited herein.
The control module 30 may be provided with a delay chip, and the control module directly writes a control word into the delay chip, and the adjustment resolution is a numerical control delay step (for example, the delay step is 10 ps) provided by the chip itself.
The following describes the operation of the delay modulation circuit 1 in detail with reference to the above description of the embodiment of the present invention.
After the delay modulation circuit 1 receives the delay modulation start instruction, the comparison signal generation unit 202 obtains the first pulse signal and the second pulse signal according to the delay modulation start instruction, so as to obtain the comparison signal according to the first pulse signal and the second pulse signal. The delay modulation starting instruction may be generated by active triggering of a user, or may be generated by periodically and automatically triggering the delay modulation circuit 1 to start delay modulation on the delay circuit 10.
In some embodiments, the delay reference unit 201 includes an odd number of inverters, the delay circuit 10 includes an even number of inverters, and the control word is increased to increase the delay of the delay circuit 10.
For example, referring to fig. 4, an output terminal of the delay circuit 10 is connected to the first data input terminal D-1 of the first D flip-flop 2021, and the delay reference unit 201 includes an inverter, an output terminal of which is connected to the first clock input terminal Clk-1 of the first D flip-flop 2021, and is configured to invert the phase of the input clock signal Clk-in by 180 °, and output a second pulse signal, so that the first D flip-flop 2021 samples the first pulse signal input by the first data input terminal D-1 according to the second pulse signal to obtain a comparison signal.
The delay time is a product of a pulse duty cycle and a pulse period, so that the current delay time T1 of the delay circuit 10 is obtained according to the first pulse signal, and the preset delay time TA corresponding to the clock signal Clk-in is obtained according to the second pulse signal.
For example, referring to fig. 5, fig. 5 is a waveform diagram of signals when the current delay time T1 of the delay circuit 10 is greater than the preset delay time TA, where the duty ratio of the clock signal Clk-in and the second pulse signal B is 50%, and the duty ratio of the first pulse signal a is greater than 50%. At this time, the first D flip-flop 2021 samples the first pulse signal a according to the rising edge of the second pulse signal B, that is, according to the falling edge of the clock signal Clk-in. Since the duty ratio of the first pulse signal a is greater than 50%, the comparison signal output by the first D flip-flop 2021 is a high level signal.
After the control module 30 receives the high level signal, the generated control signal is a signal for reducing the control word, and the delay unit 11 performs parameter adjustment according to the corresponding control word to reduce the current delay time T1 of the delay circuit 10, where the parameter adjustment of the delay unit 11 may be to adjust a voltage parameter, a capacitance parameter, a current parameter, and the like, which is not limited herein. When the comparison signal output by the first D flip-flop 2021 is a low level signal, that is, when the comparison signal jumps, it indicates that the current delay time T1 is equal to the preset delay time TA, and the delay adjustment of the delay circuit 10 is completed.
Referring to fig. 6, fig. 6 is a waveform diagram of signals when the current delay time T1 of the delay circuit 10 is less than the preset delay time TA, where the duty ratio of the clock signal Clk-in and the second pulse signal B is 50%, and the duty ratio of the first pulse signal a is less than 50%. At this time, the first D flip-flop 2021 samples the first pulse signal a according to the rising edge of the second pulse signal B, that is, according to the falling edge of the clock signal Clk-in. Since the duty ratio of the first pulse signal a is less than 50%, the comparison signal output by the first D flip-flop 2021 is a low level signal.
After the control module 30 receives the low level signal, the generated control signal is a signal for increasing the control word, and the delay unit 11 performs parameter adjustment according to the corresponding control word to increase the current delay time T1 of the delay circuit 10, where the parameter adjustment of the delay unit 11 may be to adjust a voltage parameter, a capacitance parameter, a current parameter, and the like, which is not limited herein. When the comparison signal output by the first D flip-flop 2021 is a high level signal, that is, when the comparison signal jumps, it indicates that the current delay time T1 is equal to the preset delay time TA, and the delay adjustment of the delay circuit 10 is completed.
After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved, so that the delay unit 11 performs delay processing on the subsequent pulse signal according to the current configuration.
Through the first pulse signal and the second pulse signal, a deviation between the current delay time T1 of the delay circuit 10 and the preset delay time TA is obtained, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, so as to reduce the deviation between the current delay time and the preset delay time, thereby avoiding a situation of duty ratio distortion of the first pulse signal generated by the delay circuit 10, and ensuring the accuracy of the first pulse signal.
In some embodiments, the delay reference unit 201 includes an even number of inverters, the delay circuit 10 includes an odd number of inverters, and the control word is increased to increase the delay of the delay circuit 10.
For example, referring to fig. 7, the delay reference unit 201 includes two inverters, the output end of which is connected to the first data input end D-1 of the first D flip-flop 2021 and outputs the second pulse signal. The output end of the delay circuit 10 is connected to the first clock input Clk-1 of the first D flip-flop 2021, and is configured to delay the initial pulse signal, invert the phase of the initial pulse signal by 180 °, and output the first pulse signal, so that the first D flip-flop 2021 samples the input second pulse signal according to the first pulse signal to obtain the comparison signal.
The delay time is a product of a pulse duty cycle and a pulse period, so that the current delay time T1 of the delay circuit 10 is obtained according to the first pulse signal, and the preset delay time TA corresponding to the clock signal Clk-in is obtained according to the second pulse signal.
It can be understood that an inverter is provided at the signal Output terminal Output of the delay circuit 10 to ensure that the logic of the pulse signal Output by the delay circuit 10 is correct.
For example, referring to fig. 8, fig. 8 is a waveform diagram of each signal when the current delay time T1 of the delay circuit 10 is greater than the preset delay time TA, wherein the duty ratio of the clock signal Clk-in and the second pulse signal B is 50%, and the duty ratio of the first pulse signal a is less than 50%. At this time, the first D flip-flop 2021 samples the second pulse signal B according to the rising edge of the first pulse signal a, and thus the comparison signal output by the first D flip-flop 2021 is a low level signal.
After the control module 30 receives the low level signal, the generated control signal is a signal for reducing the control word, and the delay unit 11 performs parameter adjustment according to the corresponding control word to reduce the current delay time T1 of the delay circuit 10, where the parameter adjustment of the delay unit 11 may be to adjust a voltage parameter, a capacitance parameter, a current parameter, and the like, which is not limited herein. When the comparison signal output by the first D flip-flop 2021 is a high level signal, that is, when the comparison signal jumps, it indicates that the current delay time T1 is equal to the preset delay time TA, and the delay adjustment of the delay circuit 10 is completed.
For example, referring to fig. 9, fig. 9 is a waveform diagram of signals when a current delay time T1 of the delay circuit 10 is less than a preset delay time TA, where a duty ratio of the clock signal Clk-in and the second pulse signal B is 50%, and a duty ratio of the first pulse signal a is greater than 50%. At this time, the first D flip-flop 2021 samples the second pulse signal B according to the rising edge of the first pulse signal a, and thus the comparison signal output by the first D flip-flop 2021 is a high level signal.
After the control module 30 receives the high level signal, the generated control signal is a signal for increasing the control word, and the delay unit 11 performs parameter adjustment according to the corresponding control word to increase the current delay time T1 of the delay circuit 10, where the parameter adjustment of the delay unit 11 may be to adjust a voltage parameter, a capacitance parameter, a current parameter, and the like, which is not limited herein. When the comparison signal output by the first D flip-flop 2021 is a low level signal, that is, when the comparison signal jumps, it indicates that the current delay time T1 is equal to the preset delay time TA, and the delay adjustment of the delay circuit 10 is completed.
After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved, so that the delay unit 11 performs delay processing on the subsequent pulse signal according to the current configuration.
Through the first pulse signal and the second pulse signal, a deviation between the current delay time T1 of the delay circuit 10 and the preset delay time TA is obtained, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, so as to reduce the deviation between the current delay time and the preset delay time, thereby avoiding a situation of duty ratio distortion of the first pulse signal generated by the delay circuit 10, and ensuring the accuracy of the first pulse signal.
In some embodiments, referring to fig. 10, the delay reference unit 201 includes a reference circuit 211, and the reference circuit 211 includes a predetermined number of inverters for outputting the second pulse signal processed by the predetermined delay. And obtaining a preset delay time TA corresponding to the preset delay processing according to the second pulse signal, and obtaining the current delay time T1 of the delay circuit 10 according to the first pulse signal. The comparison signal generating unit 202 obtains a corresponding comparison signal according to the second pulse signal and the first pulse signal, and the control module 30 generates a corresponding control signal according to the comparison signal, so that the delay circuit 10 adjusts the parameter configuration of the delay unit 11 according to the control signal to adjust the delay time T1, thereby reducing the deviation between the delay time T1 and the preset delay time TA.
After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved, so that the delay unit 11 performs delay processing on the subsequent pulse signal according to the current configuration.
The preset delay time TA of the reference circuit 211 is used as a target of delay adjustment, and a deviation between the current delay time T1 of the delay circuit 10 and the preset delay time TA is obtained through the first pulse signal and the second pulse signal, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, and further, the delay time of the delay circuit 10 can be aligned with the delay time of the reference circuit 211, that is, clock synchronization between the delay circuit 10 and the reference circuit 211 is realized.
The invention also provides a chip, which comprises the delay modulation circuit described in any one of the above embodiments of the invention.
Therefore, the corresponding specific implementation manner of the chip in the embodiment of the present invention is similar to the specific implementation manner of the delay modulation circuit in the embodiment of the present invention, and please refer to the description of the delay modulation circuit part specifically, which is not described herein again.
The invention also provides a server for data processing or operation, such as operation of digging virtual digital currency. The server comprises a connecting plate, a control board, a radiator, a power supply board and one or more force calculation boards, wherein each force calculation board comprises one or more chips. The control board is connected with the force calculation board through a connecting board, and the radiator is arranged around the force calculation board. The power panel is used for providing power for the connecting plate, the control panel, the radiator and the force calculation plate.
It should be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments. While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A delay modulation circuit, comprising:
the delay circuit is connected with a clock source and a data source and used for outputting a first pulse signal subjected to delay processing according to a clock signal of the clock source and a data signal of the data source;
the comparison circuit comprises a delay reference unit and a comparison signal generation unit; the delay reference unit is connected with the clock source and used for outputting a corresponding second pulse signal according to the clock signal; the comparison signal generating unit is connected with the delay reference unit and the delay circuit and is used for outputting corresponding comparison signals according to the first pulse signals and the second pulse signals; and
and the control module is connected with the comparison signal generation unit and the delay circuit and used for generating a corresponding control signal according to the comparison signal so as to adjust the delay time of the delay circuit for delay processing according to the control signal.
2. The delay modulation circuit according to claim 1, wherein the delay reference unit and the delay circuit each include a predetermined number of inverters, and one of the number of inverters in the delay reference unit and the number of inverters in the delay circuit is an odd number, and the other is an even number.
3. The delay modulation circuit according to claim 1, wherein the comparison signal generating unit comprises a first D flip-flop including a first clock input terminal, a first data input terminal, and a first signal output terminal;
the first clock input end is connected with one of the delay circuit and the delay reference unit;
the first data input terminal is connected with the other one of the delay circuit and the delay reference unit;
the first signal output end is connected with the control module;
and the first D trigger processes the pulse signal input by the first data input end according to the pulse signal input by the first clock input end.
4. The delay modulation circuit of claim 1, wherein the delay circuit comprises a second D flip-flop and a delay unit;
the second D trigger is connected with the clock source and the data source and used for generating a corresponding initial pulse signal according to a clock signal of the clock source and a data signal of the data source;
the delay unit is connected with the second D trigger and used for carrying out delay processing on the initial pulse signal so as to output a first pulse signal subjected to delay processing.
5. The delay modulation circuit of claim 4, wherein: the second D trigger comprises a second data input end, a second clock input end, a second signal output end and a zero clearing signal end, wherein the second data input end is connected with the data source, the second clock input end is connected with the clock source, the second signal output end is connected with the input end of the delay unit, and the zero clearing signal end is connected with the output end of the delay unit;
the delay unit comprises a plurality of phase inverters which are connected in series, each phase inverter comprises a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube, the source electrode of each PMOS tube is connected with a power supply, the grid electrode of each PMOS tube is connected with the grid electrode of each NMOS tube and serves as an input end, the drain electrode of each PMOS tube is connected with the drain electrode of each NMOS tube and serves as an output end, and the source electrode of each NMOS tube is connected with a grounding end.
6. A delay modulation method applied to the delay modulation circuit according to any one of claims 1 to 5, the method comprising:
acquiring a delay modulation starting instruction;
acquiring a first pulse signal of a delay circuit and a second pulse signal of a delay reference unit according to the delay modulation starting instruction;
generating a comparison signal according to the first pulse signal and the second pulse signal;
and generating a corresponding control signal according to the comparison signal so as to adjust the delay time of the delay circuit according to the control signal.
7. The delay modulation method according to claim 6, wherein the comparison signal includes a low level signal and a high level signal, the delay reference unit includes an odd number of inverters, the delay circuit includes an even number of inverters, and the generating the comparison signal from the first pulse signal and the second pulse signal includes:
acquiring the first pulse signal according to the rising edge of the second pulse signal so as to generate a corresponding comparison signal according to an acquisition result;
when the current delay time of the delay circuit is greater than the preset delay time, the output comparison signal is a high-level signal;
and when the current delay time of the delay circuit is less than the preset delay time, the output comparison signal is a low-level signal.
8. The delay modulation method of claim 7, wherein the control signal comprises a control word signal, and the generating a corresponding control signal according to the comparison signal to adjust the delay time of the delay circuit according to the control signal comprises:
generating a corresponding control word signal according to the comparison signal;
adjusting the delay time of the delay circuit according to the control word signal;
and when the comparison signal jumps, finishing delay adjustment.
9. A chip integrated with the delay modulation circuit of any one of claims 1-5.
10. A server, characterized in that it comprises at least one chip according to claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110595214.8A CN115412064A (en) | 2021-05-28 | 2021-05-28 | Delay modulation circuit, method, chip and server |
| PCT/CN2022/093111 WO2022247681A1 (en) | 2021-05-28 | 2022-05-16 | Delay modulation circuit and method, chip, and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110595214.8A CN115412064A (en) | 2021-05-28 | 2021-05-28 | Delay modulation circuit, method, chip and server |
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| CN115412064A true CN115412064A (en) | 2022-11-29 |
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| WO (1) | WO2022247681A1 (en) |
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| CN117119075B (en) * | 2023-10-25 | 2024-02-09 | 浙江地芯引力科技有限公司 | Protocol identification circuit, chip, protocol identification method and electronic equipment |
| CN117240394B (en) * | 2023-11-16 | 2024-01-19 | 北京无线电测量研究所 | Synchronous calibrating device between transceiver chip channels |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5317202A (en) * | 1992-05-28 | 1994-05-31 | Intel Corporation | Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle |
| JP3060970B2 (en) * | 1996-11-14 | 2000-07-10 | 日本電気株式会社 | Pulse width modulation circuit |
| US6100736A (en) * | 1997-06-05 | 2000-08-08 | Cirrus Logic, Inc | Frequency doubler using digital delay lock loop |
| KR101290192B1 (en) * | 2011-10-28 | 2013-07-30 | 고려대학교 산학협력단 | High-Speed Duty Cycle Correction Circuit |
| CN110957998B (en) * | 2019-12-02 | 2020-08-11 | 翱捷智能科技(上海)有限公司 | Circuit for accurately correcting duty ratio of clock signal |
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| WO2022247681A1 (en) | 2022-12-01 |
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