CN104124945A - Duty ratio calibrating circuit - Google Patents
Duty ratio calibrating circuit Download PDFInfo
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- CN104124945A CN104124945A CN201410353784.6A CN201410353784A CN104124945A CN 104124945 A CN104124945 A CN 104124945A CN 201410353784 A CN201410353784 A CN 201410353784A CN 104124945 A CN104124945 A CN 104124945A
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Abstract
A duty ratio calibrating circuit comprises a semi-cycle delay circuit, a control signal generating circuit and a triggering circuit. The semi-cycle delay circuit is applicable to semi-cycle delay processing of an input clock so as to generate a first delay clock. The control signal generating circuit is applicable to generating of a control signal according to the input clock, and the control signal is in a first level at a trigger edge moment of the input clock, or is in a second level. The triggering circuit is applicable to generating of an output clock according to the first delay clock and the control signal. The state of the output clock is changed into the second level when the trigger edge of the first delay clock arrives and is changed into the first level when the control signal is in the first level. The duty ratio calibrating circuit is short in stabilizing time.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of duty-ratio calibrating circuit.
Background technology
Along with the technological change replacement of integrated circuit and the continuous innovation of designing technique, the operating rate of chip is continued to be improved.Mean at a high speed harsher time sequence precision, the clock performance of system is required to also corresponding raising, one of them important performance index is duty ratios of clock.As a rule, duty ratio is that 50 percent clock is the most favourable for the propagation of data.
In actual applications, the clock of system often produces by phase-locked loop or delay locked loop.The deviation of technique and simulation model in the mismatch producing due to circuit design itself and chip manufacturing proces, through frequency multiplication, synchronous after the clock of generation often can not guarantee that duty ratio is 50 percent.In addition, in the communication process of clock, owing to existing equally the deviation of system and technique in distribution link, also the duty ratio imbalance of clock will be caused.Particularly, when frequency applications, the imbalance of duty ratio even can make clock normally not overturn, thereby causes serious sequential mistake.Therefore, duty ratio is being required in strict occasion, it is very necessary adding duty-ratio calibrating circuit (DDC, Duty Cycle Corrector).
Duty-ratio calibrating circuit is widely used in the circuit such as Double Data Rate synchronous DRAM, two sampling analog to digital converter, phase-locked loop and clock and data recovery, take and produce the clock that a duty ratio is 50 percent, thus the best of the normal operation of safeguards system and usefulness performance.In prior art, duty-ratio calibrating circuit adopts analog form to calibrate conventionally.Detection mode in analog duty-ratio calibrating circuit and adjustment mode are all continuous, thereby have advantages of that calibration accuracy is high, adjustable frequency wide ranges.Yet analog duty-ratio calibrating circuit adopts feedback arrangement more, stabilization time that need to be longer, needing the long period could output duty cycle be 50 percent clock.
Summary of the invention
What the present invention solved is analog duty-ratio calibrating circuit long problem stabilization time.
For addressing the above problem, the invention provides a kind of duty-ratio calibrating circuit, comprising: half period delay circuit, control signal produce circuit and circuits for triggering;
Described half period delay circuit is suitable for input clock to carry out half period delay processing to produce the first delayed clock;
Described control signal produces circuit and is suitable for producing control signal according to described input clock, and described control signal is the first level in the triggering of described input clock along the moment, otherwise is second electrical level;
Described circuits for triggering are suitable for producing output clock according to described the first delayed clock and described control signal, the state of described output clock is updated to described second electrical level in the triggering of described the first delayed clock when arriving, and is updated to described the first level when described control signal is described the first level.
Optionally, described control signal produces circuit and comprises the first d type flip flop and the first not circuit;
The clock end of described the first d type flip flop is suitable for receiving described input clock, the data terminal of described the first d type flip flop is suitable for receiving the first data-signal, the control end of described the first d type flip flop is suitable for receiving described output clock, the output of described the first d type flip flop connects the input of described the first not circuit, and described the first data-signal is described second electrical level;
The output of described the first not circuit is suitable for producing described control signal.
Optionally, described circuits for triggering comprise the second d type flip flop;
The clock end of described the second d type flip flop is suitable for receiving described the first delayed clock, the data terminal of described the second d type flip flop is suitable for receiving the second data-signal, the control end of described the second d type flip flop is suitable for receiving described control signal, the output of described the second d type flip flop is suitable for producing described output clock, and described the second data-signal is described second electrical level.
Optionally, described the first level is low level, and described second electrical level is high level.
Optionally, described the first level is high level, and described second electrical level is low level.
Optionally, described half period delay circuit comprises: status signal generation unit, status unit and (2 * N) individual first delay cell, and N >=1 and N are positive integer;
The control end of described the first delay cell is suitable for receiving conditioning signal, described conditioning signal is suitable for regulating the time of delay of described the first delay cell, the initial delay time of described the first delay cell is determined according to Td < T0 ÷ (2 * N), wherein, Td is the initial delay time of described the first delay cell, the cycle that T0 is described input clock;
Described (2 * N) individual first delay cell is connect in series structure, the input of first the first delay cell is suitable for receiving described input clock, the output of N the first delay cell is suitable for producing described the first delayed clock, and the output of (2 * N) individual first delay cell is suitable for producing the second delayed clock;
Described status signal generation unit is suitable for producing status signal according to described input clock and described the second delayed clock, described status signal is high level when the rising edge of described input clock and the arrival of the rising edge synchronization of described the second delayed clock, otherwise is low level;
Described status unit is suitable for producing described conditioning signal according to described status signal, increase the time of delay that described conditioning signal is controlled described the first delay cell when described status signal is low level, and remain unchanged the time of delay of controlling described the first delay cell when described status signal is high level.
Optionally, described status signal generation unit comprises the second delay cell, 3d flip-flop, four d flip-flop, the second not circuit and AND circuit, and described 3d flip-flop and described four d flip-flop are trailing edge d type flip flop;
Described the second delay cell is suitable for described input clock to carry out delay disposal to produce the 3rd delayed clock;
The clock end of described 3d flip-flop is suitable for receiving described input clock, the data terminal of described 3d flip-flop connects the data terminal of described four d flip-flop and is suitable for receiving described the second delayed clock, and the output of described 3d flip-flop connects the first input end of described AND circuit;
The clock end of described four d flip-flop is suitable for receiving described the 3rd delayed clock, and the output of described four d flip-flop connects the input of described the second not circuit;
The output of described the second not circuit connects the second input of described AND circuit;
The output of described AND circuit is suitable for producing described status signal.
Optionally, described the first delay cell is inverter.
Optionally, described conditioning signal is suitable for regulating the current value that in described inverter, tail current source provides.
Optionally, described conditioning signal is suitable for regulating the capacitance of load capacitance in described inverter.
Compared with prior art, technical scheme of the present invention has the following advantages:
Duty-ratio calibrating circuit provided by the invention, obtains the first delayed clock by input clock is carried out to half period delay, and adopts the triggering edge of described the first delayed clock and the triggering of described input clock along the output state that changes circuits for triggering.Due to described the first delayed clock half period that time of described input clock is described input clock that lags behind, thereby the triggering edge of described the first delayed clock and the triggering of the described input clock half period that is described input clock along interval time, that is to say, the output state of described circuits for triggering just changes once every the half period of described input clock, the duty ratio of the output clock that therefore, described circuits for triggering produce is 50 percent.Duty-ratio calibrating circuit provided by the invention produces described output clock at most within two cycles of described input clock, has shortened the stabilization time of duty-ratio calibrating circuit.
In possibility of the present invention, described duty-ratio calibrating circuit has adopted d type flip flop and not circuit to realize, and because digital circuit is easy to conversion from a technique to another technique, thereby described duty-ratio calibrating circuit can simply be transplanted.
Accompanying drawing explanation
Fig. 1 is the structural representation of the duty-ratio calibrating circuit of embodiment of the present invention;
Fig. 2 is the structural representation of a kind of duty-ratio calibrating circuit of providing of the embodiment of the present invention;
Fig. 3 is a kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2;
Fig. 4 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2;
Fig. 5 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2;
Fig. 6 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 2;
Fig. 7 is the structural representation of the another kind of duty-ratio calibrating circuit that provides of the embodiment of the present invention;
Fig. 8 is a kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7;
Fig. 9 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7;
Figure 10 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7;
Figure 11 is the another kind of working timing figure of the duty-ratio calibrating circuit shown in Fig. 7;
Figure 12 is the structural representation of a kind of half period delay circuit of providing of the embodiment of the present invention;
Figure 13 is the structural representation of a kind of status signal generation unit of providing of the embodiment of the present invention;
Figure 14 is a kind of working timing figure of the status signal generation unit of the embodiment of the present invention;
Figure 15 is the another kind of working timing figure of the status signal generation unit of the embodiment of the present invention.
Embodiment
Fig. 1 is the structural representation of the duty-ratio calibrating circuit of embodiment of the present invention, and described duty-ratio calibrating circuit comprises that half period delay circuit 11, control signal produce circuit 12 and circuits for triggering 13.
Particularly, described half period delay circuit 11 is suitable for input clock CKI to carry out half period delay processing to produce the first delayed clock CKD1.Described input clock CKI is as clock to be calibrated, and its duty ratio is random, may be less than 50 percent, also may be greater than 50 percent.Through described half period delay, process, described the first delayed clock CKD1 lags behind described input clock CKI, duty ratio equates with the duty ratio of described input clock CKI, be the half period of described input clock CKI lag time, and be the half period of described input clock CKI first rising edge interval time of first rising edge of described the first delayed clock CKD1 and described input clock CKI.
Described control signal produces circuit 12 and is suitable for producing control signal CKC according to described input clock CKI, and described control signal CKC is the first level in the triggering of described input clock CKI along the moment, otherwise is second electrical level.Described the first level is relative level with described second electrical level, and described the first level can be high level, and correspondingly described second electrical level is low level; Described the first level can be also low level, and correspondingly described second electrical level is high level.The triggering of described input clock CKI, along being the rising edge of described input clock CKI, can be also the trailing edge of described input clock CKI, will illustrate in embodiments of the present invention.
Described circuits for triggering 13 are suitable for producing output clock CKO according to described the first delayed clock CKD1 and described control signal CKC, the state of described output clock CKO is updated to described second electrical level in the triggering of described the first delayed clock CKD1 when arriving, and the state of described output clock CKO is updated to described the first level when described control signal CKC is described the first level.The triggering of described the first delayed clock CKD1 is identical along type with the triggering of described input clock CKI along type, the triggering edge that is described input clock CKI is the rising edge of described input clock CKI, and the triggering of described the first delayed clock CKD1 edge is the rising edge of described the first delayed clock CKD1; The triggering of described input clock CKI is along being the trailing edge of described input clock CKI, and the triggering of described the first delayed clock CKD1 edge is the trailing edge of described the first delayed clock CKD1.
The duty-ratio calibrating circuit that technical solution of the present invention provides, because lag behind time of described input clock CKI of described the first delayed clock CKD1 is the half period of described input clock CKI, thereby the triggering edge of described the first delayed clock CKD1 and the triggering of described input clock CKI are the half period of described input clock CKI along interval time, thereby the state of described output clock CKO just changes once every the half period of described input clock CKI, therefore, the duty ratio of described output clock CKO is 50 percent.Duty-ratio calibrating circuit provided by the invention produces described output clock CKO at most within two cycles of described input clock CKI, has shortened the stabilization time of duty-ratio calibrating circuit.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Described the first level of take is example as low level, described second electrical level as high level, Fig. 2 is the structural representation of a kind of duty-ratio calibrating circuit of providing of the embodiment of the present invention, and described duty-ratio calibrating circuit comprises that half period delay circuit 21, control signal produce circuit 22 and circuits for triggering 23.
In the present embodiment, described control signal generation circuit 22 comprises the first d type flip flop 221 and the first not circuit 222.The clock end Cl of described the first d type flip flop 221 is suitable for receiving described input clock CKI; The data terminal D of described the first d type flip flop 221 is suitable for receiving the first data-signal, described the first data-signal is described second electrical level, be that described the first data-signal is high level, conventionally in digital circuit, high level is that power supply voltage signal, low level are ground voltage signal, therefore, the data terminal D of described the first d type flip flop 221 is suitable for receiving supply voltage Vdd; The control end C of described the first d type flip flop 221 is suitable for receiving described output clock CKO; The output Q of described the first d type flip flop 221 connects the input of described the first not circuit 222; The output of described the first not circuit 222 is suitable for producing described control signal CKC.
The triggering type of described the first d type flip flop 221 is determined according to the triggering edge of described input clock CKI: the triggering of described input clock CKI is along being the rising edge of described input clock CKI, and described the first d type flip flop 221 is rising edge d type flip flop; The triggering of described input clock CKI is along being the lower edge that rises of described input clock CKI, described the first d type flip flop 221 be lower liter along d type flip flop.
Those skilled in the art know, and d type flip flop comprises with the d type flip flop of control end with not with the d type flip flop of control end.With the output state of the d type flip flop of control end, be not only updated to data-signal when arriving triggering, and being not only updated to data-signal when arriving triggering with the output state of the d type flip flop of control end, the level also receiving at its control end is updated to described significant level while being significant level.In the present embodiment, described the first d type flip flop 221 is the d type flip flop with control end, and the significant level that the control end C of described the first d type flip flop 221 receives is low level, described the first data-signal is high level, therefore, the output state of described the first d type flip flop 221 is updated to high level in the triggering of described input clock CKI when arriving, and the output state of described the first d type flip flop 221 is updated to low level when described output clock CKO is low level.
The signal of 222 pairs of described the first d type flip flop 221 outputs of described the first not circuit carries out non-processing, produce described control signal CKC, the opposite states of the signal of described control signal CKC and described the first d type flip flop 221 outputs, the signal that is described the first d type flip flop 221 outputs is high level, and described control signal CKC is low level; The signal of described the first d type flip flop 221 outputs is low level, and described control signal CKC is high level.
Described circuits for triggering 23 comprise the second d type flip flop 231.The clock end Cl of described the second d type flip flop 231 is suitable for receiving described the first delayed clock CKD1; The data terminal D of described the second d type flip flop 231 is suitable for receiving the second data-signal, and described the second data-signal is described second electrical level, and described the second data-signal is high level, and the data terminal D of described the second d type flip flop 231 is suitable for receiving described supply voltage Vdd; The control end C of described the second d type flip flop 231 is suitable for receiving described control signal CKC, and the control end C of described the second d type flip flop 231 connects the output of described the first not circuit 222; The output Q of described the second d type flip flop 231 is suitable for producing described output clock CKO.
The triggering type of described the second d type flip flop 231 is determined according to the triggering edge of described the first delayed clock CKD1: the triggering of described the first delayed clock CKD1 is along being the rising edge of described the first delayed clock CKD1, and described the second d type flip flop 231 is rising edge d type flip flop; The triggering of described the first delayed clock CKD1 is along being the lower edge that rises of described the first delayed clock CKD1, described the second d type flip flop 231 be lower liter along d type flip flop.In the present embodiment, because the triggering edge of described input clock CKI is identical along type with the triggering of described the first delayed clock CKD1, therefore, described the second d type flip flop 231 is the same with the triggering type of described the first d type flip flop 221.
The operation principle of the operation principle of described the second d type flip flop 231 and described the first d type flip flop 221 is similar: described the second d type flip flop 231 is the d type flip flop with control end, and the significant level that the control end C of described the second d type flip flop 231 receives is low level, described the second data-signal is high level, therefore, described output clock CKO is updated to high level in the triggering of described the first delayed clock CKD1 when arriving, and described output clock CKO is updated to low level when described control signal CKC is low level.
As previously mentioned, the duty ratio of described input clock CKI may be less than 50 percent, also may be greater than 50 percent; Described the first d type flip flop 221 and described the second d type flip flop 231 can be rising edge d type flip flops, can be also trailing edge d type flip flops.Therefore, the duty-ratio calibrating circuit shown in Fig. 2 has multiple work schedule.The duty ratio of described input clock CKI of take is less than 50 percent, described the first d type flip flop 221 and described the second d type flip flop 231 are that rising edge d type flip flop is example, and Fig. 3 is the working timing figure of described duty-ratio calibrating circuit.
Referring to figs. 2 and 3, through the half period delay of described half period delay circuit 21, to process, lag behind time of described input clock CKI of described the first delayed clock CKD1 is the half period of described input clock CKI; In the rising edge moment of described the first delayed clock CKD1, described output clock CKO is updated to high level; In the rising edge moment of described input clock CKI, the output state of described the first d type flip flop 221 is updated to high level; Through the non-processing of described the first not circuit 222, described control signal CKC is low level, controls described output clock CKO and is updated to low level; Described output clock CKO inputs the control end C of described the first d type flip flop 221, makes described control signal CKC be updated to high level, makes described the second d type flip flop 231 wait for next time and triggers.
Fig. 4～Fig. 6 is another three kinds of working timing figures of the duty-ratio calibrating circuit shown in Fig. 2, wherein, Fig. 4 be that the duty ratio of described input clock CKI is greater than 50 percent, the work schedule of described the first d type flip flop 221 and described the second d type flip flop 231 duty-ratio calibrating circuit shown in Fig. 2 while being rising edge d type flip flop; Fig. 4 is that the duty ratio of described input clock CKI is less than 50 percent, the work schedule of described the first d type flip flop 221 and described the second d type flip flop 231 duty-ratio calibrating circuit shown in Fig. 2 while being trailing edge d type flip flop; Fig. 4 is that the duty ratio of described input clock CKI is greater than 50 percent, the work schedule of described the first d type flip flop 221 and described the second d type flip flop 231 duty-ratio calibrating circuit shown in Fig. 2 while being trailing edge d type flip flop.Work schedule and Fig. 3 of Fig. 4～Fig. 6 are similar, do not repeat them here.
Described the first level of take is example as high level, described second electrical level as low level, Fig. 7 is the structural representation of the another kind of duty-ratio calibrating circuit that provides of the embodiment of the present invention, and described duty-ratio calibrating circuit comprises that half period delay circuit 71, control signal produce circuit 72 and circuits for triggering 73.Described control signal produces circuit 72 and comprises the first d type flip flop 721 and the first not circuit 722, and described circuits for triggering 73 comprise the second d type flip flop 731.The structure of described the first d type flip flop 721, described the first not circuit 722 and described the second d type flip flop 731 and function and module class corresponding in Fig. 2 are seemingly, difference is: the data terminal D of the data terminal D of described the first d type flip flop 721 and described the second d type flip flop 731 receives low-level data, i.e. the data terminal D ground connection of the data terminal D of described the first d type flip flop 721 and described the second d type flip flop 731; The significant level that the control end C of the control end C of described the first d type flip flop 721 and described the second d type flip flop 731 receives is high level.
Similar with the duty-ratio calibrating circuit shown in Fig. 2, the duty-ratio calibrating circuit shown in Fig. 7 also has multiple work schedule.The duty ratio of described input clock CKI of take is less than 50 percent, described the first d type flip flop 721 and described the second d type flip flop 731 are that rising edge d type flip flop is example, and Fig. 8 is the working timing figure of described duty-ratio calibrating circuit.
With reference to figure 7 and Fig. 8, through the half period delay of described half period delay circuit 21, to process, lag behind time of described input clock CKI of described the first delayed clock CKD1 is the half period of described input clock CKI; In the rising edge moment of described the first delayed clock CKD1, described output clock CKO is updated to low level; In the rising edge moment of described input clock CKI, the output state of described the first d type flip flop 721 is updated to low level; Through the non-processing of described the first not circuit 722, described control signal CKC is high level, controls described output clock CKO and is updated to high level; Described output clock CKO inputs the control end C of described the first d type flip flop 721, makes described control signal CKC be updated to low level, makes described the second d type flip flop 731 wait for next time and triggers.
Fig. 9～Figure 11 is another three kinds of working timing figures of the duty-ratio calibrating circuit shown in Fig. 7, wherein, Fig. 9 be that the duty ratio of described input clock CKI is greater than 50 percent, the work schedule of described the first d type flip flop 721 and described the second d type flip flop 731 duty-ratio calibrating circuit shown in Fig. 7 while being rising edge d type flip flop; Figure 10 is that the duty ratio of described input clock CKI is less than 50 percent, the work schedule of described the first d type flip flop 721 and described the second d type flip flop 731 duty-ratio calibrating circuit shown in Fig. 7 while being trailing edge d type flip flop; Figure 11 is that the duty ratio of described input clock CKI is greater than 50 percent, the work schedule of described the first d type flip flop 721 and described the second d type flip flop 731 duty-ratio calibrating circuit shown in Fig. 7 while being trailing edge d type flip flop.Work schedule and Fig. 8 of Fig. 9～Figure 11 are similar, do not repeat them here.
The duty-ratio calibrating circuit of the embodiment of the present invention has adopted d type flip flop and not circuit to realize, and because digital circuit is easy to conversion from a technique to another technique, thereby described duty-ratio calibrating circuit can simply be transplanted.
Figure 12 is the structural representation of the half period delay circuit of the embodiment of the present invention, described half period delay circuit comprises status signal generation unit 121, status unit 122 and (2 * N) individual first delay cell: the first delay cell D11 ..., the first delay cell D1N, the first delay cell D1 (N+1) ..., the first delay cell D1 (2 * N), N >=1 and N are positive integer.
Particularly, described the first delay cell comprises input, output and control end, and the control end of described the first delay cell is suitable for receiving conditioning signal Ctr, and described conditioning signal Ctr is suitable for regulating the time of delay of described the first delay cell.The initial delay time of described the first delay cell is definite according to Td < T0 ÷ (2 * N), and wherein, Td is the initial delay time of described the first delay cell, and T0 is the cycle of described input clock CKI.Described (2 * N) individual first delay cell is connect in series structure, and the output of n the first delay cell connects the input of (n+1) individual first delay cell, 1≤n≤(2 * N); The input of first first delay cell D11 is suitable for receiving described input clock CKI, the output of N the first delay cell D1N is suitable for producing described the first delayed clock CKD1, and the output of (2 * N) individual first delay cell D1 (2 * N) is suitable for producing the second delayed clock CKD2.
Described status signal generation unit 121 is suitable for producing status signal Flag according to described input clock CKI and described the second delayed clock CKD2.If described the second delayed clock CKD2 lags behind, the time of described input clock CKI equals the one-period of described input clock CKI, be that the rising edge of described input clock CKI and the rising edge synchronization of described the second delayed clock CKD2 arrive, described status signal Flag is high level; If described the second delayed clock CKD2 lags behind, the time of described input clock CKI is less than the one-period of described input clock CKI, and described status signal Flag is low level.
Described status unit 122 is suitable for producing described conditioning signal Ctr according to described status signal Flag.When described status signal Flag is low level, described the second delayed clock CKD2 lags behind time of described input clock CKI while being less than the one-period of described input clock CKI, and increase the time of delay that described conditioning signal Ctr controls described the first delay cell; When described status signal Flag is high level, be that described the second delayed clock CKD2 lags behind time of described input clock CKI while equaling the one-period of described input clock CKI, remain unchanged the time of delay that described conditioning signal Ctr controls described the first delay cell, thereby described the first delayed clock CKD1 half period that time of described input clock CKI is described input clock that lags behind.
In the present embodiment, described the first delay cell can be inverter.By regulating the current value that in inverter, tail current source provides, or regulate the capacitance of load capacitance in inverter, all can regulate the time of delay of described the first delay cell.Therefore, the conditioning signal Ctr that described status unit 122 produces according to described status signal Flag can be for controlling voltage or controlling electric current, and digital signal is converted to analog signal and controls.Those skilled in the art know how described status signal Flag is converted to described conditioning signal Ctr, know the particular circuit configurations of described status unit 122, do not repeat them here.
It should be noted that, the half period delay circuit in technical solution of the present invention can adopt the circuit structure shown in Figure 12, also can adopt half period delay circuit of the prior art, and the present invention is not construed as limiting this.
Figure 13 is the structural representation of the status signal generation unit 121 of the embodiment of the present invention, described status signal generation unit 121 comprises the second delay cell 131,3d flip-flop 132, four d flip-flop 133, the second not circuit 134 and AND circuit 135, and described 3d flip-flop 132 and described four d flip-flop 133 are trailing edge d type flip flop.
Described the second delay cell 131 is suitable for described input clock CKI to carry out delay disposal to produce the 3rd delayed clock CKD3, lag behind time of described input clock CKI of described the 3rd delayed clock CKD3 can arrange according to the actual requirements, as long as be enough to differentiate the clock edge of described the 3rd delayed clock CKD3.Similar with described the first delay cell, described the second delay cell 131 can be also inverter.The clock end Cl of described 3d flip-flop 132 is suitable for receiving described input clock CKI; The data terminal D of described 3d flip-flop 132 connects the data terminal D of described four d flip-flop 133 and is suitable for receiving described the second delayed clock CKD2; The output Q of described 3d flip-flop 132 connects the first input end of described AND circuit 135.The clock end Cl of described four d flip-flop 133 is suitable for receiving described the 3rd delayed clock CKD3; The output Q of described four d flip-flop 133 connects the input of described the second not gate 134 circuit.The output of described the second not circuit 134 connects the second input of described AND circuit 135; The output of described AND circuit 135 is suitable for producing described status signal Flag.
It is example that the duty ratio of described input clock CKI of take is less than 50 percent, and Figure 14 is the working timing figure of described status signal generation unit.In the trailing edge moment of described input clock CKI, if the trailing edge of described the second delayed clock CKD2 does not arrive, be lag behind time of described input clock CKI of described the second delayed clock CKD2 to be less than the one-period of described input clock CKI, may there are three kinds of combinations in the level of described 3d flip-flop 132 and 133 outputs of described four d flip-flop: described 3d flip-flop 132 output high level, described four d flip-flop 133 output high level, digital signal 11; Described 3d flip-flop 132 output low levels, described four d flip-flop 133 output high level, digital signaling zero 1; Described 3d flip-flop 132 output low levels, described four d flip-flop 133 output low levels, digital signaling zero 0.Above-mentioned three kinds of situations, the equal output low level of described AND circuit 135, described status signal Flag is low level.In the trailing edge moment of described input clock CKI, if the trailing edge of described the second delayed clock CKD2 arrives, be lag behind time of described input clock CKI of described the second delayed clock CKD2 to equal the one-period of described input clock CKI, described 3d flip-flop 132 is exported high level, described four d flip-flop 133 output low levels, and digital signal 10.Now, described AND circuit 135 output high level, described status signal Flag is high level.
It is example that the duty ratio of described input clock CKI of take is greater than 50 percent, and Figure 15 is the working timing figure of described status signal generation unit.The working timing figure of Figure 15 and the working timing figure of Figure 14 are similar, can, with reference to the description to Figure 14, not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a duty-ratio calibrating circuit, is characterized in that, comprising: half period delay circuit, control signal produce circuit and circuits for triggering;
Described half period delay circuit is suitable for input clock to carry out half period delay processing to produce the first delayed clock;
Described control signal produces circuit and is suitable for producing control signal according to described input clock, and described control signal is the first level in the triggering of described input clock along the moment, otherwise is second electrical level;
Described circuits for triggering are suitable for producing output clock according to described the first delayed clock and described control signal, the state of described output clock is updated to described second electrical level in the triggering of described the first delayed clock when arriving, and is updated to described the first level when described control signal is described the first level.
2. duty-ratio calibrating circuit as claimed in claim 1, is characterized in that, described control signal produces circuit and comprises the first d type flip flop and the first not circuit;
The clock end of described the first d type flip flop is suitable for receiving described input clock, the data terminal of described the first d type flip flop is suitable for receiving the first data-signal, the control end of described the first d type flip flop is suitable for receiving described output clock, the output of described the first d type flip flop connects the input of described the first not circuit, and described the first data-signal is described second electrical level;
The output of described the first not circuit is suitable for producing described control signal.
3. duty-ratio calibrating circuit as claimed in claim 1, is characterized in that, described circuits for triggering comprise the second d type flip flop;
The clock end of described the second d type flip flop is suitable for receiving described the first delayed clock, the data terminal of described the second d type flip flop is suitable for receiving the second data-signal, the control end of described the second d type flip flop is suitable for receiving described control signal, the output of described the second d type flip flop is suitable for producing described output clock, and described the second data-signal is described second electrical level.
4. duty-ratio calibrating circuit as claimed in claim 1, is characterized in that, described the first level is low level, and described second electrical level is high level.
5. duty-ratio calibrating circuit as claimed in claim 1, is characterized in that, described the first level is high level, and described second electrical level is low level.
6. the duty-ratio calibrating circuit as described in claim 1 to 5 any one, is characterized in that, described half period delay circuit comprises: status signal generation unit, status unit and (2 * N) individual first delay cell, and N >=1 and N are positive integer;
The control end of described the first delay cell is suitable for receiving conditioning signal, described conditioning signal is suitable for regulating the time of delay of described the first delay cell, the initial delay time of described the first delay cell is determined according to Td < T0 ÷ (2 * N), wherein, Td is the initial delay time of described the first delay cell, the cycle that T0 is described input clock;
Described (2 * N) individual first delay cell is connect in series structure, the input of first the first delay cell is suitable for receiving described input clock, the output of N the first delay cell is suitable for producing described the first delayed clock, and the output of (2 * N) individual first delay cell is suitable for producing the second delayed clock;
Described status signal generation unit is suitable for producing status signal according to described input clock and described the second delayed clock, described status signal is high level when the rising edge of described input clock and the arrival of the rising edge synchronization of described the second delayed clock, otherwise is low level;
Described status unit is suitable for producing described conditioning signal according to described status signal, increase the time of delay that described conditioning signal is controlled described the first delay cell when described status signal is low level, and remain unchanged the time of delay of controlling described the first delay cell when described status signal is high level.
7. duty-ratio calibrating circuit as claimed in claim 6, it is characterized in that, described status signal generation unit comprises the second delay cell, 3d flip-flop, four d flip-flop, the second not circuit and AND circuit, and described 3d flip-flop and described four d flip-flop are trailing edge d type flip flop;
Described the second delay cell is suitable for described input clock to carry out delay disposal to produce the 3rd delayed clock;
The clock end of described 3d flip-flop is suitable for receiving described input clock, the data terminal of described 3d flip-flop connects the data terminal of described four d flip-flop and is suitable for receiving described the second delayed clock, and the output of described 3d flip-flop connects the first input end of described AND circuit;
The clock end of described four d flip-flop is suitable for receiving described the 3rd delayed clock, and the output of described four d flip-flop connects the input of described the second not circuit;
The output of described the second not circuit connects the second input of described AND circuit;
The output of described AND circuit is suitable for producing described status signal.
8. duty-ratio calibrating circuit as claimed in claim 6, is characterized in that, described the first delay cell is inverter.
9. duty-ratio calibrating circuit as claimed in claim 8, is characterized in that, described conditioning signal is suitable for regulating the current value that in described inverter, tail current source provides.
10. duty-ratio calibrating circuit as claimed in claim 8, is characterized in that, described conditioning signal is suitable for regulating the capacitance of load capacitance in described inverter.
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| CN201410353784.6A CN104124945B (en) | 2014-07-23 | 2014-07-23 | Duty ratio calibrating circuit |
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| CN201410353784.6A CN104124945B (en) | 2014-07-23 | 2014-07-23 | Duty ratio calibrating circuit |
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| CN106301354A (en) * | 2015-05-29 | 2017-01-04 | 京微雅格（北京）科技有限公司 | A kind of duty cycle correction device and method |
| CN108832915A (en) * | 2018-09-13 | 2018-11-16 | 长江存储科技有限责任公司 | A kind of duty-ratio calibrating circuit |
| WO2019185054A1 (en) * | 2018-03-31 | 2019-10-03 | 华为技术有限公司 | Frequency multiplier, digital phase lock loop circuit and frequency multiplying method |
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| WO2021097799A1 (en) * | 2019-11-22 | 2021-05-27 | 深圳市汇顶科技股份有限公司 | Duty cycle calibration circuit |
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| JP3762281B2 (en) * | 2001-10-17 | 2006-04-05 | シャープ株式会社 | Test circuit and test method |
| CN101087132B (en) * | 2007-07-10 | 2010-05-19 | 中国人民解放军国防科学技术大学 | Adjustment method of clock fifty percent idle percent based on phase synthesis |
| US7705649B1 (en) * | 2008-04-03 | 2010-04-27 | National Semiconductor Corporation | Duty cycle correction circuit with small duty error and wide frequency range |
| CN101478300B (en) * | 2009-01-06 | 2010-09-15 | 东南大学 | Digital clock duty ratio calibrating circuit |
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| CN106301354A (en) * | 2015-05-29 | 2017-01-04 | 京微雅格（北京）科技有限公司 | A kind of duty cycle correction device and method |
| WO2019185054A1 (en) * | 2018-03-31 | 2019-10-03 | 华为技术有限公司 | Frequency multiplier, digital phase lock loop circuit and frequency multiplying method |
| US11101808B2 (en) | 2018-03-31 | 2021-08-24 | Huawei Technologies Co., Ltd. | Frequency multiplier, digital phase-locked loop circuit, and frequency multiplication method |
| CN108832915A (en) * | 2018-09-13 | 2018-11-16 | 长江存储科技有限责任公司 | A kind of duty-ratio calibrating circuit |
| WO2021097799A1 (en) * | 2019-11-22 | 2021-05-27 | 深圳市汇顶科技股份有限公司 | Duty cycle calibration circuit |
| US11115014B2 (en) | 2019-11-22 | 2021-09-07 | Shenzhen GOODIX Technology Co., Ltd. | Duty cycle correction circuit |
| CN110928824A (en) * | 2019-11-27 | 2020-03-27 | 西安紫光国芯半导体有限公司 | High frequency off-line driver |
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| WO2023143632A1 (en) * | 2022-01-28 | 2023-08-03 | 杭州士兰微电子股份有限公司 | Trigger unit performing clock gating based on data comparison |
| CN115179695A (en) * | 2022-08-16 | 2022-10-14 | 南京英锐创电子科技有限公司 | Signal detection circuit and tire pressure monitoring system |
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