CN115179695B - Signal detection circuit and tire pressure monitoring system - Google Patents
Signal detection circuit and tire pressure monitoring system Download PDFInfo
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- CN115179695B CN115179695B CN202210982513.1A CN202210982513A CN115179695B CN 115179695 B CN115179695 B CN 115179695B CN 202210982513 A CN202210982513 A CN 202210982513A CN 115179695 B CN115179695 B CN 115179695B
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- 238000001514 detection method Methods 0.000 title claims abstract description 39
- 238000012544 monitoring process Methods 0.000 title claims abstract description 22
- 230000003111 delayed effect Effects 0.000 claims description 14
- 230000000630 rising effect Effects 0.000 claims description 14
- 238000012360 testing method Methods 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 description 11
- 230000007613 environmental effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- IRUJZVNXZWPBMU-UHFFFAOYSA-N cartap Chemical compound NC(=O)SCC(N(C)C)CSC(N)=O IRUJZVNXZWPBMU-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000002618 waking effect Effects 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60C—VEHICLE TYRES; TYRE INFLATION; TYRE CHANGING; CONNECTING VALVES TO INFLATABLE ELASTIC BODIES IN GENERAL; DEVICES OR ARRANGEMENTS RELATED TO TYRES
- B60C23/00—Devices for measuring, signalling, controlling, or distributing tyre pressure or temperature, specially adapted for mounting on vehicles; Arrangement of tyre inflating devices on vehicles, e.g. of pumps or of tanks; Tyre cooling arrangements
- B60C23/02—Signalling devices actuated by tyre pressure
- B60C23/04—Signalling devices actuated by tyre pressure mounted on the wheel or tyre
- B60C23/0408—Signalling devices actuated by tyre pressure mounted on the wheel or tyre transmitting the signals by non-mechanical means from the wheel or tyre to a vehicle body mounted receiver
- B60C23/0422—Signalling devices actuated by tyre pressure mounted on the wheel or tyre transmitting the signals by non-mechanical means from the wheel or tyre to a vehicle body mounted receiver characterised by the type of signal transmission means
- B60C23/0433—Radio signals
- B60C23/0447—Wheel or tyre mounted circuits
- B60C23/0455—Transmission control of wireless signals
- B60C23/0464—Transmission control of wireless signals to avoid signal interference
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Abstract
The invention relates to a signal detection circuit and a tire pressure monitoring system, wherein the signal detection circuit comprises a delay trigger circuit, a reset control module and a second D trigger, the delay trigger circuit comprises a first AND gate circuit and m cascaded first D triggers, a first input end of a first D trigger is used for receiving high-level signals, a second input end of each first D trigger is used for receiving signals to be detected, a first output end of an nth first D trigger is connected with a first input end of the first AND gate circuit, a second output end of the mth first D trigger is connected with a second input end of the first AND gate circuit, the reset control module is used for resetting each first D trigger in sequence according to clock signals, a first input end of the second D trigger is connected with an output end of the first AND gate circuit, and a second input end of the second D trigger is used for receiving the clock signals. The signal detection circuit can detect signals with frequencies within an effective range.
Description
Technical Field
The present invention relates to the field of signal detection technologies, and in particular, to a signal detection circuit and a tire pressure monitoring system.
Background
Currently, tire pressure monitoring systems are primarily awakened by low frequency carrier signals (e.g., 125KHz carrier), and in order to save power consumption, the system needs to periodically turn on the carrier receiving circuit to detect whether there is a low frequency signal.
However, in an actual application scenario, the environmental noise is more, the carrier receiving circuit easily judges the environmental noise as a low-frequency signal for waking up the tire pressure monitoring system, so that the tire pressure monitoring system is frequently and wrongly waken up, the power consumption of the tire pressure monitoring system is greatly increased, and the consumption of the battery power is further accelerated.
Disclosure of Invention
Based on this, it is necessary to provide a signal detection circuit and a tire pressure monitoring system that reduce the interference of environmental noise.
A signal detection circuit, comprising:
the delay trigger circuit comprises a first AND gate circuit and m cascaded first D triggers, wherein the first input end of a first D trigger of a first stage is used for receiving a high-level signal, the first input end of a first D trigger of an upper stage is connected with the first input end of a first D trigger of a next stage, the second input end of each first D trigger is used for receiving a signal to be detected, the first output end of a first D trigger of an nth stage is connected with the first input end of the first AND gate circuit, the second output end of the first D trigger of an mth stage is connected with the second input end of the first AND gate circuit, and m is more than n and is more than or equal to 1;
the output end of the reset control module is connected with the reset end of each first D trigger, and the reset control module is used for resetting each first D trigger in sequence according to the clock signals, wherein the reset interval period of each first D trigger by the reset control module is one clock period;
the first input end of the second D trigger is connected with the output end of the first AND gate circuit, the second input end of the second D trigger is used for receiving a clock signal, and the second D trigger is used for responding to the clock signal to trigger so as to output an identification signal indicating whether the signal to be tested is valid or not.
In the signal detection circuit, the first input end of the first D trigger of the first stage is used for receiving high-level signals, and the second input end of each first D trigger receives signals to be detected, so that the circuit starts to work, and the high-level signals are sampled for a plurality of beats by the signals to be detected; the first output end of the first D trigger of the nth stage is connected with the first input end of the first AND gate circuit, the second output end of the first D trigger of the mth stage is connected with the second input end of the first AND gate circuit, the first input end of the second D trigger is connected with the output end of the first AND gate circuit, the second input end of the second D trigger is connected with the output end of the clock module, the reset control module resets each first D trigger after the triggering edge of the clock signal, so that when the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal, the second D trigger can output a high-level signal, namely an identification signal indicating that the signal to be detected is effective, whether the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal can be detected through the identification signal, thereby eliminating noise signals with frequencies not between n times and m times of the frequency of the clock signal, and reducing interference of environmental noise.
In one embodiment, the signal detection circuit further comprises:
and the enabling module is connected with the reset end of the second D trigger and is used for outputting a control signal to the second D trigger so as to control the second D trigger to work or reset.
In one embodiment, the enabling module includes:
the control submodule is used for alternately generating a first indication signal and a second indication signal;
and the first NOT circuit is used for outputting a control signal for controlling the second D trigger to work according to the first indication signal when the first indication signal is received, and outputting a control signal for controlling the second D trigger to reset according to the second indication signal when the second indication signal is received.
In one embodiment, the enabling module includes:
and the control sub-module is used for generating the corresponding control signals according to the external instructions.
In one embodiment, the reset control module includes:
the input end of the first delay sub-module is used as the input end of the reset control module and is used for delaying the clock signal and outputting a first delayed clock signal;
the input end of the second delay sub-module is connected with the output end of the first delay sub-module and is used for delaying the first delay clock signal and outputting a second delay clock signal;
the input end of the second NOT gate circuit is connected with the output end of the second delay submodule and is used for outputting a second delay clock inversion signal according to the second delay clock signal;
the first input end of the modulation submodule is connected with the output end of the first delay submodule, the second input end of the modulation submodule is connected with the output end of the second NOT gate circuit, the output end of the modulation submodule is used as the output end of the reset control module, and the modulation submodule is used for outputting a target reset signal according to the first delay clock signal and the second delay clock inversion signal so as to reset each first D trigger in sequence.
In one embodiment, the modulation submodule includes:
the first input end of the second AND gate circuit is used as the first input end of the modulation submodule, the second input end of the second AND gate circuit is used as the second input end of the modulation submodule, and the output end of the second AND gate circuit is used as the output end of the modulation submodule and used for generating a target reset signal according to the first delay clock signal and the second delay clock flip-bit signal and outputting the target reset signal to each first D trigger.
In one embodiment, the first D flip-flop and the second D flip-flop are high level reset flip-flops; the modulation submodule includes:
the first input end of the second AND gate circuit is used as the first input end of the modulation submodule, and the second input end of the second AND gate circuit is used as the second input end of the modulation submodule and is used for generating a modulation signal according to the first delay clock signal and the second delay clock flip signal;
the first input end of the OR gate circuit is connected with the output end of the second AND gate circuit, the second input end of the OR gate circuit is connected with the output end of the enabling module, and the output end of the OR gate circuit serves as the output end of the modulation submodule and is used for generating a target reset signal according to the control signal and the modulation signal and outputting the target reset signal to each first D trigger.
In one embodiment, the delay flip-flop circuit includes a first and gate circuit and five cascaded first D flip-flops, a first output terminal of a third stage first D flip-flop is connected to a first input terminal of the first and gate circuit, and a second output terminal of a fifth stage first D flip-flop is connected to a second input terminal of the first and gate circuit.
In one embodiment, the first D flip-flop and the second D flip-flop are both rising edge flip-flops.
A tyre pressure monitoring system comprising a signal detection circuit as claimed in any one of the preceding claims and a processor, the signal detection circuit being connected to the processor, the processor being arranged to receive the identification signal and to wake up the tyre pressure monitoring system when the identification signal indicates that the signal to be tested is valid.
According to the tire pressure monitoring system, the signal detection circuit can eliminate noise signals with the frequency not being n times and m times of the frequency of the clock signal, so that the interference of environmental noise is reduced, the tire pressure monitoring system is prevented from being awakened by mistake frequently, the power consumption of the tire pressure monitoring system is reduced, and the consumption of the battery power is reduced.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIGS. 1-7 are schematic diagrams illustrating the structure of a signal detection circuit according to various embodiments;
FIG. 8 is a timing diagram of signal detection when the signal under test is a valid signal in one embodiment;
FIG. 9 is a timing diagram of signal detection when the signal under test is faster in one embodiment;
FIG. 10 is a timing diagram of signal detection when the signal under test is slow in one embodiment;
fig. 11 is a block diagram of a tire pressure monitoring system in one embodiment.
Reference numerals illustrate:
10-signal detection circuit, 1-delay trigger circuit, 11-first D trigger, 12-first AND gate circuit, 2-reset control module, 21-first delay submodule, 22-second delay submodule, 23-second NOT gate circuit, 24-modulation submodule, 241-second AND gate circuit, 242-OR gate circuit, 3-second D trigger, 4-enable module, 41-control submodule, 42-first NOT gate circuit, 20-processor, 30-tire pressure monitoring system.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first D flip-flop may be referred to as a second D flip-flop, and similarly, a second D flip-flop may be referred to as a first D flip-flop, without departing from the scope of the present application. Both the first D flip-flop and the second D flip-flop are D flip-flops, but they are not the same D flip-flop.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, sub-modules, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and the like, specify the presence of stated features, integers, components, portions, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, components, portions, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In one embodiment, as shown in fig. 1, the present application provides a signal detection circuit 10 comprising: a delay flip-flop circuit 1, a reset control module 2 and a second D flip-flop 3. The delay trigger circuit 1 comprises a first AND gate circuit 12 and m cascaded first D triggers 11, wherein a first input end of a first stage first D trigger 11 is used for receiving a high-level signal, a first input end of a previous stage first D trigger 11 is connected with a first input end of a next stage first D trigger 11, a second input end of each first D trigger 11 is used for receiving a signal to be detected, a first output end of an nth stage first D trigger 11 is connected with a first input end of the first AND gate circuit 12, a second output end of the mth stage first D trigger 11 is connected with a second input end of the first AND gate circuit 12, and m is more than n and n is more than or equal to 1. The input end of the reset control module 2 is used for receiving clock signals, the output end of the reset control module 2 is connected with the reset end of each first D trigger 11, and the reset control module 2 is used for resetting each first D trigger 11 in sequence according to the clock signals, wherein the reset interval period of each first D trigger 11 by the reset control module 2 is one clock period. The first input end of the second D flip-flop 3 is connected to the output end of the first and gate 12, the second input end of the second D flip-flop 3 is used for receiving the clock signal, and the second D flip-flop 3 is used for responding to the clock signal to trigger so as to output an identification signal indicating whether the signal to be tested is valid.
Wherein, the triggering edge of the clock signal is related to the second D flip-flop 3, and if the second D flip-flop 3 is a rising edge flip-flop, the triggering edge is a rising edge; if the second D flip-flop 3 is a falling edge flip-flop, the triggering edge is a falling edge. The first D flip-flop 11 and the second D flip-flop 3 may be falling edge flip-flops or rising edge flip-flops. The reset node of the first D flip-flop 11 is later than the trigger node of the second D flip-flop 3.
Specifically, since the second input terminal of each first D flip-flop 11 is used for receiving the signal to be tested, the first D flip-flop 11 is triggered to operate by the signal to be tested, and the first D flip-flop 11 is reset every other clock cycle. It will be understood that when the frequency of the signal to be measured is less than n times the frequency of the clock signal, and the first D flip-flop 11 of the nth stage and the first D flip-flop 11 of the mth stage enter the reset state before being triggered, the first output terminal of the first D flip-flop 11 of the nth stage continuously outputs the low level signal, the second output terminal of the first D flip-flop 11 of the mth stage continuously outputs the high level signal, the first and gate 12 continuously outputs the low level signal, and the second D flip-flop 3 continuously outputs the low level signal in response to the triggering of the clock signal. When the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal, the first D trigger 11 of the nth stage is triggered, the first D trigger 11 of the mth stage enters a reset state before triggering, the first D trigger 11 of the nth stage outputs a high-level signal before the trigger node is reset to the next time, the first D trigger 11 of the mth stage continuously outputs the high-level signal, and the output signal of the first AND gate circuit 12 is the same as the output signal of the first D trigger 11 of the nth stage; since the frequency of the signal to be tested is between n times and m times of the frequency of the clock signal, and since the reset control module 2 resets each first D flip-flop 11 after the triggering edge of the clock signal, the second D flip-flop 3 responds to the fact that the nth stage first D flip-flop 11 is triggered and not yet reset when the clock signal is triggered, at this time, the first and gate 12 outputs a high level signal, and the first output end of the second D flip-flop 3 also outputs a high level signal. When the frequency of the signal to be tested is m times greater than the frequency of the clock signal, the first D flip-flop 11 of the nth stage and the first D flip-flop 11 of the mth stage are triggered, the first D flip-flop 11 of the nth stage outputs a high-level signal before the trigger node is reset to the next time, the first D flip-flop 11 of the mth stage outputs a low-level signal before the trigger node is reset to the next time, similarly, the first D flip-flop 11 of the mth stage is triggered and not reset when the second D flip-flop 3 responds to the clock signal, at this time, the first and circuit 12 outputs a low-level signal, the first output end of the second D flip-flop 3 also outputs a low-level signal, no level change occurs in the second D flip-flop 3, and the first output end of the second D flip-flop 3 continuously outputs a low-level signal. Based on the above, it can be found that when the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal, the first output end of the second D flip-flop 3 outputs the pulse signal, that is, the identification signal is a pulse signal, and when the frequency of the signal to be detected is less than n times or greater than m times of the frequency of the clock signal, the identification signal is a continuous low level signal, and whether the signal to be detected is valid (that is, whether the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal) can be determined according to the characteristics of the identification signal.
In this embodiment, the first input terminal of the first D flip-flop 11 of the first stage is used to receive the high level signal, and the second input terminal of each first D flip-flop 11 receives the signal to be tested, so that the circuit starts to work, and the high level signal is sampled for multiple beats by the signal to be tested; the first output end of the nth stage first D flip-flop 11 is connected with the first input end of the first and gate 12, the second output end of the mth stage first D flip-flop 11 is connected with the second input end of the first and gate 12, the first input end of the second D flip-flop 3 is connected with the output end of the first and gate 12, the second input end of the second D flip-flop 3 is connected with the output end of the clock module, and the reset control module 2 resets each first D flip-flop 11 after the triggering edge of the clock signal, so that when the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal, the second D flip-flop 3 outputs a high level signal, namely an identification signal indicating that the signal to be detected is effective, and whether the frequency of the signal to be detected is between n times and m times of the frequency of the clock signal can be detected through the identification signal, thereby eliminating noise signals with frequencies not between n times and m times of the frequency of the clock signal, and reducing interference of environmental noise.
In one embodiment, as shown in fig. 2, the signal detection circuit 10 further includes an enabling module 4, where the enabling module 4 is connected to the reset terminal of the second D flip-flop 3, and is configured to output a control signal to the second D flip-flop 3 to control the second D flip-flop 3 to operate or reset.
It will be appreciated that when the second D flip-flop 3 is in the reset state, the second D flip-flop 3 will not be triggered in response to the clock signal, the output signal of the first output terminal of the second D flip-flop 3 is unchanged, and based on the characteristics of the second D flip-flop 3, a corresponding control signal may be output to the second D flip-flop 3 to control the second D flip-flop 3 to operate or reset.
The second D flip-flop 3 is illustratively a high level reset flip-flop, and is reset when the control signal is a high level signal, and is in an operating state when the control signal is a low level signal, i.e. is in a triggerable state when the control signal is a low level signal.
In one embodiment, as shown in FIG. 3, the enable module 4 includes a control sub-module 41 and a first NOT 42. The control sub-module 41 is configured to alternately generate a first indication signal and a second indication signal; the first not circuit 42 is configured to output a control signal for controlling the second D flip-flop 3 to operate according to the first indication signal when the first indication signal is received, and output a control signal for controlling the second D flip-flop 3 to reset according to the second indication signal when the second indication signal is received.
Specifically, if the first indication signal and the second indication signal are opposite logic level signals, the control signal generated by the first not gate 42 according to the first indication signal and the second indication signal is also opposite logic level signal, and since the control sub-module 41 alternately generates the first indication signal and the second indication signal, the enabling module 4 can control the second D flip-flop 3 to periodically operate and reset, so as to periodically detect the signal to be detected.
In application, the enabling module 4 may include a control submodule 41, where the control submodule 41 is configured to alternately generate a control signal for controlling the operation of the second D flip-flop 3 and a control signal for controlling the reset of the second D flip-flop 3.
In another embodiment, the enabling module 4 includes a control submodule 41, and the control submodule 41 is configured to generate a corresponding control signal according to an external instruction.
It can be understood that, since the control sub-module 41 is configured to generate a corresponding control signal according to an external instruction, the second D flip-flop 3 can be manually controlled to operate or reset, so as to manually control whether to detect the signal to be detected.
In one embodiment, as shown in fig. 4, the reset control module 2 includes a first delay sub-module 21 and a second delay sub-module 22. The input terminal of the first delay sub-module 21 is used as the input terminal of the reset control module 2, and is used for delaying the clock signal and outputting a first delayed clock signal. The input end of the second delay sub-module 22 is connected to the output end of the first delay sub-module 21, and is used for delaying the first delay clock signal and outputting a second delay clock signal. And the input end of the second NOT circuit 23 is connected with the output end of the second delay sub-module 22 and is used for outputting a second delay clock inversion signal according to the second delay clock signal. The first input end of the modulation submodule 24 is connected with the output end of the first delay submodule 21, the second input end of the modulation submodule 24 is connected with the output end of the second NOT gate 23, the output end of the modulation module serves as the output end of the reset control module 2, and the modulation submodule 24 is used for outputting a target reset signal according to the first delay clock signal and the second delay clock flip-bit signal so as to reset each first D trigger 11 in sequence.
It may be appreciated that, when the first delayed clock signal and the second delayed clock flip signal are both delayed relative to the clock signal, the reset node of the target reset signal output according to the first delayed clock signal and the second delayed clock flip signal may be after the trigger edge of the clock signal, and the interval between two adjacent reset nodes of the target reset signal may be one clock cycle.
In one embodiment, as shown in FIG. 5, the modulation submodule 24 includes a second AND gate 241. The first input terminal of the second and circuit 241 is used as the first input terminal of the modulation sub-module 24, the second input terminal of the second and circuit 241 is used as the second input terminal of the modulation sub-module 24, and the output terminal of the second and circuit is used as the output terminal of the modulation sub-module 24 for generating a target reset signal according to the first delay clock signal and the second delay clock flip-bit signal, and outputting the target reset signal to each first D flip-flop 11.
Illustratively, as shown in fig. 4, a reset signal having a rising edge after the rising edge of the clock signal may be generated based on the first delayed clock signal and the second delayed clock flip-bit signal, and the interval of the reset nodes is one clock period, so that each first D flip-flop 11 is controlled to be reset at an appropriate node, so that the second D flip-flop 3 outputs an identification signal indicating whether the signal to be tested is valid.
In one embodiment, as shown in fig. 6, the first D flip-flop 11 and the second D flip-flop 3 are high level reset flip-flops. The modulation submodule 24 includes a second and circuit 241 and an or circuit 242. A first input terminal of the second and circuit 241 is used as a first input terminal of the modulation sub-module 24, and a second input terminal of the second and circuit 241 is used as a second input terminal of the modulation sub-module 24 for generating a modulation signal according to the first delayed clock signal and the second delayed clock flip signal; a first input terminal of the or circuit 242 is connected to an output terminal of the second and circuit 241, a second input terminal of the or circuit 242 is connected to an output terminal of the enable module 4, and an output terminal of the or circuit 242 serves as an output terminal of the modulation submodule 24, and is configured to generate a target reset signal according to the control signal and the modulation signal, and output a second reset signal to each first D flip-flop 11.
Specifically, since the first D flip-flop 11 and the second D flip-flop 3 are high-level reset flip-flops, based on the characteristics of the or circuit 242, when the control signal is a high-level signal, the target reset signal is also a high-level signal, and when the control signal is a low-level signal, the target reset signal is the same as the modulation signal, and when the second D flip-flop 3 receives the control signal for reset, each first D flip-flop 11 is also reset, thereby avoiding the operation of each first D flip-flop 11 when the second D flip-flop 3 is in the reset state, and reducing the power consumption.
In another embodiment, the first D flip-flop 11 and the second D flip-flop 3 are low level reset flip-flops; the modulation submodule 24 includes a second and gate 241 and a third and gate. A first input terminal of the second and circuit 241 is used as a first input terminal of the modulation sub-module 24, and a second input terminal of the second and circuit 241 is used as a second input terminal of the modulation sub-module 24 for generating a modulation signal according to the first delayed clock signal and the second delayed clock flip signal; the first input end of the third and circuit is connected to the output end of the second and circuit 241, the second input end of the third and circuit is connected to the output end of the enabling module 4, and the output end of the third and circuit is used as the output end of the modulating sub-module 24, and is used for generating a target reset signal according to the control signal and the modulating signal, and outputting a second reset signal to each first D flip-flop 11.
Specifically, when the first D flip-flop 11 and the second D flip-flop 3 are low-level reset flip-flops, based on the characteristics of the and circuit, when the control signal is a low-level signal, the target reset signal is also a low-level signal, when the control signal is a high-level signal, the target reset signal is the same as the modulation signal, and when the second D flip-flop 3 receives the control signal for reset, each first D flip-flop 11 is also reset, thereby avoiding the operation of each first D flip-flop 11 when the second D flip-flop 3 is in a reset state, and reducing power consumption.
Based on the above embodiments, exemplarily, as shown in fig. 7, the first D flip-flop 11 and the second D flip-flop 3 are both rising edge flip-flops; the delay trigger circuit 1 comprises five cascaded first D triggers 11 and a first AND gate circuit 12, wherein a first output end of a third-stage first D trigger 11 is connected with a first input end of the first AND gate circuit 12, and a second output end of a fifth-stage first D trigger 11 is connected with a second input end of the first AND gate circuit 12; the third stage first D flip-flop 11 is triggered at the third rising edge of the signal under test, and the fifth stage first D flip-flop 11 is triggered at the fifth rising edge of the signal under test. The frequency of the clock signal is 32 Khz; if the signal to be detected is in the detection range (the frequency is between 3 times and 5 times of 32K, 96Khz-160 Khz), the signal detection time sequence is shown in FIG. 8. When check_en (signal output by the control submodule) =1, check_enb (control signal) =0, when the second D flip-flop 3 is in a triggerable state, clk_32k (clock signal of 32 Khz) is triggered by the rising edge of the clock signal, the first D flip-flop 11 is reset at a high level, the rising edge of the target reset signal car_clr is a reset node, and it can be found that the rising edge of the target reset signal car_clr is located after the rising edge of the clock signal, then the reset node of the first D flip-flop 11 is located after the trigger node of the second D flip-flop 3, at this time, car_tap3 (output signal of the first output terminal of the third stage first D flip-flop 11) =1 (high level), car_tap5_n (output signal of the second output terminal of the fifth stage first D flip-flop 11) =1, car_valid_pre (output signal of the output terminal of the first and gate 12) =1, and the second output signal of the second D flip-flop 3 (output signal of the fifth stage first and valid signal 1) =1.
If the signal to be measured is faster (the frequency is greater than 5 times of 32K and greater than 160 Khz), the signal detection timing is shown in fig. 9, when clk_32k rises, car_tap 3=1, car_tap 5_n=0 (low level), and car_valid_pre=0, and the signal to be measured is an invalid signal.
If the signal to be measured is slow (the frequency is less than 3 times of 32K and less than 96 Khz), the signal detection timing is shown in fig. 10, when clk_32k rises, car_tap 3=0, car_tap 5_n=1, and car_valid_pre=0, so car_valid=0 (identification signal), and the signal to be measured is an invalid signal. Thus, a circuit based on the above example can effectively exclude signals with frequencies outside 96Khz-160 Khz.
In one embodiment, as shown in fig. 11, the present application further provides a tire pressure monitoring system 30, including the signal detection circuit 10 and the processor 20 as described above, where the signal detection circuit 10 is connected to the processor 20, and the processor 20 is configured to receive an identification signal, and wake up the tire pressure monitoring system 30 when the identification signal indicates that the signal to be tested is valid.
In this embodiment, the signal detection circuit 10 can eliminate noise signals with frequencies not between n times and m times of the clock signal frequency, so as to reduce interference of environmental noise, and further avoid frequent false wake-up of the tire pressure monitoring system 30, thereby reducing power consumption of the tire pressure monitoring system 30 and reducing consumption of battery power.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A signal detection circuit, comprising:
the delay trigger circuit comprises a first AND gate circuit and m cascaded first D triggers, wherein the first input end of a first D trigger of a first stage is used for receiving a high-level signal, the first input end of a first D trigger of an upper stage is connected with the first input end of a first D trigger of a next stage, the second input end of each first D trigger is used for receiving a signal to be detected, the first output end of a first D trigger of an nth stage is connected with the first input end of the first AND gate circuit, the second output end of the first D trigger of an mth stage is connected with the second input end of the first AND gate circuit, and m is more than n and is more than or equal to 1;
the input end of the reset control module is used for receiving clock signals, the output end of the reset control module is connected with the reset end of each first D trigger, and the reset control module comprises: the input end of the first delay submodule is used as the input end of the reset control module and is used for delaying the clock signal and outputting a first delayed clock signal; the input end of the second delay sub-module is connected with the output end of the first delay sub-module and is used for delaying the first delay clock signal and outputting a second delay clock signal; the input end of the second NOT circuit is connected with the output end of the second delay submodule and is used for outputting a second delay clock inversion signal according to the second delay clock signal; the first input end of the modulation submodule is connected with the output end of the first delay submodule, the second input end of the modulation submodule is connected with the output end of the second NOT gate circuit, the output end of the modulation submodule is used as the output end of the reset control module, and the modulation submodule is used for outputting a target reset signal according to the first delay clock signal and the second delay clock flip-bit signal so as to reset each first D trigger in sequence, wherein the reset interval period of each first D trigger by the reset control module is one clock period;
the first input end of the second D trigger is connected with the output end of the first AND gate circuit, the second input end of the second D trigger is used for receiving a clock signal, and the second D trigger is used for responding to the clock signal to trigger so as to output an identification signal indicating whether the signal to be tested is valid or not;
and the enabling module is connected with the reset end of the second D trigger and is used for outputting a control signal to the second D trigger so as to control the second D trigger to work or reset.
2. The signal detection circuit of claim 1, wherein the enabling module comprises:
the control submodule is used for alternately generating a first indication signal and a second indication signal;
and the first NOT circuit is used for outputting a control signal for controlling the second D trigger to work according to the first indication signal when the first indication signal is received, and outputting a control signal for controlling the second D trigger to reset according to the second indication signal when the second indication signal is received.
3. The signal detection circuit of claim 1, wherein the enabling module comprises:
and the control sub-module is used for generating the corresponding control signals according to the external instructions.
4. The signal detection circuit of claim 1, wherein the modulation submodule comprises:
the first input end of the second AND gate circuit is used as the first input end of the modulation submodule, the second input end of the second AND gate circuit is used as the second input end of the modulation submodule, and the output end of the second AND gate circuit is used as the output end of the modulation submodule and is used for generating the target reset signal according to the first delay clock signal and the second delay clock flip-bit signal and outputting the target reset signal to each first D trigger.
5. The signal detection circuit of claim 1, wherein the first D flip-flop and the second D flip-flop are high level reset flip-flops; the modulation submodule includes:
the first input end of the second AND gate circuit is used as the first input end of the modulation submodule, and the second input end of the second AND gate circuit is used as the second input end of the modulation submodule and is used for generating a modulation signal according to the first delay clock signal and the second delay clock flip signal;
the first input end of the OR gate circuit is connected with the output end of the second AND gate circuit, the second input end of the OR gate circuit is connected with the output end of the enabling module, and the output end of the OR gate circuit serves as the output end of the modulation submodule and is used for generating the target reset signal according to the control signal and the modulation signal and outputting the target reset signal to each first D trigger.
6. The signal detection circuit of claim 1, wherein the delay flip-flop circuit comprises a first and gate circuit and five cascaded first D flip-flops, a first output terminal of a third stage first D flip-flop is connected to a first input terminal of the first and gate circuit, and a second output terminal of a fifth stage first D flip-flop is connected to a second input terminal of the first and gate circuit.
7. The signal detection circuit of claim 1, wherein the first D flip-flop and the second D flip-flop are both rising edge flip-flops.
8. The signal detection circuit of claim 1, wherein the identification signal is a pulse signal.
9. The signal detection circuit of claim 1, wherein the identification signal is a continuous low level signal when the frequency of the signal under test is less than n times the frequency of the clock signal or greater than m times the frequency of the clock signal.
10. A tyre pressure monitoring system comprising a signal detection circuit as claimed in any one of claims 1 to 9 and a processor, the signal detection circuit being connected to the processor, the processor being arranged to receive the identification signal and to wake up the tyre pressure monitoring system when the identification signal indicates that the signal to be tested is valid.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1238600A (en) * | 1998-03-17 | 1999-12-15 | 摩托罗拉公司 | Phase detection apparatus |
| CN102133844A (en) * | 2010-01-22 | 2011-07-27 | 联创汽车电子有限公司 | Vehicle tire pressure detection system |
| CN102419417A (en) * | 2011-08-17 | 2012-04-18 | 北京时代民芯科技有限公司 | Test circuit for propagation delay of triggers in FPGA (Field Programmable Gate Array) |
| CN104124945A (en) * | 2014-07-23 | 2014-10-29 | 上海华虹宏力半导体制造有限公司 | Duty ratio calibrating circuit |
| CN104242920A (en) * | 2014-09-24 | 2014-12-24 | 上海华力微电子有限公司 | Locking detection circuit for phase-locked loop circuit |
| CN108362991A (en) * | 2017-01-13 | 2018-08-03 | 联发科技股份有限公司 | Scan chain circuit |
| CN109450441A (en) * | 2018-12-27 | 2019-03-08 | 上海华力集成电路制造有限公司 | The phaselocked loop of lock detecting circuit and its composition |
| CN114421933A (en) * | 2022-01-21 | 2022-04-29 | 长江存储科技有限责任公司 | Glitch detection and processing circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI757819B (en) * | 2020-08-06 | 2022-03-11 | 華邦電子股份有限公司 | Delay control device and tunable delay device |
-
2022
- 2022-08-16 CN CN202210982513.1A patent/CN115179695B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1238600A (en) * | 1998-03-17 | 1999-12-15 | 摩托罗拉公司 | Phase detection apparatus |
| CN102133844A (en) * | 2010-01-22 | 2011-07-27 | 联创汽车电子有限公司 | Vehicle tire pressure detection system |
| CN102419417A (en) * | 2011-08-17 | 2012-04-18 | 北京时代民芯科技有限公司 | Test circuit for propagation delay of triggers in FPGA (Field Programmable Gate Array) |
| CN104124945A (en) * | 2014-07-23 | 2014-10-29 | 上海华虹宏力半导体制造有限公司 | Duty ratio calibrating circuit |
| CN104242920A (en) * | 2014-09-24 | 2014-12-24 | 上海华力微电子有限公司 | Locking detection circuit for phase-locked loop circuit |
| CN108362991A (en) * | 2017-01-13 | 2018-08-03 | 联发科技股份有限公司 | Scan chain circuit |
| CN109450441A (en) * | 2018-12-27 | 2019-03-08 | 上海华力集成电路制造有限公司 | The phaselocked loop of lock detecting circuit and its composition |
| CN114421933A (en) * | 2022-01-21 | 2022-04-29 | 长江存储科技有限责任公司 | Glitch detection and processing circuit |
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