CN114421933A

CN114421933A - Glitch detection and processing circuit

Info

Publication number: CN114421933A
Application number: CN202210070477.1A
Authority: CN
Inventors: 王勇勇; 魏汝新; 蔡友刚
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2022-04-29

Abstract

Disclosed is a burr detection and processing circuit, comprising: a glitch detection module for detecting a glitch occurring in an input signal of the glitch detection and processing circuit, wherein the glitch has a first pulse width; a glitch extension module for generating a glitch extension signal having pulses of a second pulse width that is pre-configured in response to the glitch detection module detecting a glitch in the input signal, wherein the pulses in the glitch extension signal correspond to the glitch in the input signal and the second pulse width is greater than the first pulse width.

Description

Glitch detection and processing circuit

Technical Field

Embodiments of the present disclosure relate to electronic circuits, and more particularly, to circuits for detecting and processing glitches occurring in electronic signals.

Background

In electronic or integrated circuitry, such as a system on a chip (SoC), the wires and signals conducted thereon are susceptible to various electrical noises, which introduce undesirable interference into the signals.

For example, the presence of glitches in a signal, which may affect the proper operation of a logic circuit, is difficult to avoid. Therefore, it is desirable to detect and process glitches occurring in the signal to reduce or avoid their effect.

Disclosure of Invention

In one embodiment, a burr detection and processing circuit is disclosed, comprising: a glitch detection module for detecting a glitch occurring in an input signal of the glitch detection and processing circuit, wherein the glitch has a first pulse width; a glitch extension module to generate a glitch extension signal having pulses of a preconfigured second pulse width in response to the glitch detection module detecting the glitch in the input signal, wherein the pulses in the glitch extension signal correspond to the glitch in the input signal, the second pulse width being greater than the first pulse width.

In one embodiment, a burr detection and processing circuit is disclosed, comprising: a first SR flip-flop, whose set input terminal receives the input signal of the glitch detection and processing circuit; a second SR flip-flop, whose set input terminal receives the inverted signal of the input signal; a first output end of the first SR trigger is connected to an input end of the first pulse forming submodule, and an output signal of the first pulse forming submodule is inverted and then input to a reset input end of the second SR trigger; and a first output end of the second SR trigger is connected to an input end of the second pulse forming submodule, and an output signal of the second pulse forming submodule is inverted and then input to a reset input end of the first SR trigger.

In one embodiment, a delay circuit for a system on a chip is disclosed, comprising: a delay cell array including a plurality of delay cells; and a glitch detection and processing circuit provided by the various embodiments herein, an output of the glitch detection and processing circuit being connected to the plurality of delay cells in the delay array.

In one embodiment, a system on a chip is disclosed, comprising: a low voltage domain system receiving an enable signal and operating under control of the enable signal to provide a low voltage; delay circuitry provided by various embodiments herein to receive the enable signal and to provide a delayed enable signal; and a high voltage domain system receiving the delayed enable signal and the low voltage and operating under control of the delayed enable signal to provide a high voltage.

In one embodiment, a storage device is disclosed, comprising: a storage unit; and a peripheral circuit configured to include the glitch detection and processing circuit or the delay circuit provided by the various embodiments herein.

By adopting the technical scheme of the embodiment of the disclosure, the glitch detection and processing circuit detects the glitch appearing in the enable signal for the system on chip and correspondingly expands the glitch into the pulse with the preset width, so that all delay units in the delay array can be reliably reset, and the problem caused by that part of the delay units are reset and part of the delay units are not reset due to the variable width of the glitch signal is avoided. Other advantages of embodiments of the present disclosure are also provided, as illustrated in the detailed description below.

Drawings

The drawings that accompany the disclosed embodiments can be briefly described as follows, wherein like or corresponding elements are designated by like or similar reference numerals.

FIG. 1A illustrates a schematic block diagram of a system-on-chip 10 according to one embodiment of the present disclosure.

Fig. 1B illustrates schematic waveform diagrams of an enable signal en and a delayed enable signal en _ d according to one embodiment of the present disclosure.

Fig. 2A shows a schematic block diagram of a delay circuit 110A, according to one embodiment of the present disclosure.

Fig. 2B illustrates schematic waveform diagrams of the enable signal en and the delay enable signals en _ d1 and en _ d2 without glitches in the enable signal en, according to one embodiment of the present disclosure.

Fig. 2C illustrates schematic waveform diagrams of the enable signal en and the delay enable signals en _ d1 and en _ d2 when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Fig. 3A illustrates a schematic block diagram of a delay circuit 110B, according to one embodiment of the present disclosure.

Fig. 3B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure.

Fig. 3C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Fig. 4A illustrates a schematic block diagram of a glitch detection and processing circuit 400, according to one embodiment of the present disclosure.

Fig. 4B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure.

Fig. 4C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Fig. 5A illustrates a schematic block diagram of a glitch detection and processing circuit 500, according to one embodiment of the present disclosure.

Fig. 5B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure.

Fig. 5C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Fig. 6A illustrates a schematic block diagram of a glitch detection and processing circuit 600, according to one embodiment of this disclosure.

Fig. 6B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure.

Fig. 6C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Fig. 7 illustrates a schematic block diagram of a glitch detection and processing circuit 700 according to one embodiment of the present disclosure.

Fig. 8 shows a schematic block diagram of a delay circuit 800 according to one embodiment of the present disclosure.

FIG. 9 illustrates a schematic block diagram of a storage system 900, according to one embodiment of the present disclosure.

Detailed Description

Specific embodiments of the disclosure will be described below, and those skilled in the art will understand that obvious variations of the described embodiments may be used without departing from the scope of the disclosure.

FIG. 1A illustrates a schematic block diagram of a system-on-chip 10 according to one embodiment of the present disclosure. Fig. 1B illustrates schematic waveform diagrams of an enable signal en and a delayed enable signal en _ d according to one embodiment of the present disclosure.

The system-on-chip 10 includes a delay circuit 110, a first voltage domain system 120, and a second voltage domain system 130. First voltage domain system 120 provides a low voltage lv and second voltage domain system 130 provides a high voltage hv for other components of the system-on-chip. First voltage domain system 120 and second voltage domain system 130 each operate under control of an enable signal en. In order to ensure the system operates properly, it is necessary that after the first voltage domain system 120 is started and operates normally, the second voltage domain system 130 is restarted and operates with the low voltage lv provided by the first voltage domain system 120. The delay circuit 110 receives the enable signal en and outputs a delayed enable signal en _ d for controlling the operation of the second voltage domain system 130 after delaying the enable signal en.

As shown in fig. 1B, the delay circuit 110 delays the enable signal en by a certain time and then provides the delayed enable signal en _ d to the second voltage domain system 130. In the embodiment shown in fig. 1B, the enable signals en and en _ d are both active high. Those skilled in the art will appreciate that in other embodiments, the enable signals en and en _ d may be active low.

Fig. 2A shows a schematic block diagram of a delay circuit 110A, according to one embodiment of the present disclosure. Fig. 2B illustrates schematic waveform diagrams of the enable signal en and the delay enable signals en _ d1 and en _ d2 without glitches in the enable signal en, according to one embodiment of the present disclosure. Fig. 2C illustrates schematic waveform diagrams of the enable signal en and the delay enable signals en _ d1 and en _ d2 when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

The delay circuit 110A shown in fig. 2A is an example of the delay circuit 110 shown in fig. 1A. The delay circuit 110A includes a delay array 1110 including a plurality of D flip-flops (DFFs), of which only four D flip-

flops

1111 and 1114 are shown in fig. 2A. The plurality of D flip-flops in delay array 1110 are used to provide different amounts of delay time for enable signal en. For example, the Q output of flip-flop 1113 outputs delayed enable signal en _ d1, and the Q output of flip-flop 1114 outputs delayed enable signal en _ d 2.

In the example shown in fig. 2A, the delayed enable signal en _ d2 is input to an input of an inverter 1101, an output of the inverter 1101 is connected to one input of a three-input nand gate 1102, and the enable signal en and the clock signal clk are input to the other two inputs of the three-input nand gate 1102. The output of the nand gate 1102 is connected to the clock input of the D flip-flop 1103 and to the input of the inverter 1105. The enable signal en is input to the D input (also referred to as the data input) and the reset input of D flip-flop 1103 and the reset inputs of the plurality of D flip-flops in delay array 1110. The Q output of the D flip-flop 1103 (also referred to as the data latch output) and the output of the inverter 1105 are connected to the inputs of the and gate 1104. The output of the and gate 1104 is connected to the clock input of the first D flip-flop 1111 in the delay array 110. Of D flip-flop 1111

(also referred to as the inverted data latch output) is connected to its own D input and to the clock input of the next D flip-flop 1112. The connections of D flip-flop 1112 and the various D flip-flops following it are similar to D flip-flop 1111 as shown in FIG. 2A.

The logic function of the D flip-flop is known in the art and is briefly described below. When the input signal at the reset input terminal is high, the signal at the Q output terminal is equal to the signal at the D input terminal at the rising edge of the input signal at the clock input terminal,

the signal at the output is in anti-phase with the signal at the Q output. When the input signal at the reset input terminal is at a low level, the signal at the Q output terminal is reset to a low level or 0.

Delay circuit 110A, when operating normally, is capable of providing a plurality of delay enable signals having different amounts of delay time, such as the illustrated delay enable signals en _ d1 and en _ d 2. Fig. 2B illustrates waveform diagrams of the enable signal en and the delay enable signals en _ d1 and en _ d 2. In the particular implementation shown in fig. 1, the delay enable signal may be selected as desired as the delay enable signal en _ d output by the delay circuit 110. For example, en _ d1 may be used as the delay enable signal en _ d output by the delay circuit 110. Thus, the delay array 1110 can flexibly provide the delay enable signal according to the requirements of the signal delay amount in a specific application.

When a glitch occurs in the enable signal en, for example, due to a CDC problem, the delay circuit 110A may have a problem. As shown in fig. 2C, a glitch occurs in the enable signal en, and the glitch is usually an extremely short pulse whose pulse width is variable. When a glitch occurs, the level of the enable signal en changes from high to low, causing the D flip-flops in the corresponding D flip-flop array 1110 to be reset. However, since the low level duration of the glitch is short, the glitch may be filtered out by the wiring resistance and the capacitance, so that there may occur a case where: during the en signal passing along the line to the reset input of each D flip-flop of delay array 1110, a glitch in the en signal may be filtered out at a certain point, resulting in one portion of D flip-flops in delay array 1110 receiving a glitch and another portion of D flip-flops not receiving a glitch, such that a glitch in the en signal resets only a portion of D flip-flops in delay array 1110 and does not reset another portion of D flip-flops in delay array 1110. For example, a low level of a glitch in the enable signal en resets the D flip-flop 1113 so that the output signal en _ D1 at its Q output changes from 1 to 0; while the enable signal en to the reset input of D flip-flop 1114 already has no glitch and therefore D flip-flop 1114 is not reset and its output signal en _ D2 at the Q output remains 1. Since en _ D2 remains at 1, the output of AND gate 1104 remains at 0, i.e., the clock input signal of delay array 1110 remains at 0, so the delay enable signal en _ D output by D flip-flop 1113 remains at 0 clocked, as shown in FIG. 2C.

Since the delay enable signal en _ d1 may be configured to be the output delay enable signal en _ d of the delay circuit 110 in certain applications, when this occurs, see fig. 1A and 2C, the delay enable signal en _ d provided to the second voltage domain system 130 causes the second voltage domain system 130 to be disabled due to the inability to toggle from 0 to 1 again, resulting in a circuit failure. Furthermore, it will be appreciated that if a glitch occurs which resets only a portion of the delay cells in the delay array, there is also the possibility of an unknown potential risk due to such uncertainty in the circuit, in order to desirably eliminate such unknown risk as much as possible at the circuit design stage.

Fig. 3A illustrates a schematic block diagram of a delay circuit 110B, according to one embodiment of the present disclosure. Fig. 3B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure. Fig. 3C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

The delay circuit 110B may be used as the delay circuit 110 shown in fig. 1A. The delay circuit 110B includes a glitch detection and processing circuit 300 in addition to the circuit portion of the delay circuit 110A shown in fig. 2A.

In the embodiment shown in fig. 3A, glitch detection and processing circuit 300 receives enable signal en and outputs a processed glitch extension enable signal en _ p and provides glitch extension enable signal en _ p to the reset inputs of the various D flip-flops in delay array 1110.

The glitch detection and processing circuit 300 includes a first SR flip-flop 3101 and a second SR flip-flop 3201. SR flip-flops, also referred to as set (S) reset (R) flip-flops, have logic functions known in the art and are briefly described below. When the input signal of the S input end is high level '1' and the input signal of the R input end is low level '0', the signal of the Q output endThe number is high level "1",

the signal at the output terminal is low level "0"; when S is 0 and R is 1, Q is 0,

is 1; when S and R are both 0, Q and

the original state is maintained.

The S input of the first SR flip-flop 3101 is connected to an input of the glitch detection and processing circuit 300, receiving the enable signal en. The inverter 3205 is connected to an input of the glitch detection and processing circuit 300, receives the enable signal en, and provides an inverted enable signal en _ b to the S input of the second SR flip-flop 3201. In fig. 3A, an input signal at the S input terminal of the first SR flip-flop 3101 is denoted by a symbol S1, and an input signal at the S input terminal of the second SR flip-flop 3201 is denoted by a symbol S2, i.e., S1 is the enable signal en and S2 is the inverted enable signal en _ b.

As shown in fig. 3B, in the normal operating state when there is no glitch in the enable signal en, s1 is high and s2 is low, which are respectively indicated as 1 and 0 in fig. 3B. The output signal Q1 at the Q output of the first SR flip-flop 3101 is 1 and the output signal Q2 at the Q output of the second SR flip-flop 3201 is 0.

The Q output of the first SR flip-flop 3101 is connected to the input of the rising edge delay 3102. Rising edge delay 3102 is used to delay the rising edge that occurs in its input signal by a configured amount of time, for example, as shown in fig. 3A, rising edge delay 3102 may delay the rising edge in signal q1 by 20ns and output delayed signal q1 rd. In one implementation, the rising edge delay 3102 may be implemented by an RC delay circuit, and by setting the appropriate values of the resistance R and the capacitance C, the amount of time that the rising edge delay 3102 can delay may be configured. The advantage of implementing the rising edge delay 3102 by an RC delay circuit is that the circuit structure is simple, the RC delay circuit itself being a circuit known in the art, the specific structure of which is not described in detail.

The Q output of the first SR flip-flop 3101 is connected to the input of an inverter 3103, and the output of the inverter 3103 and the output of the rising edge delay 3102 are connected to the input of an or gate 3104. As shown in fig. 3B, when the signal q1 is 1, the output signal q1_ rd of the rising edge delay is also 1, the output signal q1_ B of the inverter 3103 is 0, and the output signal q1_ p of the or gate 3104 is 1. The control signal active _ n remains 0, and thus the output signal of the inverter 3305 remains 1. The output of the or gate 3104 and the output of the inverter 3305 are connected to a nand gate 3302. Because the output signal of inverter 3305 remains 1, the output of nand gate 3302 is the inverse of the input signal q1_ p, denoted as q1_ pb, when the signal q1_ pb is 0.

The Q output of the second SR flip-flop 3201 is connected to an input of a rising edge delay 3202, and the rising edge delay 3202 has the same configuration as the rising edge delay 3102. As shown in fig. 3A, the rising edge delayer 3102 may delay the rising edge in signal q2 by 20ns and output a delayed signal q2_ rd.

The Q output of the second SR flip-flop 3201 is connected to an input of an inverter 3203, and an output of the inverter 3203 and an output of the rising edge delay 3202 are connected to an input of an or gate 3204. As shown in fig. 3B, when the signal q2 is 0, the signal q2_ rd is also 0, the output signal q2_ B of the inverter 3203 is 1, and the output signal q2_ p of the or gate 3204 is 1. The control signal active _ n remains 0, and thus the output signal of the inverter 3305 remains 1. The output of the or gate 3204 and the output of the inverter 3305 are connected to the nand gate 3301. Because the output signal of inverter 3305 remains 1, the output of nand gate 3301 is the inverse of the input signal q2_ p, denoted as q2_ pb, when the signal q2_ pb is 0.

Glitch filtering module 3401 in glitch detection and processing circuit 300 receives the enable signal and filters the glitches in enable signal en to output a clean enable signal en _ f without glitches. In one implementation, the glitch filtering module 3401 can include a plurality of buffers, which can be connected in series, and the wiring capacitance and resistance included in the plurality of buffers are sufficient to filter out glitches in the enable signal en, and the output clean enable signal en _ f is kept to be 1.

The output of the glitch filter module 3401 and the output of the nand gate 3302 are connected to the input of the nor gate 3303. Since the clean enable signal en _ f remains at 1, the output of nor gate 3303 remains at 0. The output of the nor gate 3303 and the output of the nand gate 3301 are connected to the inputs of the nor gate 3304. Since the output of the nor gate 3303 remains 0, the output signal en _ p of the nor gate 3304 depends on the other input signal q2_ pb, in particular the inverse of q2_ pb, so the output signal en _ p is 1. As shown in fig. 3B, in a state where there is no glitch in the enable signal en, which is a reset signal of the reset input terminal of each D flip-flop in the delay array 1110, the output signal en _ p of the glitch detecting and processing block 300 is maintained at 1.

Referring to fig. 3A and 3C, when a glitch occurs in the enable signal en at time t1, the signal s1 changes from 1 to 0, and the signal s2 changes from 0 to 1. The R input of the second SR flip-flop is connected to the output of the nand gate 3302, and the output signal q1_ pb of the nand gate 3302 serves as the R input signal of the second SR flip-flop 3201. At this time, the S input signal of the second SR flip-flop is 1, the R input signal is 0 (see the signal Q1_ pb in fig. 3B), and thus the Q output signal Q2 of the second SR flip-flop changes from 0 to 1, thereby detecting that a glitch occurs in the enable signal en.

When the signal q2 changes from 0 to 1, the output signal q2_ b of the inverter 3203 changes from 1 to 0, and the output signal q2_ rd of the rising edge delay 3202 remains 0 for 20ns and changes from 0 to 1 at time t2 delayed by 20 ns. Accordingly, the output signal q2_ p of the or gate 3204 changes from 1 to 0 and remains 0 for a time of 20ns from t1 to t2, thereby forming a 20ns pulse signal corresponding to a glitch. Accordingly, the output signal q2_ pb of the nand gate 3301 changes from 0 to 1. Accordingly, the output signal en _ p of the nand gate 3304 changes from 1 to 0.

The output of the nand gate 3301 is connected to the R input of the first SR flip-flop, so during the glitch duration of the signal S1, the S input signal of the first SR flip-flop is 0, the R input signal is 1, the Q output signal Q1 changes from 1 to 0, and remains 0 under the control of the reset signal Q2_ pb.

When the signal q1 changes from 1 to 0, the output signal q1_ b of the inverter 3103 changes from 0 to 1, and the output signal q1_ rd of the rising edge delay 3102 changes from 1 to 0. Accordingly, the output signal q1_ p of the or gate 3104 remains 1. Accordingly, the output signal q2_ pb of the nand gate 3302 remains 0. During the time that the signal Q2_ pb remains at 0, the Q output signal Q2 of the second SR flip-flop 3201 remains at 1.

At time t2, the output signal q2_ rd of the rising edge delay 3202 changes from 0 to 1. Accordingly, the output signal q2_ p of the or gate 3204 changes from 0 to 1. Accordingly, the output signal q2_ pb of the nand gate 3301 changes from 1 to 0. At this time, the S input signal S1 of the first SR flip-flop is 1, and the R input signal is 0, so the Q output signal Q1 changes from 0 to 1.

When the signal q1 changes from 0 to 1 at time t2, the output signal q1_ b of the inverter 3103 changes from 1 to 0, and the output signal q1_ rd of the rising edge delay 3102 remains 0 for 20ns and changes from 0 to 1 after a delay of 20 ns. Accordingly, the output signal q1_ p of the or gate 3104 changes from 1 to 0 and remains 0 for 20ns after t 2. Accordingly, the output signal q1_ pb of the nand gate 3302 changes from 0 to 1. At this time, the S input signal S2 of the second SR flip-flop is 0, and the R input signal Q1_ pb is 1, so its Q output signal Q2 changes from 1 to 0.

When the signal q2 changes from 1 to 0, the output signal q2_ b of the inverter 3203 changes from 0 to 1, and the output signal q2_ rd of the rising edge delay 3202 changes from 1 to 0. Accordingly, the output signal q2_ p of the or gate 3204 remains 1. Accordingly, the output signal q2_ pb of the nand gate 3301 remains 0. Accordingly, the output signal en _ p of the nand gate 3304 remains at 1. Thus, glitch detection and processing circuit 300 provides enable signal en _ p having a pulse width of 20ns, which is not referred to as glitch extension enable signal en _ p.

At a time t 320 ns after t2, the output signal q1_ rd of the rising edge delay 3102 changes from 0 to 1. Accordingly, the output signal q1_ p of the or gate 3104 changes from 0 to 1. Accordingly, the output signal q1_ pb of the nand gate 3302 changes from 1 to 0. After time t3, the waveforms of all signals are the same as those shown in fig. 3B until the next occurrence of a glitch.

Through the above-described procedure, the glitch detection and processing circuit 300 can detect a glitch occurring in the enable signal en and generate the glitch extension enable signal en _ p of a pulse having a pulse width of 20ns in response to the occurrence of the glitch. It will be appreciated that in the embodiment shown in fig. 3A-3C, configuring the extended pulse width to be 20ns is exemplary, and that in particular implementations, the extended pulse width may be configured to other values.

As shown in fig. 3A, an output terminal of the glitch detection and processing circuit 300 is connected to a reset input terminal of each D flip-flop in the delay array 1110, and when a glitch occurs in the enable signal en, a glitch extension signal en _ p having a pulse width of 20ns is input to the reset input terminal of each D flip-flop in the delay array 1110. A pulse width of 20ns is sufficient to reset all D flip-flops in delay array 1110, thus avoiding the problems described above in connection with fig. 2 that a glitch may only reset a portion of the D flip-flops.

Those skilled in the art will appreciate that while a specific circuit diagram of delay circuit 110B and its glitch detection and processing circuit 300 is shown in fig. 3A, embodiments of the present disclosure are not limited to the specific circuit shown in fig. 3A and the specific components employed therein, and other circuits and components that perform the same or corresponding functions may be employed in other embodiments.

Fig. 4A illustrates a schematic block diagram of a glitch detection and processing circuit 400, according to one embodiment of the present disclosure. Fig. 4B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure. Fig. 4C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure. Some of the signals in fig. 4B and 4C correspond to some of the signals in fig. 3B and 3C, and therefore the details of all the signals in the figures are not described in detail.

Glitch detection and processing circuit 400 can be used as a glitch detection and processing circuit in

delay circuits

110 and 110B. As shown in fig. 4A, glitch detection and processing circuit 400 includes a glitch detection module 410, a pulse formation module 420, a logic combination module 430, and a glitch filtering module 440.

Glitch detection module 410 is used to detect a glitch in the input signal of glitch detection and processing circuit 400, the glitch having a first pulse width. The first pulse width of the different spikes is variable. In the embodiment shown in fig. 4A, the input signal of the glitch detection and processing circuit 400 is an enable signal en for the system on chip, which is input to the input of the glitch detection module 410 via the inverter 4101. Although the inverter 4101 is shown as a component outside the glitch detection module 410 in fig. 4A for inverting the enable signal en and supplying it to the glitch detection module 410, the inverter 4101 may also be understood as a component included in the glitch detection module 410. In one implementation, glitch detection module 410 includes an SR flip-flop, such as SR flip-flop 3201 described in conjunction with fig. 3A.

The glitch detection module 410 flips its output signal in response to a glitch occurring in the input signal en, thereby detecting the occurrence of the glitch. In the example shown in fig. 4C, a glitch occurs in the input signal en at time t1, and accordingly the input signal s2 of the glitch detection block 410 changes from 0 to 1 and the output signal q2 thereof changes from 0 to 1, thereby detecting the occurrence of the glitch. It is to be appreciated that although the glitch detection module 410 is depicted in fig. 3A and 4A by way of example as an SR flip-flop, the glitch detection module 410 may be implemented using other components or modules capable of toggling its output signal in response to the occurrence of a glitch in the input signal. For ease of description, in the description of the embodiments herein, glitch detection module 410 flips its output signal from low to high, i.e., from 0 to 1, in response to the occurrence of a glitch in the input signal. Those skilled in the art will appreciate that in a particular implementation, depending on whether the circuit design in whole or in part is based on rising or falling edges, glitch detection module 410 may also flip its output signal from 1 to 0 in response to the occurrence of a glitch in the input signal, and accordingly the design of subsequent processing circuits may need to be adjusted in response to the output signal changing from 1 to 0.

The pulse forming module 420 generates a pulse forming signal q2_ p having pulses of a second preconfigured pulse width in response to the glitch detection module 410 detecting a glitch in the input signal en, wherein the pulses in the pulse forming signal q2_ p correspond to the detected glitch in the input signal, the second pulse width being larger than the first pulse width. In some implementations, the second pulse width can be configured to be much larger than the first pulse width. For example, the second pulse width may be configured to be 20ns or other suitable value, while in general the width of the glitch may be on the order of a fraction of a nanosecond or on the order of a few nanoseconds.

In one implementation, the pulse forming module 420 generates the pulse forming signal q2_ p having pulses of the second pulse width in response to an inversion of the output signal q2 of the glitch detection module 410, e.g., a change in the output signal q2 from 0 to 1. The pulse forming signal q2_ p ultimately determines the pulse width of the glitch extension output signal en _ p of the glitch detection and processing circuit 400.

In the implementation shown in fig. 4A, pulse forming module 420 includes an SR flip-flop 4201, a first pulse forming sub-module 4202, and a second pulse forming sub-module 4203. The Q output of the SR flip-flop 410 is connected to an input of the pulse forming sub-module 4203, so that a rising edge of the output signal Q2 of the SR flip-flop 410 triggers the pulse forming sub-module 4203 to form a pulse forming signal Q2_ p having a pulse of the second pulse width, as shown in waveform diagram 4C. In one particular implementation, the pulse forming sub-module 4203 may be implemented by the

particular components

3202, 3203, and 3204 shown in fig. 3A, i.e., the pulse forming sub-module 4203 may include a rising edge delay 3202, an inverter 3203, and an or gate 3204, which is advantageous in that the pulse forming sub-module 4203 is simple in structure. Those skilled in the art will appreciate that pulse forming sub-modules 4203 and 4202 may be implemented using other components or modules capable of generating a pulse signal having a particular width in response to trigger signal q 2.

As shown in fig. 4C, the output signal q2_ p of the pulse forming sub-module 4203 is used to control the reset input operation of the SR flip-flop 4201. Specifically, the output signal Q2_ p is inverted by the nand gate 4302 to obtain an inverted output signal Q2_ pb having a high level pulse of the second pulse width, and the high level pulse Q2_ pb is input to the R input terminal of the SR flip-flop to control the Q output signal Q1 thereof to be 0 for the duration of the corresponding second pulse width. The output signal q1_ p of the pulse forming submodule 4202 is used to control the reset input operation of the SR flip-flop 410. Specifically, the output signal Q1_ p is inverted by the nand gate 4301 to obtain an inverted output signal Q1_ pb having a high-level pulse of a second pulse width during the time t2 to t3, and the high-level pulse Q2_ pb is input to the R input of the SR flip-flop 410 to control the Q output signal Q2 thereof to return to 0 at the time t 2.

In the embodiment shown in fig. 4A, the logic combination module 430 includes a first nand gate 4301 for flipping the output signal q1_ p of the pulse forming sub-module 4202, and a second nand gate 4302 for flipping the output signal q2_ p of the pulse forming sub-module 4203. The logic combination module 430 further includes nor

gates

4303 and 4304, and finally generates a glitch extension signal en _ p based on the pulse forming signal q2_ p by logic combination as an output signal of the glitch detection and processing circuit 400. As shown in fig. 4A, in one particular implementation, the combinational logic circuit 430 may be implemented by

logic components

4301, 4302, 4303, 4304 corresponding to the

particular components

3301, 3302, 3303, 3304 shown in fig. 3A, but those skilled in the art will appreciate that the combinational logic circuit 430 may also be implemented by other particular circuits for generating a corresponding glitch extension signal en _ p in response to the pulse forming signal q2_ p.

Although

nand gates

4301 and 4302 are shown as part of the combinational logic block 430 in the embodiment shown in fig. 4A, those skilled in the art will understand that

nand gates

4301 and 4302 may also be part of the pulse forming block 420, where the output signal q1_ pb of the nand gate 4301 is used to control the set operation of the SR flip-flop 410 and the output signal q2_ pb of the nand gate 4302 is used to control the set operation of the SR flip-flop 4201.

The spur filtering module 440 is configured to filter out a spur in the input signal en to output a clean signal en _ f without a spur. Combinational logic module 430 generates a glitch extension signal en _ p based on pulse forming signal q2_ p and clean signal en _ f. As shown in fig. 4A and 4C, the clean signal en _ f is always 1, so it determines that the output of nor gate 4303 is 0 and the corresponding input of nor gate 4304 is 0; since the active _ n signal is always 0, the pulse forming signal q2_ p determines the output q2_ pb of the nand gate 4302 and thus the output en _ p of the nor gate 4304. As shown in fig. 4A, in one particular implementation, glitch filtering module 440 may be implemented by the particular component 3401 shown in fig. 3A, but those skilled in the art will appreciate that glitch filtering module 440 may be implemented using other particular circuitry for filtering glitches in a signal.

Through the above-described process described in connection with fig. 4A-4C, the glitch detection and processing circuit is able to detect a glitch occurring in the enable signal en and generate the glitch extension enable signal en _ p of a pulse having a second pulse width of, for example, 20ns in response to the occurrence of the glitch.

Fig. 5A illustrates a schematic block diagram of a glitch detection and processing circuit 500, according to one embodiment of the present disclosure. Fig. 5B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure. Fig. 5C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure. Some of the signals in fig. 5A and 5C correspond to some of the signals in fig. 3B and 3C, and fig. 4B and 4C, and therefore the details of all the signals in the figures are not described in detail.

Glitch detection and processing circuit 500 may be used as a glitch detection and processing circuit in

delay circuits

110 and 110B. As shown in fig. 5A, glitch detection and processing circuit 500 includes a glitch detection module 510, a glitch propagation module 520, and a glitch filtering module 530.

The glitch detection module 510 is configured to detect a glitch in the input signal en, wherein the glitch has a variable first pulse width. The glitch extension module 520 is configured to generate a glitch extension signal en _ p having pulses of a second pulse width that is pre-configured in response to the glitch detection module 510 detecting a glitch, wherein the pulses in the glitch extension signal en _ p correspond to the glitch in the signal en and the second pulse width is greater than the first pulse width.

The glitch extension module 520 includes a pulse forming module 5210 and a logic combining module 5220. Implementations of the pulse forming module 5210 and the logical combination module 3220 may correspond to the pulse forming module 420 and the logical combination module 430 shown in fig. 4A, respectively, and thus are not described in detail. An implementation of the spike filtering module 530 may correspond to the spike filtering module 440 shown in fig. 4A and thus will not be described in detail.

Fig. 6A illustrates a schematic block diagram of a glitch detection and processing circuit 600, according to one embodiment of this disclosure. Fig. 6B shows a schematic waveform diagram of individual signals without glitches in the enable signal en, according to one embodiment of the present disclosure. Fig. 6C shows a schematic waveform diagram of various signals when a glitch occurs in the enable signal en, according to one embodiment of the present disclosure.

Glitch detection and processing circuit 600 can be used as a glitch detection and processing circuit in

delay circuits

110 and 110B. As shown in fig. 6A, glitch detection and processing circuit 600 includes a glitch detection module 610, a glitch extension module 620. The glitch detection module 610 is configured to detect a glitch in the input signal en, wherein the glitch has a variable first pulse width. The glitch extension module 620 is configured to generate a glitch extension signal en _ p having pulses of a second preconfigured pulse width in response to the glitch detection module 610 detecting a glitch, wherein the pulses in the glitch extension signal en _ p correspond to the glitch in the signal en, and the second pulse width is greater than the first pulse width.

Unlike the glitch detection and processing circuitry shown in fig. 3A, 4A, 5A, the glitch detection and processing circuitry 600 does not include a glitch filtering module, in which the output of the inverter 6225 is connected to the input of the xor 6223 in place of the output of the glitch filtering module.

The spur spreading module 620 includes a pulse forming module 6210 and a logic combining module 6220. Implementations of the pulse forming module 6210 and the logic combining module 6220 may correspond to the pulse forming module 420 and the logic combining module 430, respectively, shown in fig. 4A, and thus will not be described in detail.

Glitch detection and processing circuitry provided in various embodiments of the present disclosure is described above in connection with fig. 3A, 4A, 5A, and 6A. An embodiment of the present disclosure provides a glitch detection and processing circuit, including: a first SR flip-flop, whose set input terminal receives the input signal of the glitch detection and processing circuit; a second SR flip-flop, whose set input end receives the inverted signal of the input signal; a first output end of the first SR trigger is connected to an input end of the first pulse forming submodule, and an output signal of the first pulse forming submodule is input to a reset input end of the second SR trigger after being inverted; and a first output end of the second SR trigger is connected to an input end of the second pulse forming submodule, and an output signal of the second pulse forming submodule is inverted and then is input to a reset input end of the first SR trigger.

In one embodiment, the first pulse forming submodule includes a first one-sided delay for delaying a rising edge or a falling edge in its input signal by a predetermined time, a first inverter and a first or gate, a first output terminal of the first SR flip-flop is connected to an input terminal of the first inverter and an input terminal of the first one-sided delay, an output terminal of the first inverter and an output terminal of the first one-sided delay are connected to an input terminal of the first or gate. The second pulse forming submodule includes a second single-sided delay for delaying a rising edge or a falling edge in an input signal thereof by the predetermined time, a second inverter, and a second or gate, a first output terminal of the second SR flip-flop is connected to an input terminal of the second inverter and an input terminal of the second single-sided delay, and an output terminal of the second inverter and an output terminal of the second single-sided delay are connected to an input terminal of the second or gate.

In one embodiment, the glitch detection and processing circuit further comprises: the output end of the first or gate is connected to the input end of the first inversion unit, and the output end of the first inversion unit is connected to the reset input end of the second SR flip-flop; and the output end of the second OR gate is connected to the input end of the second inversion unit, and the output end of the second inversion unit is connected to the reset input end of the first SR flip-flop.

In one embodiment, the first inversion unit includes a first nand gate, a first input of the first nand gate is connected to the output of the first or gate, and a second input of the first nand gate receives a high signal. The second inversion unit comprises a second NAND gate, a first input end of the second NAND gate is connected to the output end of the second OR gate, and a second input end of the second NAND gate receives a high-level signal.

In one embodiment, the glitch detection and processing circuit further comprises: the burr filtering module receives the input signal and filters burrs in the input signal so as to output a clean signal without the burrs at the output end of the burr filtering module; a first NOR gate, wherein a first input end of the first NOR gate is connected to the output end of the burr filtering module, and a second input end of the first NOR gate is connected to the output end of the first NAND gate; a second NOR gate, a first input of the second NOR gate being connected to the output of the first NOR gate, a second input of the second NOR gate being connected to the output of the second NAND gate. The output of the second nor gate serves as the output of the glitch detection and processing circuit.

Glitch detection and processing circuit 700 may be used as the glitch detection and processing circuit in

delay circuits

110 and 110B. In one embodiment, as shown in fig. 7, glitch detection and processing circuit 700 includes a glitch detection module 710 for detecting a glitch occurring in an input signal of glitch detection and processing circuit 700, wherein the glitch has a first pulse width; a glitch extension module 720 for generating a glitch extension signal having pulses of a second pulse width that is pre-configured in response to the glitch detection module 710 detecting a glitch in the input signal, wherein the pulses in the glitch extension signal correspond to the glitch in the input signal and the second pulse width is greater than the first pulse width.

In one embodiment, as shown in fig. 7, glitch extension module 720 includes a pulse forming module 7210 for generating a pulse formed signal having a pulse of the second pulse width in response to glitch detection module 710 detecting the glitch; a logic combination module 7220 for generating the spur-spread signal based on the pulse-forming signal.

In one embodiment, as shown in fig. 7, the glitch detection and processing circuit 700 further includes a glitch filtering module 730 for filtering out glitches in the input signal to output a clean signal without glitches. Logic combination module 7220 generates the spur spread signal based on the pulse forming signal and the clean signal.

In one embodiment, glitch detection module 710 toggles its first output signal in response to a glitch occurring in the input signal. The pulse forming module 7210 generates the pulse forming signal having pulses of the second pulse width in response to the flipped first output signal of the glitch detection module 710.

In one embodiment, pulse forming module 7210 generates a control signal for glitch detection module 710 in response to the flipped first output signal of glitch detection module 710 to control glitch detection module 710 to keep outputting the flipped first output signal during a time corresponding to the second pulse width.

In one embodiment, the control signal for glitch detection module 710 also controls glitch detection module 710 to again flip its first output signal at the end of the time period corresponding to the second pulse width.

In one embodiment, the pulse forming module 7210 includes a first SR flip-flop, a first pulse forming sub-module, and a second pulse forming sub-module. The glitch detection module 710 includes a second SR flip-flop. The first output terminal of the first SR flip-flop is connected to the input terminal of the first pulse forming submodule, the first output terminal of the second SR flip-flop is connected to the input terminal of the second pulse forming submodule, the output signal of the second pulse forming submodule is used to control the reset operation of the first SR flip-flop, the output signal of the first pulse forming submodule is used to control the reset operation of the second SR flip-flop, and the input signal of the glitch detection and processing circuit 700 is used to control the set operation of the second SR flip-flop and the first SR flip-flop.

In one embodiment, the output signal of the second pulse forming sub-module is inverted and then input to the reset input terminal of the first SR flip-flop to control the reset operation of the first SR flip-flop, the output signal of the first pulse forming sub-module is inverted and then input to the reset input terminal of the second SR flip-flop to control the reset operation of the second SR flip-flop, and the input signal of the glitch detection and processing circuit 700 is input to the S input terminal of the first SR flip-flop to control the set operation of the first SR flip-flop, and the input signal is inverted and then input to the S input terminal of the second SR flip-flop to control the set operation of the second SR flip-flop.

In one embodiment, the first pulse forming submodule includes a first one-sided delay for delaying a rising edge or a falling edge in an input signal thereof by a predetermined time corresponding to the second pulse width, a first inverter and a first or gate, a first output terminal of the first SR flip-flop is connected to an input terminal of the first inverter and an input terminal of the first one-sided delay, and an output terminal of the first inverter and an output terminal of the first one-sided delay are connected to an input terminal of the first or gate. The second pulse forming submodule includes a second one-sided delay for delaying a rising edge or a falling edge in an input signal thereof by a predetermined time corresponding to a second pulse width, a second inverter and a second or gate, a first output terminal of the second SR flip-flop is connected to an input terminal of the second inverter and an input terminal of the second one-sided delay, and an output terminal of the second inverter and an output terminal of the second one-sided delay are connected to an input terminal of the second or gate. In the above embodiments described in connection with fig. 3A-6C, implementations of rising edge delays are described, such as 20ns rising

edge delays

3102 and 3202. It will be appreciated by those skilled in the art that when the design of the circuit is triggered by a falling edge, a falling edge delay may be used accordingly instead of the rising edge delay described in the embodiments. The rising edge delay and the falling edge delay may be collectively referred to as a one-sided delay.

In one embodiment, logic combination module 7220 includes a first inversion unit and a second inversion unit. The first inverting unit is used for inverting the output signal of the first OR gate and providing the inverted signal to the reset input end of the second SR flip-flop. The second inverting unit is used for inverting the output signal of the second OR gate and providing the inverted signal to the reset input end of the first SR flip-flop.

In one embodiment, logic combining module 7220 includes a first nor gate having a first input connected to the output of glitch filter module 730, glitch filter module 730 for filtering glitches in the input signal to output a clean signal without glitches, and a second nor gate having a second input connected to the output of the first nand gate. The first input of the second nor gate is connected to the output of the first nor gate, the second input of the second nor gate is connected to the output of the second nand gate, and the second nor gate outputs a glitch-spread signal. In one embodiment, spur filtering module 730 includes a plurality of buffers.

In one embodiment, glitch detection and processing circuit 700 further includes a third inverter, wherein the set input of the first SR flip-flop receives the input signal of glitch detection and processing circuit 700, the third inverter receiving the input signal and providing an inverted input signal to the set input of the second SR flip-flop. In one embodiment, the input signal to glitch detection and processing circuit 700 is an enable signal for a system-on-chip.

FIG. 8 illustrates a delay circuit for a system on a chip according to one embodiment of the present disclosure.

Delay circuit 800 includes a delay cell array 810 that includes a plurality of delay cells. Delay circuit 800 also includes glitch detection and processing circuit 820 in the various embodiments described in this disclosure in connection with fig. 3A-8, with the output of glitch detection and processing circuit 820 connected to a plurality of delay cells in delay array 810.

In one embodiment, the plurality of delay cells of delay array 810 includes a plurality of D flip-flops, wherein the output of glitch detection and processing circuit 820 is connected to the reset input of the plurality of D flip-flops in delay array 810.

In one embodiment, the delay circuit 800 further comprises: a first inverter that receives a first output signal from the delay array 810; a first input end of the NAND gate receives an enable signal, a second input end of the NAND gate receives an output signal of the first inverter, and a third input end of the NAND gate receives a clock signal; the data input end of the first D flip-flop receives the enabling signal, the clock input end of the first D flip-flop receives the output signal of the NAND gate, and the reset input end of the first inverter receives the enabling signal; the input end of the second inverter receives the output signal of the NAND gate; and the first input end of the AND gate receives the first output signal of the first D flip-flop, the second input end of the AND gate receives the output signal of the second inverter, and the output end of the AND gate is connected to the delay array.

In one embodiment, the plurality of D flip-flops in the delay array 810 are connected in series, wherein the second output of the previous D flip-flop is connected to its own D input and the clock input of the next D flip-flop, and the output of the and gate is connected to the clock input of the first D flip-flop in the delay array 810.

In one embodiment, the present disclosure also provides a system-on-chip, such as the system-on-chip shown in fig. 1A, comprising: a low voltage domain system receiving an enable signal and operating under control of the enable signal to provide a low voltage; a delay circuit in various embodiments described in this disclosure in connection with fig. 1A-7 for receiving the enable signal and providing a delayed enable signal; and a high voltage domain system receiving the delayed enable signal and the low voltage and operating under control of the delayed enable signal to provide a high voltage.

FIG. 9 illustrates a storage system 900 according to one embodiment of the present disclosure.

Memory system 900 may also be referred to as memory 900, including peripheral circuits 910 and memory unit 920. In the embodiment shown in FIG. 9, peripheral circuit 910 includes a power supply system that includes first voltage domain system 120, second voltage domain system 130, and delay circuit 110.

In one embodiment, the power system outputs the voltage hv to the memory unit 920 for performing an operation of reading and writing the memory unit 920 through the first voltage domain system 110, the second voltage domain system 120 and the delay circuit 130 for performing a proper timing control. Those skilled in the art will appreciate that the embodiment illustrated in FIG. 9 shows only the components relevant to the embodiments of the present disclosure, and that the memory system 900 or peripheral circuitry 910 may include additional components.

In one embodiment of the present disclosure, a memory device 900 is disclosed, comprising: a memory unit 920 and a peripheral circuit 910, the peripheral circuit 910 being configured to include a glitch detection and processing circuit provided in various embodiments herein or a delay circuit provided in various embodiments herein.

The detailed description set forth above in connection with the appended drawings describes exemplary embodiments but does not represent all embodiments that may be practiced or fall within the scope of the claims. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A burr detection and processing circuit, comprising:

a glitch detection module for detecting a glitch occurring in an input signal of the glitch detection and processing circuit, wherein the glitch has a first pulse width;

a glitch extension module to generate a glitch extension signal having pulses of a preconfigured second pulse width in response to the glitch detection module detecting the glitch in the input signal, wherein the pulses in the glitch extension signal correspond to the glitch in the input signal, the second pulse width being greater than the first pulse width.

2. The glitch detection and processing circuit of claim 1 in which said glitch extension module comprises:

a pulse forming module for generating a pulse forming signal having a pulse of the second pulse width in response to the glitch detection module detecting the glitch; and

a logic combination module to generate the spur spread signal based on the pulse forming signal.

3. The glitch detection and processing circuit of claim 2 further including:

the burr filtering module is used for filtering burrs in the input signal so as to output a clean signal without the burrs;

wherein the logic combining module generates the spur spread signal based on the pulse forming signal and the clean signal.

4. The glitch detection and processing circuit of claim 2 in which,

the burr detection module is used for responding to the burrs appearing in the input signal and overturning a first output signal of the burr detection module;

the pulse forming module generates the pulse formed signal having pulses of the second pulse width in response to the flipped first output signal of the glitch detection module.

5. The glitch detection and processing circuit of claim 4 in which,

the pulse forming module generates a control signal for the glitch detection module in response to the flipped first output signal of the glitch detection module to control the glitch detection module to keep outputting the flipped first output signal during a time corresponding to the second pulse width.

6. The glitch detection and processing circuit of claim 4 in which,

the control signal for the glitch detection module also controls the glitch detection module to again flip its first output signal at the end of the time period corresponding to the second pulse width.

7. The glitch detection and processing circuit of claim 2 or 4 in which,

the pulse forming module comprises a first SR trigger, a first pulse forming submodule and a second pulse forming submodule; and

the glitch detection module comprises a second SR trigger;

the first output end of the first SR flip-flop is connected to the input end of the first pulse forming submodule, the first output end of the second SR flip-flop is connected to the input end of the second pulse forming submodule, an output signal of the second pulse forming submodule is used for controlling the reset operation of the first SR flip-flop, an output signal of the first pulse forming submodule is used for controlling the reset operation of the second SR flip-flop, and the input signal is used for controlling the set operation of the second SR flip-flop and the first SR flip-flop.

8. The glitch detection and processing circuit of claim 7 in which,

the output signal of the second pulse forming submodule is inverted and then input to the reset input end of the first SR flip-flop so as to control the reset operation of the first SR flip-flop, the output signal of the first pulse forming submodule is inverted and then input to the reset input end of the second SR flip-flop so as to control the reset operation of the second SR flip-flop, the input signal is input to the S input end of the first SR flip-flop so as to control the set operation of the first SR flip-flop, and the input signal is inverted and then input to the S input end of the second SR flip-flop so as to control the set operation of the second SR flip-flop.

9. The glitch detection and processing circuit of claim 7 in which,

the first pulse forming submodule comprises a first one-sided delayer, a first inverter and a first OR gate, wherein the first one-sided delayer is used for delaying the rising edge or the falling edge in the input signal of the first one-sided delayer by a preset time corresponding to the second pulse width, the first output end of the first SR trigger is connected to the input end of the first inverter and the input end of the first one-sided delayer, and the output end of the first inverter and the output end of the first one-sided delayer are connected to the input end of the first OR gate;

the second pulse forming submodule includes a second one-sided delay for delaying a rising edge or a falling edge in an input signal thereof by a predetermined time corresponding to the second pulse width, a second inverter, and a second or gate, a first output terminal of the second SR flip-flop is connected to an input terminal of the second inverter and an input terminal of the second one-sided delay, and an output terminal of the second inverter and an output terminal of the second one-sided delay are connected to an input terminal of the second or gate.

10. The glitch detection and processing circuit of claim 9 in which,

the logic combination module comprises a first inversion unit and a second inversion unit;

the first inversion unit is used for inverting the output signal of the first OR gate and providing the inverted signal to the reset input end of the second SR flip-flop;

the second inverting unit is used for inverting the output signal of the second OR gate and providing the inverted signal to the reset input end of the first SR flip-flop.

11. The glitch detection and processing circuit of claim 10 in which,

the first inversion unit comprises a first NAND gate, a first input end of the first NAND gate is connected to an output end of the first OR gate, a second input end of the first NAND gate receives a high-level signal,

the second inversion unit comprises a second nand gate, a first input end of the second nand gate is connected to an output end of the second or gate, and a second input end of the second nand gate receives a high-level signal.

12. The glitch detection and processing circuit of claim 11 in which,

the logic combination module comprises a first NOR gate and a second NOR gate;

a first input terminal of the first nor gate is connected to an output terminal of a glitch filtering module, the glitch filtering module is configured to filter the glitch in the input signal to output a clean signal without the glitch, and a second input terminal of the first nor gate is connected to an output terminal of the first nand gate;

a first input of the second nor gate is connected to an output of the first nor gate, a second input of the second nor gate is connected to an output of the second nand gate, and the second nor gate outputs the glitch-spread signal.

13. The glitch detection and processing circuit of claim 12 in which said glitch filter module includes a plurality of buffers.

14. The glitch detection and processing circuit of claim 13 further comprising a third inverter, wherein the set input of the first SR flip-flop receives the input signal, the third inverter receiving the input signal and providing an inverted input signal to the set input of the second SR flip-flop.

15. The glitch detection and processing circuit of claim 1 in which the input signal is an enable signal for a system-on-a-chip.

16. A burr detection and processing circuit, comprising:

a first SR flip-flop, whose set input terminal receives the input signal of the glitch detection and processing circuit;

a second SR flip-flop, whose set input terminal receives the inverted signal of the input signal;

a first output end of the first SR trigger is connected to an input end of the first pulse forming submodule, and an output signal of the first pulse forming submodule is inverted and then input to a reset input end of the second SR trigger;

and a first output end of the second SR trigger is connected to an input end of the second pulse forming submodule, and an output signal of the second pulse forming submodule is inverted and then input to a reset input end of the first SR trigger.

17. The glitch detection and processing circuit of claim 16 in which,

the first pulse forming submodule comprises a first single-side delayer, a first inverter and a first OR gate, wherein the first single-side delayer is used for delaying the rising edge or the falling edge in an input signal of the first SR flip-flop for a preset time, a first output end of the first SR flip-flop is connected to an input end of the first inverter and an input end of the first single-side delayer, and an output end of the first inverter and an output end of the first single-side delayer are connected to an input end of the first OR gate;

the second pulse forming submodule comprises a second single-side delayer, a second inverter and a second or gate, the second single-side delayer is used for delaying the rising edge or the falling edge in the input signal of the second single-side delayer for the preset time, the first output end of the second SR trigger is connected to the input end of the second inverter and the input end of the second single-side delayer, and the output end of the second inverter and the output end of the second single-side delayer are connected to the input end of the second or gate.

18. The glitch detection and processing circuit of claim 17 further comprising:

a first inversion unit, an output terminal of the first or gate being connected to an input terminal of the first inversion unit, an output terminal of the first inversion unit being connected to a reset input terminal of the second SR flip-flop;

and the output end of the second OR gate is connected to the input end of the second inversion unit, and the output end of the second inversion unit is connected to the reset input end of the first SR flip-flop.

19. The glitch detection and processing circuit of claim 18 in which,

20. The glitch detection and processing circuit of claim 19 further comprising:

a spur filtering module that receives the input signal and filters spurs in the input signal to output a clean signal without the spurs at an output thereof;

a first NOR gate, wherein a first input end of the first NOR gate is connected to the output end of the burr filtering module, and a second input end of the first NOR gate is connected to the output end of the first NAND gate;

a second NOR gate, a first input of the second NOR gate being connected to the output of the first NOR gate, a second input of the second NOR gate being connected to the output of the second NAND gate.

21. A delay circuit for a system on a chip, comprising:

a delay cell array including a plurality of delay cells;

a glitch detection and processing circuit according to one of claims 1 to 20, an output of said glitch detection and processing circuit being connected to said plurality of delay cells in said delay array.

22. The delay circuit of claim 21, wherein the plurality of delay cells comprises a plurality of D flip-flops, wherein the output of the glitch detection and processing circuit is connected to the reset inputs of the plurality of D flip-flops in the delay array.

23. The delay circuit of claim 22, further comprising:

a first inverter receiving a first output signal from the delay array;

a first input end of the NAND gate receives an enable signal, a second input end of the NAND gate receives an output signal of the first inverter, and a third input end of the NAND gate receives a clock signal;

a data input end of the first D flip-flop receives the enable signal, a clock input end of the first D flip-flop receives an output signal of the NAND gate, and a reset input end of the first inverter receives the enable signal;

the input end of the second inverter receives the output signal of the NAND gate;

and the first input end of the AND gate receives the first output signal of the first D flip-flop, the second input end of the AND gate receives the output signal of the second inverter, and the output end of the AND gate is connected to the delay array.

24. The delay circuit of claim 21, wherein the plurality of D flip-flops in the delay array are connected in series, wherein the second output of a previous D flip-flop is connected to its own D input and to the clock input of a subsequent D flip-flop, and wherein the output of the and gate is connected to the clock input of the first D flip-flop in the delay array.

25. A system on a chip, comprising:

a low voltage domain system receiving an enable signal and operating under control of the enable signal to provide a low voltage;

the delay circuit of one of claims 21-24, configured to receive the enable signal and to provide a delayed enable signal; and

a high voltage domain system receiving the delayed enable signal and the low voltage and operating under control of the delayed enable signal to provide a high voltage.

26. A memory device, comprising:

a storage unit; and

peripheral circuitry configured to include the glitch detection and processing circuitry of one of claims 1-20 or the delay circuitry of one of claims 21-24.