CN210090558U

CN210090558U - Timer clock detection system

Info

Publication number: CN210090558U
Application number: CN201920732424.5U
Authority: CN
Inventors: 吕英杰
Original assignee: Tianjin Pengxiang Huaxia Technology Co Ltd
Current assignee: Tianjin Pengxiang Huaxia Technology Co Ltd
Priority date: 2019-05-21
Filing date: 2019-05-21
Publication date: 2020-02-18
Anticipated expiration: 2029-05-21

Abstract

A timer clock detection system comprises a clock detection module and a timer module connected with a vss pin of the clock detection module, wherein the vss pin is grounded, the clock detection module is connected with a vreg pin, an rn pin and a ca pin, the ca pin is connected with a ca series terminal, the rn pin is connected with a reset terminal, and the output end of the clock detection module and the output end of the timer module are connected with a clk abrormal pin through an OR gate. The utility model discloses a be between timer module and the clock detection module or the door relation, when having one in clock detection module or the timer module for the high level, then the electric potential of output just is the high level, and the time-recorder among the clock detection module is 75us intervals, can carry out accurate measurement to the clock signal of input, and the timer module is the watchdog circuit, provides the reserve protection for detecting system.

Description

Timer clock detection system

Technical Field

The utility model belongs to the technical field of timing detection device technique and specifically relates to a timer clock detecting system.

Background

A clock signal is the basis of sequential logic, which determines when states in a logic cell are updated, is a semaphore with a fixed period and which is independent of operation, has a fixed clock frequency, which is the inverse of the clock period, and in synchronous digital circuits of electronic signals, a clock signal is a high and low state between special signal oscillations of a signal, the digital clock signal being substantially a square wave voltage. The clock control signal is also called as a timing signal, is a signal for controlling the double-clock alternate switching through 'off' and 'on', and the timing signal is the key for ensuring the complete synchronous work of the whole digital communication system. It is obvious from this that the importance of the clock signal is especially important for detecting the clock signal in the weak current system, and it is necessary to ensure not only the accuracy but also the prevention of the misoperation.

Therefore, a timer clock detecting system capable of accurately detecting a clock needs to be designed.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's not enough, provide a test system who realizes the clock detection purpose through the time-recorder.

The utility model provides a its technical problem take following technical scheme to realize:

a timer clock detection system comprises a clock detection module and a timer module connected with a vss pin of the clock detection module, wherein the vss pin is grounded, the clock detection module is connected with a vreg pin, an rn pin and a ca pin, the vreg pin is connected with a 3.3V reference voltage, the ca pin is connected with a ca series terminal, the rn pin is connected with a reset terminal, and the output end of the clock detection module and the output end of the timer module are connected with a clk abnormal pin through an OR gate.

Preferably, the clock detection module includes a timer, a timer reset pin of the timer is connected with a clk clock input signal, a vss pin of the timer is grounded, and a timer up pin of the timer is connected with a clk out pin through a series connection of a D flip-flop to output a clock signal.

Preferably, the time interval of the timer is 75 us.

Preferably, the vreg pin of timer be connected with the S utmost point of first PMOS pipe, the pd pin of timer connect the G utmost point of first PMOS pipe, the D utmost point of first PMOS pipe be connected with the third PMOS pipe, the pd pin of timer still be connected with the G utmost point of second PMOS pipe, the timer reset pin of timer be connected with the G utmost point of second NMOS pipe, the iclk detector pin of timer be connected with the S utmost point of first NMOS pipe, the vss pin of timer connect the D utmost point of second NMOS pipe, the D utmost point of third PMOS pipe with the S utmost point of second NMOS pipe parallelly connected through not door connection time up pin.

Preferably, an I2c cmd pin of the timer module is connected to an input command of the I2C, a wdt clr pin of the timer module is connected to a Watchdog timer clearing signal, the I2c cmd pin is connected to a D terminal of a D flip-flop, the wdt clr pin is connected to an R terminal of the D flip-flop through series connection of two not gates, and a plurality of the D flip-flops are connected to a wdt out pin in series.

The utility model has the advantages that:

the utility model discloses a be between timer module and the clock detection module or the door relation, when having one in clock detection module or the timer module for the high level, then the electric potential of output just is the high level, then assigns the instruction of stopping, the timer in the clock detection module is 75us intervals, can carry out the accuracy to the clock signal of input and measure, the timer module is watchdog circuit, for detecting system provides reserve protection, guaranteed can not take place because of the condition of no operation continuation operation.

Drawings

Fig. 1 is a schematic diagram of the circuit structure of the present invention;

fig. 2 is a schematic circuit diagram of the clock detection module of the present invention;

fig. 3 is a schematic circuit diagram of the timer of the present invention;

fig. 4 is a schematic circuit diagram of the timer module of the present invention.

In the figure: 1. a first PMOS tube; 2. a second PMOS tube; 3. a first NMOS transistor; 4. a third PMOS tube; 5. and a second NMOS transistor.

Detailed Description

The embodiments of the present invention will be described in detail with reference to the accompanying drawings:

as shown in fig. 1, a timer clock detecting system, including clock detection module, still include with the timer module that clock detection module's vss pin links to each other, vss pin ground connection, clock detection module be connected with vreg pin, rn pin and ca pin, vreg pin is connected at 3.3V reference voltage, ca pin connect ca series terminal, rn pin connects the reset terminal, clock detection module's output with the output of timer module be connected with clk abnormal pin through or the door.

As shown in fig. 2, the clock detection module includes a timer, and the time interval of the timer is 75 us. The timer reset pin of the timer is connected with a clk clock input signal, the vss pin of the timer is grounded, and the timer up pin of the timer is connected with a clk out pin in series through a D trigger to output a clock signal.

In addition, the clk pin of the clock detection module is a clock signal input terminal, the clk dct en pin is an input terminal of a clock stop detection signal set by a CDETECT instruction, and the do pin is an input terminal of a DOV (differential output voltage) signal set by a SETFET instruction, and when the discharge control is turned on at the time of high discharge detection, a high level potential is reached. The co pin is an input terminal of a COV signal set by the SETFET instruction, and reaches a high level potential when detecting overcharge. The Sda in pin is the input of the clock signal of the counter that detects SCL stop during detection, and the iclk detector pin is the input of the bias current (200nA) of the PMOS transistor.

As shown in fig. 3, the vreg pin of the timer is connected with the S pole of the first PMOS transistor 1, the pd pin of the timer is connected with the G pole of the first PMOS transistor 1, the D pole of the first PMOS transistor 1 is connected with the third PMOS transistor 4, the pd pin of the timer is further connected with the G pole of the second PMOS transistor 2, the timer reset pin of the timer is connected with the G pole of the second NMOS transistor 5, the iclk detector pin of the timer is connected with the S pole of the first NMOS transistor 3, the vss pin of the timer is connected with the D pole of the second NMOS transistor 5, and the D pole of the third PMOS transistor 4 and the S pole of the second NMOS transistor 5 are connected in parallel through the not-gate connection e up pin.

As shown in fig. 4, an I2c cmd pin of the timer module is connected to an input command of I2C, a wdt clr pin of the timer module is connected to a Watchdog timer clearing signal, the I2c cmd pin is connected to a D terminal of a D flip-flop, the wdt clr pin is connected to an R terminal of the D flip-flop through a series connection of two not gates, and a plurality of the D flip-flops are connected to a wdt out pin in series.

In specific implementation, a clock signal to be detected is input from a clk pin, an I2c cmd pin is connected to an I2C bus, an iclkdetector pin is connected to a bias current of 200nA, a vreg pin is connected to a 3.3V power voltage, a vss pin is grounded, an rn pin is connected to a reset instruction, the clock signal is input to a timer in a clock detection module, an incoming clock signal is detected through 75us intervals of the timer, the incoming clock signal is output through a clk out pin after data processing is completed, a wddt clr pin is a watchdog timer, the watchdog timer is used for monitoring the running state of the detection module system in real time, and when an NOOP (no-operation) instruction is input, the wdt out output is high level. When the clock detection module detects an overcharge or a high discharge, the clkout output is high. Because the output ends of the clock detection module and the timer module are connected through the OR gate and output signals, as long as one output signal of the signals output by the clock detection module and the signals output by the timer module is a high level, the clk abrormal pin can output the high level to the outside of the system so as to give an interrupt signal to the clock detection module and the timer module and stop the continuous work of the clock detection module and the timer module.

It should be emphasized that the embodiments described herein are illustrative and not restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also falls within the scope of the present invention, in any other embodiments derived by those skilled in the art according to the technical solutions of the present invention.

Claims

1. A timer clock detection system comprises a clock detection module and is characterized in that: the clock detection module is connected with a vreg pin, an rn pin and a ca pin, the vreg pin is connected to 3.3V reference voltage, the ca pin is connected with a ca series terminal, the rn pin is connected with a reset terminal, and the output end of the clock detection module and the output end of the timer module are connected with a clk abrormal pin through an OR gate.

2. The timer clock detection system of claim 1, wherein: the clock detection module comprises a timer, a timer reset pin of the timer is connected with a clk clock input signal, a vss pin of the timer is grounded, and a timer up pin of the timer is connected with a clk out pin in series through a D trigger to output a clock signal.

3. A timer clock detection system according to claim 2, wherein: the time interval of the timer is 75 us.

4. A timer clock detection system according to claim 2, wherein: the vreg pin of time-recorder be connected with the S utmost point of first PMOS pipe (1), the pd pin of time-recorder connect the G utmost point of first PMOS pipe (1), the D utmost point of first PMOS pipe (1) be connected with third PMOS pipe (4), the pd pin of time-recorder still be connected with the G utmost point of second PMOS pipe (2), the timer reset pin of time-recorder be connected with the G utmost point of second NMOS pipe (5), the iclk detector pin of time-recorder be connected with the S utmost point of first NMOS pipe (3), the vss pin of time-recorder connect the D utmost point of second NMOS pipe (5), the D utmost point of third PMOS pipe (4) with the S utmost point of second NMOS pipe (5) parallelly connected through non-gate connection time up pin.

5. The timer clock detection system of claim 1, wherein: the I2c cmd pin of timer module insert I2C's input instruction, the wdt clr pin of timer module insert the Watchdog timer clear signal, the I2c cmd pin is connected with the D end of D flip-flop, the wdt clr pin through the series connection of two NOT gates the R end of D flip-flop, a plurality of the D flip-flop series connection wdt out pin.