CN217955097U - A clock detection circuit - Google Patents

Abstract

The utility model provides a clock detection circuit, which includes a first pulse generator, a second pulse generator, a counter and a timer. The input terminal of the first pulse generator is connected with the Q0 terminal of the counter, and the output terminal is externally connected with the first or The input terminal of the gate, the input terminal of the second pulse generator is externally connected to the clk terminal, the output terminal thereof is externally connected to the first OR gate, the first OR gate passes through the first switch, the current source is externally connected to the dvdd terminal, and the current source passes through the first NOT gate and the second The two NOT gates are externally connected to a latch, the latch is connected to the clk terminal of the counter, the Q1 terminal of the counter is externally connected to a trigger, the trigger is externally connected to a logic gate circuit, and the Q terminal of the trigger is externally connected to the clk_abnormal terminal through the second OR gate , the input terminal of the second OR gate is externally connected with I2C_cmd and I2C_clr terminals through the timer. The utility model can output a clock abnormal signal by carrying out logic control through a logic gate circuit.

Description

A clock detection circuit

technical field

The utility model relates to the technical field of clock detection, in particular to a clock detection circuit.

Background technique

The clock signal is the basis of sequential logic. It is used to determine when the state in the logic unit is updated. It is a semaphore with a fixed period and has nothing to do with operation. A clock signal has a fixed clock frequency, which is the reciprocal of the clock period. Clock signals are often used in synchronous circuits to play the role of timers to ensure that related electronic components are synchronized; clocks can be used to synchronize different processes of the MCU, and the cycle output can be changed through rising or falling edges. Once the external clock provided to the circuit board fails, some chips on the circuit board will not work normally; in severe cases, even if the clock is restored, the chip cannot work normally, and the chip needs to be re-initialized to resume normal operation.

Utility model content

In view of this, the problem to be solved by the utility model is to provide a clock detection circuit.

In order to solve the above-mentioned technical problems, the technical solution adopted by the utility model is: a clock detection circuit, comprising a first pulse generator, a second pulse generator, a counter and a timer, the input terminal of the first pulse generator is connected to The Q0 terminal of the counter is connected, the output terminal of the first pulse generator is externally connected to the input terminal of the first OR gate, the input terminal of the second pulse generator is externally connected to the clk terminal, and the output of the second pulse generator The terminal is externally connected to the input terminal of the first OR gate, the output terminal of the first OR gate is externally connected to the dvdd terminal through the first switch, the current source is externally connected to the dvdd terminal, and the current source is externally connected to a latch through the first NOT gate and the second NOT gate The latch is connected to the clk terminal of the counter, the Q1 terminal of the counter is externally connected with a flip-flop, and the flip-flop is externally connected with a logic gate circuit, and the Q terminal of the flip-flop is connected externally through the second OR gate There is a clk_abnormal terminal, and the input terminal of the second OR gate is externally connected with an I2C_cmd terminal and an I2C_clr terminal through the timer.

In the present utility model, preferably, a third OR gate is provided between the second pulse generator and the flip-flop, and one input terminal of the third OR gate is connected to the latch, so The other input end of the third OR gate is connected to the output end of the second pulse generator, and the output end of the third OR gate is connected to the clk terminal of the flip-flop.

In the present invention, preferably, the logic gate circuit includes a first NOR gate, a second NOR gate, a first AND gate, a first NAND gate, a fourth OR gate and a third NOT gate, and the The Rn terminal of the flip-flop is connected to the output terminal of the third NOT gate, the input terminal of the third NOT gate is connected to the output terminal of the second NOR gate, and one input of the second NOR gate terminal is connected with the output terminal of the second pulse generator, the other input terminal of the second NOR gate is connected with the output terminal of the first NAND gate, and one input terminal of the first NAND gate terminal is connected with the output terminal of the first AND gate, the other input terminal of the first NAND gate is connected with the output terminal of the fourth OR gate, and one input terminal of the first AND gate is connected with the output terminal of the fourth OR gate. The output terminal of the first NOR gate is connected, the other input terminal of the first AND gate is externally connected with the Rn terminal, the two input terminals of the first NOR gate are respectively externally connected with the CLK_DTC_EN terminal and the PWS_EN terminal, and the The two input ends of the fourth OR gate are externally connected with a CO terminal and a DO terminal respectively.

In the present invention, preferably, the flip-flop is set as a D-type flip-flop.

The utility model has the advantages and positive effects: the clk terminal is used to input the clock detection signal, and is connected to the I2C bus through the I2C_cmd terminal, and the working frequency of the I2C_SCL is 32K. If the H and L of the SCL do not change within 1 ms or longer , it is judged that an abnormality has occurred, and the clock signal is detected and output through the clk_out terminal of the flip-flop. The CO terminal is used to input the CO signal from the decoder. When overcharging is detected, the "H" level turns on the charging control. The DO terminal is used to input the DO signal from the decoder. When over-discharge is detected, the "H" level turns on the discharge control. Through the built-in counter, each time I2C receives control commands and data from the MCU, it counts. When the counter counts to 128, it is determined that there is a problem with the MCU. When the MCU is working normally, the counter clearing signal is sent regularly through I2C. When either the trigger or the timer outputs a high level, the output signal is a high level. The logic control through the logic gate circuit can output a clock abnormal signal. The structure Simple and easy to control.

Description of drawings

The accompanying drawings are used to provide a further understanding of the utility model, and constitute a part of the description, and are used to explain the utility model together with the embodiments of the utility model, and do not constitute a limitation to the utility model. In the attached picture:

FIG. 1 is an overall structural diagram of a clock detection circuit of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or there can also be an intervening component. When a component is said to be "connected" to another component, it may be directly connected to the other component or there may be intervening components at the same time. When a component is said to be "set on" another component, it may be set directly on the other component or there may be an intervening component at the same time. The terms "vertical," "horizontal," "left," "right," and similar expressions are used herein for purposes of illustration only.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of this invention. The terminology used in the description of the utility model herein is only for the purpose of describing specific embodiments, and is not intended to limit the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in Figure 1, the utility model provides a clock detection circuit, including a first pulse generator, a second pulse generator, a counter and a timer, the input terminal of the first pulse generator is connected with the Q0 terminal of the counter, and the second The output end of a pulse generator is externally connected to the input end of the first OR gate, the input end of the second pulse generator is externally connected to the clk terminal, the output end of the second pulse generator is externally connected to the input end of the first OR gate, and the input end of the first OR gate The output terminal is externally connected to the dvdd terminal through the first switch, the current source is externally connected to a latch through the first NOT gate and the second NOT gate, the latch is connected to the clk terminal of the counter, and the Q1 terminal of the counter is externally connected to a trigger. The flip-flop is externally connected with a logic gate circuit, the Q terminal of the flip-flop is externally connected with the clk_abnormal terminal through the second OR gate, and the input terminal of the second OR gate is externally connected with the I2C_cmd terminal and the I2C_clr terminal through the timer.

In this embodiment, further, a third OR gate is provided between the second pulse generator and the flip-flop, one input terminal of the third OR gate is connected to the latch, and the other input terminal of the third OR gate It is connected with the output terminal of the second pulse generator, and the output terminal of the third OR gate is connected with the clk terminal of the flip-flop.

In this embodiment, further, the logic gate circuit includes a first NOR gate, a second NOR gate, a first AND gate, a first NAND gate, a fourth OR gate and a third NOT gate, and the Rn of the flip-flop terminal is connected with the output terminal of the third NOT gate, the input terminal of the third NOT gate is connected with the output terminal of the second NOR gate, and one input terminal of the second NOR gate is connected with the output terminal of the second pulse generator, The other input terminal of the second NOR gate is connected with the output terminal of the first NAND gate, one input terminal of the first NAND gate is connected with the output terminal of the first AND gate, and the other input terminal of the first NAND gate The terminal is connected with the output terminal of the fourth OR gate, one input terminal of the first AND gate is connected with the output terminal of the first NOR gate, the other input terminal of the first AND gate is externally connected with the Rn terminal, and the first NOR gate The two input terminals of the fourth OR gate are respectively externally connected with the CLK_DTC_EN terminal and the PWS_EN terminal, and the two input terminals of the fourth OR gate are respectively externally connected with the CO terminal and the DO terminal.

In this embodiment, further, the flip-flop is set as a D-type flip-flop.

The dvdd terminal is a digital power supply pin, vss is a ground pin, the PWS_EN terminal is used to input the power-saving enable signal, and the clock detection circuit does not work when the protection IC starts, the I2C_clr terminal is used to input the timer clear signal from the decoder, I2C_cmd The terminal is used to input the timer count signal from the decoder, the Rn terminal is used to input the reset signal, the clk_abnormal terminal is the clock abnormal signal output, and the CLK_DTC_EN terminal is used to input the enable signal from the decoder. The clk terminal is used to input the clock detection signal. It is connected to the I2C bus through the I2C_cmd terminal. The operating frequency of I2C_SCL is 32K. If the H and L of SCL do not change within 1ms or longer, it is judged that an abnormality has occurred. After detecting the clock signal It is output via the clk_out terminal of the flip-flop, and the CO terminal is used to input the CO signal from the decoder. When overcharging is detected, the "H" level turns on the charging control. The DO terminal is used to input the DO signal from the decoder. When over-discharge is detected, the "H" level starts the discharge control. Through the built-in counter, each time I2C receives control commands and data from the MCU, it counts. When the counter counts to 128, it is determined that there is a problem with the MCU. When the MCU is working normally, the counter clearing signal is sent regularly through I2C, and the logic control through the logic gate circuit can output the abnormal clock signal, which is simple in structure and easy to control.

The embodiments of the present utility model have been described in detail above, but the content described is only a preferred embodiment of the present utility model, and cannot be considered as limiting the implementation scope of the present utility model. All equal changes and improvements made according to the scope of the present utility model should still belong to the scope covered by this patent.

Claims (4)

1. A clock detection circuit is characterized by comprising a first pulse generator, a second pulse generator, a counter and a timer, wherein the input end of the first pulse generator is connected with a Q0 terminal of the counter, the output end of the first pulse generator is externally connected with the input end of a first OR gate, the input end of the second pulse generator is externally connected with a clk terminal, the output end of the second pulse generator is externally connected with the input end of the first OR gate, the output end of the first OR gate is externally connected with a dvdd terminal through a first switch and a current source, the current source is externally connected with a latch through a first NOT gate and a second NOT gate, the latch is connected with the clk terminal of the counter, a trigger is externally connected with a Q1 terminal of the counter, a logic gate circuit is externally connected with the Q terminal of the trigger, a clk _ ABNORMAL terminal is externally connected with a second OR gate, and the input end of the second OR gate is externally connected with an I2C _ cmd terminal and an I2C _ clr terminal through the timer.

2. A clock detection circuit as claimed in claim 1, wherein a third or-gate is provided between the second pulse generator and the flip-flop, one input of the third or-gate being connected to the latch, the other input of the third or-gate being connected to the output of the second pulse generator, and the output of the third or-gate being connected to the clk terminal of the flip-flop.

3. The clock detection circuit of claim 1, wherein the logic gate circuit comprises a first nor gate, a second nor gate, a first and gate, a first nand gate, a fourth or gate and a third nor gate, the Rn terminal of the flip-flop is connected to the output terminal of the third nor gate, the input terminal of the third nor gate is connected to the output terminal of the second nor gate, one input terminal of the second nor gate is connected to the output terminal of the second pulse generator, the other input terminal of the second nor gate is connected to the output terminal of the first nand gate, one input terminal of the first nand gate is connected to the output terminal of the first and gate, the other input terminal of the first nand gate is connected to the output terminal of the fourth or gate, one input terminal of the first and gate is connected to the output terminal of the first nor gate, the other input terminal of the first and gate is externally connected to Rn terminal, the two input terminals of the first nor gate are respectively connected to the CLK _ DTC _ terminal and the PWS _ EN terminal, and the two input terminals of the fourth nor gate are respectively externally connected to the CO terminal.

4. A clock detection circuit according to claim 1, wherein the flip-flop is configured as a D-type flip-flop.

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