CN217955097U

CN217955097U - Clock detection circuit

Info

Publication number: CN217955097U
Application number: CN202222211327.6U
Authority: CN
Inventors: 吕英杰
Original assignee: Tianjin Tengxiang Huaxia Technology Co ltd
Current assignee: Tianjin Tengxiang Huaxia Technology Co ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-12-02
Anticipated expiration: 2032-08-19

Abstract

The utility model provides a clock detection circuit, including first pulse generator, second pulse generator, counter and timer, first pulse generator's input links to each other with the Q0 terminal of counter, the external first input of OR gate of its output, the external clk terminal of second pulse generator's input, the external first OR gate of its output, first OR gate is through first switch, the external dvdd terminal of electric current source, the electric current source is external to have the latch through first NOT gate and second NOT gate, the latch links to each other with the clk terminal of counter, the Q1 terminal of counter is external to have the trigger, the trigger is external to have logic gate circuit, the Q terminal of trigger is external to have clk _ antinormal terminal through second OR gate, the input of second or gate is external to have I2C _ cmd and I2C _ clr terminal through the timer. The utility model discloses a logic gate circuit carries out logic control and can exports clock abnormal signal.

Description

Clock detection circuit

Technical Field

The utility model relates to a clock detection technical field, concretely relates to clock detection circuit.

Background

The clock signal is the basis of sequential logic, which determines when the state in a logic cell is updated, and is a semaphore with a fixed period and which is independent of operation. The clock signal has a fixed clock frequency, which is the inverse of the clock period. Clock signals are often used in synchronous circuits to play the role of a timer to ensure that the related electronic components are operated synchronously; the clock may be used to synchronize the different processes of the MCU, changing the periodic output by either a rising or falling edge. In case of failure of a clock externally provided to the circuit board, some chips on the circuit board may malfunction; in severe cases, even if the clock is recovered, the chip cannot work normally, and the chip needs to be reinitialized to recover the normal work.

SUMMERY OF THE UTILITY MODEL

In view of this, the present invention provides a clock detection circuit.

In order to solve the technical problem, the utility model discloses a technical scheme is: a clock detection circuit comprises a first pulse generator, a second pulse generator, a counter and a timer, wherein the input end of the first pulse generator is connected with a Q0 terminal of the counter, the output end of the first pulse generator is externally connected with the input end of a first OR gate, the input end of the second pulse generator is externally connected with a clk terminal, the output end of the second pulse generator is externally connected with the input end of the first OR gate, the output end of the first OR gate is externally connected with a dvdd terminal through a first switch and a current source, the current source is externally connected with a latch through a first NOT gate and a second NOT gate, the latch is connected with the clk terminal of the counter, a trigger is externally connected with a Q1 terminal of the counter, a logic gate circuit is externally connected with the Q terminal of the trigger, a clk _ ABNORMA terminal is externally connected with a second OR gate, and an I2C _ cmd terminal and an I2C _ clr terminal are externally connected with the input end of the second OR gate through the timer.

In the present invention, preferably, a third or gate is provided between the second pulse generator and the flip-flop, one input end of the third or gate is connected to the latch, another input end of the third or gate is connected to the output end of the second pulse generator, and the output end of the third or gate is connected to the clk terminal of the flip-flop.

In the present invention, preferably, the logic gate circuit includes a first nor gate, a second nor gate, a first and gate, a first nand gate, a fourth or gate and a third nor gate, the Rn terminal of the flip-flop is connected to the output of the third nor gate, the input of the third nor gate is connected to the output of the second nor gate, one input of the second nor gate is connected to the output of the second pulse generator, the other input of the second nor gate is connected to the output of the first nand gate, one input of the first nand gate is connected to the output of the first and gate, the other input of the first nand gate is connected to the output of the fourth or gate, one input of the first and gate is connected to the output of the first nor gate, the other input of the first and gate has an Rn terminal, the two inputs of the first nor gate are respectively externally connected to a CLK _ DTC _ terminal and a PWS _ EN terminal, and the two inputs of the fourth or gate have a DO terminal and a CO terminal, respectively.

In the present invention, preferably, the flip-flop is configured as a D-type flip-flop.

The utility model has the advantages and positive effects that: the clk terminal is used for inputting a clock detection signal, the I2C bus is accessed through the I2C _ cmd terminal, the operating frequency of the I2C _ SCL is 32K, if the H and L of the SCL do not change within 1ms or longer, the abnormality is judged to occur, the clock signal is detected and then output through the clk _ out terminal of the trigger, the CO terminal is used for inputting a CO signal from the decoder, and when overcharge is detected, the charging control is started at an H level. The DO terminal is used to input a DO signal from the decoder, and when overdischarge is detected, the "H" level turns on the discharge control. Through the built-in counter, the I2C counts each time when receiving the control command and data from the MCU, and when the counter counts to 128, the MCU is determined to have a problem. When the MCU normally works, the counter clear signal is sent by the I2C timing, when one of the trigger or the timer outputs high level, the output signal is high level, the clock abnormal signal can be output by logic control through the logic gate circuit, and the clock abnormal signal is simple in structure and easy to control.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is an overall structure diagram of a clock detection circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, the utility model provides a clock detection circuit, including first pulse generator, second pulse generator, counter and timer, first pulse generator's input links to each other with the Q0 terminal of counter, the external first input of OR gate of first pulse generator's output, the external clk terminal of second pulse generator's input, the external first input of OR gate of second pulse generator's output, the external dvdd terminal of first output of OR gate through first switch, the external first latch that has of current source, the current source has through first NOT gate and the external latch that has of second NOT gate, the latch links to each other with the clk terminal of counter, the external flip-flop that has of Q1 terminal of counter, the external logical gate circuit that has of flip-flop, the external _ ABNORMAL terminal that has through second or gate, the external I2C _ cmd terminal and I2C _ clr terminal of second OR gate through the timer.

In this embodiment, a third or gate is further disposed between the second pulse generator and the flip-flop, one input terminal of the third or gate is connected to the latch, the other input terminal of the third or gate is connected to the output terminal of the second pulse generator, and the output terminal of the third or gate is connected to the clk terminal of the flip-flop.

In this embodiment, the logic gate circuit further includes a first nor gate, a second nor gate, a first and gate, a first nand gate, a fourth or gate and a third nor gate, an Rn terminal of the flip-flop is connected to an output terminal of the third nor gate, an input terminal of the third nor gate is connected to an output terminal of the second nor gate, an input terminal of the second nor gate is connected to an output terminal of the second pulse generator, another input terminal of the second nor gate is connected to an output terminal of the first nand gate, an input terminal of the first nand gate is connected to an output terminal of the first and gate, another input terminal of the first nand gate is connected to an output terminal of the fourth or gate, an input terminal of the first and gate is connected to an output terminal of the first nor gate, another input terminal of the first and gate is externally connected to an Rn terminal, two input terminals of the first nor gate have an external CLK _ DTC _ EN terminal and an external PWS _ EN terminal, and two input terminals of the fourth or gate have a CO terminal and a DO terminal, respectively.

In the present embodiment, further, the flip-flop is configured as a D-type flip-flop.

The dvdd terminal is a digital power supply pin, vss is a ground pin, the PWS _ EN terminal is used for inputting a power saving enable signal, the clock detection circuit does not work when the IC is protected from being started, the I2C _ clr terminal is used for inputting a timer clear signal from the decoder, the I2C _ cmd terminal is used for inputting a timer count signal from the decoder, the Rn terminal is used for inputting a reset signal, the CLK _ denormal terminal is used for outputting a clock abnormal signal, and the CLK _ DTC _ EN terminal is used for inputting an enable signal from the decoder. The clk terminal is used for inputting a clock detection signal, the I2C bus is accessed through the I2C _ cmd terminal, the operating frequency of the I2C _ SCL is 32K, if the H and L of the SCL do not change within 1ms or longer, the abnormality is judged to occur, the clock signal is detected and then output through the clk _ out terminal of the trigger, the CO terminal is used for inputting a CO signal from the decoder, and when overcharge is detected, the charging control is started at an H level. The DO terminal is used to input a DO signal from the decoder, and when overdischarge is detected, the "H" level turns on the discharge control. Through the built-in counter, the I2C counts each time when receiving the control command and data from the MCU, and when the counter counts to 128, the MCU is determined to have a problem. When the MCU normally works, the counter clear signal is sent by the I2C timing, the clock abnormal signal can be output by performing logic control through the logic gate circuit, and the MCU is simple in structure and easy to control.

The above detailed description of the embodiments of the present invention is only for the purpose of describing the preferred embodiments of the present invention, and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.

Claims

1. A clock detection circuit is characterized by comprising a first pulse generator, a second pulse generator, a counter and a timer, wherein the input end of the first pulse generator is connected with a Q0 terminal of the counter, the output end of the first pulse generator is externally connected with the input end of a first OR gate, the input end of the second pulse generator is externally connected with a clk terminal, the output end of the second pulse generator is externally connected with the input end of the first OR gate, the output end of the first OR gate is externally connected with a dvdd terminal through a first switch and a current source, the current source is externally connected with a latch through a first NOT gate and a second NOT gate, the latch is connected with the clk terminal of the counter, a trigger is externally connected with a Q1 terminal of the counter, a logic gate circuit is externally connected with the Q terminal of the trigger, a clk _ ABNORMAL terminal is externally connected with a second OR gate, and the input end of the second OR gate is externally connected with an I2C _ cmd terminal and an I2C _ clr terminal through the timer.

2. A clock detection circuit as claimed in claim 1, wherein a third or-gate is provided between the second pulse generator and the flip-flop, one input of the third or-gate being connected to the latch, the other input of the third or-gate being connected to the output of the second pulse generator, and the output of the third or-gate being connected to the clk terminal of the flip-flop.

3. The clock detection circuit of claim 1, wherein the logic gate circuit comprises a first nor gate, a second nor gate, a first and gate, a first nand gate, a fourth or gate and a third nor gate, the Rn terminal of the flip-flop is connected to the output terminal of the third nor gate, the input terminal of the third nor gate is connected to the output terminal of the second nor gate, one input terminal of the second nor gate is connected to the output terminal of the second pulse generator, the other input terminal of the second nor gate is connected to the output terminal of the first nand gate, one input terminal of the first nand gate is connected to the output terminal of the first and gate, the other input terminal of the first nand gate is connected to the output terminal of the fourth or gate, one input terminal of the first and gate is connected to the output terminal of the first nor gate, the other input terminal of the first and gate is externally connected to Rn terminal, the two input terminals of the first nor gate are respectively connected to the CLK _ DTC _ terminal and the PWS _ EN terminal, and the two input terminals of the fourth nor gate are respectively externally connected to the CO terminal.

4. A clock detection circuit according to claim 1, wherein the flip-flop is configured as a D-type flip-flop.