CN101087132B - Adjustment method of clock fifty percent idle percent based on phase synthesis - Google Patents
Adjustment method of clock fifty percent idle percent based on phase synthesis Download PDFInfo
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- CN101087132B CN101087132B CN200710035335A CN200710035335A CN101087132B CN 101087132 B CN101087132 B CN 101087132B CN 200710035335 A CN200710035335 A CN 200710035335A CN 200710035335 A CN200710035335 A CN 200710035335A CN 101087132 B CN101087132 B CN 101087132B
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Abstract
The invention discloses a clock 50% duty ratio adjusting method which is based on phase systemization, steps are: (1) Pulse generating: source clock input is transmitted into narrow pulse signal by pulse generating circuit, frequency is kept; (2) half cycle delay: marrow pulse signal obtained in step (1) is delayed for half-cycle; (3) image delay: pulse signal delayed for half period is delayed for half period to obtain pulse signal whose period is a period from signal in step (1); (4) phase synthesizing: pulse signal in step (2) and step (3) are superposed to obtain pulse signal whose frequency is two times of source clock, clock signal whose phase is similar and duty ratio is 50% is as output signal. The invention can adjust 50% duty ratio for clock signal whose frequency and duty ratioare within definite range, capability of defend Voltage Temperatre interfere is strong, quality of clock wave output is high.
Description
Technical field
The present invention is mainly concerned with the control method field of cmos clock signal 50% duty ratio, refers in particular to a kind of based on synthetic clock 50% dutyfactor adjusting method of phase place.
Background technology
Along with improving constantly of integrated circuit dominant frequency, the clock cycle becomes shorter and shorter.In the strict circuit of some sequential, register read write circuit for example, clock signal is bilateral along sample circuit in the DDR technology, and the slight jitter at clock edge will produce considerable influence to the sequential relationship of circuit, even cause system correctly not work.In cmos circuit, because of PMOS pipe and NMOS pipe driving force do not match, the existence of factors such as interconnection line parasitic capacitance distribution interference, duty ratio may take place and seriously distort in the source clock signal in transmission course.For this reason, press for this type of clock is carried out duty cycle adjustment to improve systematic function.
At present, dutyfactor adjusting method has multiple: phase-locked loop pll (Phase Locked Loop) method, synthetic CPB (the Complementary Phase Blending) method of complementary phases, delay lock loop DLL (Delay Locked Loop) method, pulse duration control ring PWCL (Pulse Width Control Loop) method etc., the main body when these methods realize is analog circuit.
In the PLL method, owing to there is feedback control loop, complex circuit designs, degree of regulation is high but be easy to generate fluctuation, generally needs hundreds of the clock cycle just can locking phase.Analog PLL is difficult to produce 50% duty cycle clock signal of upper frequency because of the structural limitations of self, and designing requirement is unusual accurate to guarantee that circuit still can operate as normal when the variation of process deviation and voltage temperature takes place.In the complementary phases synthetic method, owing to rely on complementary clock signal, this method is just no longer suitable when device mismatch.When the input clock duty ratio is near 50%, can obtain comparatively accurate 50% duty cycle clock; But when the input clock duty ratio departs from 50% when big, the output clock duty cycle is not satisfactory, and range of application is narrow.In the DLL method, phase detectors speed is slow, has limited the raising of adjusting function.And when adopting pulse duration control method, the locking result of PLL or DLL is disturbed in the change of phase place easily, under the bad situation even cause the locking failure.
This shows, adopt the simulation way to realize that duty cycle adjustment exists many common defectives, poor anti jamming capability.And the digital dock duty cycle adjustment technology of some open loops does not consider to export the phase deviation between clock and the source clock, and it is long to regulate operation, generally needs 5-10 clock cycle just can finish.The present invention adopts the pure digi-tal mode, based on the phase place synthetic technology a kind of clock signal 50% dutyfactor adjusting method has been proposed, the various defectives that exist in the above design have been eliminated, regulate operation and only need 4 clock cycle, there is not complicated feedback control loop, make that duty cycle adjustment realizes being more prone to, efficient.
Summary of the invention
The problem to be solved in the present invention just is: at the technical problem that prior art exists, the invention provides a kind ofly can carry out 50% duty cycle adjustment, have that anti-VT interference performance is strong the clock signal that frequency and duty ratio all change within the specific limits, the clock waveform quality advantages of higher after the frequency division output based on synthetic clock 50% dutyfactor adjusting method of phase place.
For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of based on synthetic clock 50% dutyfactor adjusting method of phase place, it is characterized in that step is:
(1), pulse produces: by pulse-generating circuit, the source clock of importing is converted into narrow pulse signal, frequency remains unchanged;
(2), the half period postpones: the narrow pulse signal of gained in the step (1) is postponed the half period;
(3), mirror delay: postpone the half period again with having postponed the pulse signal of half period in the step (2), obtain with step (1) in pulse signal differ the pulse signal of one-period;
(4), phase place is synthetic: the pulse signal of output in step (2) and the step (3) is carried out the phase place stack, and obtaining frequency is the pulse signal of 2 times on source clock;
(5), two divided-frequency: the pulse signal after synthetic in the step (4) is carried out two divided-frequency, obtain identically with source clock frequency, phase place unanimity and duty ratio are that 50% clock signal is as output signal.
The idiographic flow of described step (2) is:
(1), the clock cycle measures: the measurement of clock cycle is finished by measuring delay line, with the pulse signal of step (1) gained through behind the two divided-frequency as the clock CLK that measures delay line, the lasting time of such high level just is a clock cycle of source clock; After reset circuit is closed, high level signal begins to propagate in measuring delay line by the initial delay line in the half period delay line, the input of initial delay line is changed to high level all the time, the low level pulse signal that resets always produces in the half period of source clock signal when low, makes the propagation of high level signal and sampling to hocket; When reset signal is put when low, clock signal also is a low level, sample circuit starts the output level of sampling delay unit, high level signal is propagated the position stop, sampled result output just, the corresponding length of source clock signal period, when reset signal is put when high, sampler cuts out, and measures the zero clearing that resets of unit in the delay line, for period measurement is next time prepared.After clock signal was put height once more, high level signal continued to propagate forward along measuring delay line;
(2), clock phase adjustment: the pulse signal that has carried out period measurement is carried out the half period time-delay, and the clock phase adjustment is finished by vairable delay line.
Compared with prior art, advantage of the present invention just is:
1, the anti-VT of the present invention (Voltage, Temperature) interference performance is strong.When the shake in the voltage generation allowed band, mirror image delay circuit (MDL) is subjected to identical influence simultaneously with main circuit, and is highly consistent thereby circuit delay keeps, also like this during variations in temperature;
2, used the frequency-halving circuit technology among the present invention, the clock waveform quality height after the output of phase place composite signal frequency division, clock is precipitous unusually along saltus step, very near desirable clock;
3, the present invention adopts time-delay full remuneration strategy according to the mirror delay principle, makes each step realize high-precision time-delay coupling, has reduced the phase deviation between output clock and source clock greatly, has kept synchronized relation between input/output signal.
Description of drawings
Fig. 1 is a schematic flow sheet of the present invention;
Fig. 2 be with Fig. 1 in the pairing sequential schematic diagram of flow process;
Fig. 3 is the structural representation of half period delay line;
Fig. 4 is a structural representation of measuring delay line;
The vairable delay line logical construction schematic diagram that Fig. 5 is made up of the NAND gate array.
Embodiment
Below with reference to the drawings and specific embodiments the present invention is described in further details.
The present invention uses the pure digi-tal mode, utilizes the mirror delay principle to realize not having the synthetic duty cycle adjustment of phase place of feedback control loop, and how the key that makes the output clock reach 50% duty ratio is by the source clock generating mirror image clock of 180 ° of phase phasic differences with it.In measuring the process of clock cycle, according to image theory, the numerical control delay line will make the phase delay half period of source clock signal, then, the two-way clock of phase phasic difference half period by two inputs or door to carry out phase place synthetic.Like this, the clock after synthesizing all has along saltus step on every half period point, is equivalent to the source clock has been carried out frequency multiplication.Clearly, the clock after phase place is synthetic is again by frequency-halving circuit, and it is 50% same frequency clock that output is duty ratio.
After making clock phase synthetic, be unlikely the generation phrase overlap, must use burst pulse to produce circuit the different clock unification of the duty ratio of original input is shaped as narrow pulse signal.And there is certain time-delay in pulse-generating circuit, the source clock and postpone the half period after clock carry out having skewed clock inevitably when phase place is synthetic, and also there is phase skew during through frequency dividing circuit in the clock after synthetic.For compensating these deflections, pulse generator and or door between increase matching delay-line MDL (Matching Delay Line), the delay of matching delay-line should be
t
MDL＝t
CLK-t
PULSE-t
OR-t
FD
Annotate: t
MDLThe time-delay of-matching delay-line, t
CLK-the clock cycle
t
PULSEThe time-delay of-pulse generator, t
OR-or gate delay
t
FDThe time-delay of-frequency-halving circuit
Thereby output rising edge clock deflection just is a clock cycle,
t
SKEW＝t
PULSE+t
MDL+t
OR+t
FD＝t
CLK
Like this, the time-delay of circuit each several part unit has obtained full remuneration, has promptly realized no deflection output.But consider and be difficult to accomplish accurate time-delay complete cycle coupling under the different clock frequencies, simultaneously in order to save the number of delay cell, final MDL adopts the output signal of the vairable delay line of delayed half period in the half period delay line to postpone the half period again, to reach the purpose that postpones complete cycle, the design of MDL can be transplanted the vairable delay line logic in the half period delay line fully like this, reduces design difficulty thus greatly.
In sum, the technical scheme that the present invention is based on synthetic clock 50% dutyfactor adjusting method of phase place is made up of five steps as depicted in figs. 1 and 2, and it comprises: pulse produces, and the half period postpones, mirror delay, and the synthetic and two divided-frequency of phase place is exported.It is 50% high-quality clock that input clock is duty ratio through output after this five step.
(1), pulse produces
Pulse produces and refers to that by pulse-generating circuit the source clock is converted into narrow pulse signal, and frequency remains unchanged.Be that input among Fig. 2 obtains the pulse signal shown in the node A through pulse-generating circuit.
Carrying out such conversion has reason, if because the duty ratio of input clock distorts, duty ratio might not be always less than 50%, also might be greater than 50%.To the method among the present invention, the overlapping function that causes of clock high level very likely can take place make mistakes if directly original clock is handled, and carrying out when phase place is synthetic phrase overlap taking place easily, so must use pulse-generating circuit that the different source clock unification of the duty ratio of original input is shaped as narrow pulse signal.
In general, pulse-generating circuit can be realized by being sampled in very narrow window in the hopping edge of input signal.
(2), the half period postpones
The half period delay refers to the pulse delay signal half period gained in the step 1.It is the key component of the inventive method that clock is carried out accurate half period delay, has only the degree of regulation that postpones accurately could guarantee duty ratio.Step 2 comprises two steps: the measurement of clock cycle and the adjustment of clock phase, as shown in Figure 3.
1.. the clock cycle measures
The clock cycle measurement refers to the cycle of the pulse signal of step 1 generation is measured.Among Fig. 3, t
StdPeriodic quantity for the pulse signal of measuring gained.
The measurement of clock cycle is finished by measuring delay line, and the structure of measurement delay line as shown in Figure 4.Be made up of 8 groups of delay cells, every group of delay cell inside comprises 2 NAND gate groups and 1 sample circuit.Each NAND gate group is composed in series by two NAND gate, is used for controlling the transmission of high level signal; Sample circuit is to the output of sampling of the transmission stop position of high level signal.
Measure the delay line operation principle: the pulse signal of gained is through measure the clock CLK of delay line behind the two divided-frequency as this, as Fig. 4 in the step 1.A lasting time of high level just is a clock cycle of source clock so.After reset circuit was closed, high level signal began to propagate in measuring delay line by the initial delay line in the half period delay line (HCDL).The input of initial delay line is changed to high level all the time, and the low level pulse signal that resets always produces in the half period of source clock signal when low, makes the propagation of high level signal and sampling to hocket.Put when low when reset signal, clock signal also is a low level, and sample circuit starts, the output level of sampling delay unit.High level signal is propagated the position stop, sampled result output just, the corresponding length of source clock signal period.Put when high when reset signal, sampler cuts out, and measures the zero clearing that resets of unit in the delay line, for period measurement is next time prepared.After clock signal was put height once more, high level signal continued to propagate forward along measuring delay line.
2.. the clock phase adjustment
The clock phase adjustment refers to the pulse signal that has carried out period measurement is carried out the half period time-delay.The clock phase adjustment is finished by vairable delay line, as shown in Figure 5, is made up of a series of NAND gate.D1 is respectively 8 control ports to D8, and CLK_IN connects the pulse signal in the step 1, and CLK_OUT is for postponing the output of half period, shown in the Node B among Fig. 2.
Whenever t
StdPH-value determination pH after, the phase place adjustment is just to the pulse delay signal t of gained in the step 1
Std/ 2.Each output result of sampling delay unit in the clock cycle measurement all delivers to the control end D1-D8 of vairable delay line.Because each delay cell all comprises 2 NAND gate groups in the measurement delay line, and vairable delay line has only 1 NAND gate group accordingly.So after vairable delay line was received sampled result, each control port was correspondingly put height or is put lowly, begins to guide pulse signal that input comes in along the loop output that postpones the half period.
(3), mirror delay
Mirror delay refers to the pulse signal of the delay half period in the step 2 is postponed the half period again, obtain with step 1 in pulse signal differ the pulse signal of one-period, shown in the node C among Fig. 2.This function is realized that by mirror delay line (MDL) logical construction of mirror delay line and the variable delay line structure in the step 2 are identical.
This step produces for compensated pulse and the synthetic deflection that the source clock signal is brought of phase place is introduced, because there is time-delay in pulse-generating circuit and phase place combiner circuit self, make the phase of output signal of vairable delay line compare to exist to postpone, can realize the no deflection rising edge output of phase place after synthetic as long as the vairable delay line output signal is postponed the identical time again with the source clock.
(4), phase place is synthetic
Phase place is synthetic to refer to that phase place is carried out in the output of step 2 and step 3 to superpose, and obtaining frequency is the pulse signal of 2 times on source clock.
After step 1,2,3 is finished, the two-way pulse clock of phase phasic difference half period has just been arranged, i.e. Node B among Fig. 2 and node C.Expect 50% duty ratio, must the phase place of this two-way clock be superposeed.The present invention adopts two inputs or door that the two pulse signals at Node B and node C place is carried out phase place to synthesize.Obtainable signal after synthetic shown in the node D among Fig. 2.
(5), two divided-frequency
Two divided-frequency refers to pulse signal synthetic in the step 4 is carried out two divided-frequency, obtains identically with source clock frequency, and phase place unanimity and duty ratio are 50% clock signal, i.e. output among Fig. 2.
As described in step 4, the clock duty cycle at node D place has been 50%, but its frequency is the twice of original clock, so need carry out two divided-frequency in order to obtain to the pulse signal after synthetic with clock the present invention of source clock same frequency.
Claims (1)
1. one kind based on synthetic clock 50% dutyfactor adjusting method of phase place, it is characterized in that step is:
(1), pulse produces: by pulse-generating circuit, the source clock of importing is converted into narrow pulse signal, frequency remains unchanged;
(2), the half period postpones: the narrow pulse signal of gained in the step (1) is postponed the half period; At first carrying out the clock cycle measures, the measurement of clock cycle is finished by measuring delay line, with the pulse signal of step (1) gained through behind the two divided-frequency as the clock CLK that measures delay line, the lasting time of such high level just is a clock cycle of source clock; After reset circuit is closed, high level signal begins to propagate in measuring delay line by the initial delay line in the half period delay line, the input of initial delay line is changed to high level all the time, the low level pulse signal that resets always produces in the half period of source clock signal when low, makes the propagation of high level signal and sampling to hocket; When reset signal is put when low, clock signal also is a low level, and sample circuit starts the output level of sampling delay unit, and high level signal is propagated the position that stops, sampled result output just, the corresponding length of source clock signal period is put when high when reset signal, and sampler cuts out, measure the zero clearing that resets of unit in the delay line, prepare for period measurement next time, after clock signal was put height once more, high level signal continued to propagate forward along measuring delay line; Carry out the clock phase adjustment then, the pulse signal that has carried out period measurement is carried out the half period time-delay, the clock phase adjustment is finished by vairable delay line;
(3), mirror delay: postpone the half period again with having postponed the pulse signal of half period in the step (2), obtain with step (1) in pulse signal differ the pulse signal of one-period;
(4), phase place is synthetic: the pulse signal of output in step (2) and the step (3) is carried out the phase place stack, and obtaining frequency is the pulse signal of 2 times on source clock;
(5), two divided-frequency: the pulse signal after synthetic in the step (4) is carried out two divided-frequency, obtain identically with source clock frequency, phase place unanimity and duty ratio are that 50% clock signal is as output signal.
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| CN1136371A (en) * | 1993-11-24 | 1996-11-20 | 诺基亚电信公司 | Method and device for symmetrizing a clock signal |
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| CN109120257A (en) * | 2018-08-03 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | A kind of low jitter frequency-dividing clock circuit |
| CN109120257B (en) * | 2018-08-03 | 2020-06-12 | 中国电子科技集团公司第二十四研究所 | Low-jitter frequency division clock circuit |
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