CN102035512B - Clock phase-splitting technology-based precise digital time delay synchronous machine and time delay method - Google Patents
Clock phase-splitting technology-based precise digital time delay synchronous machine and time delay method Download PDFInfo
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- CN102035512B CN102035512B CN201010552082.2A CN201010552082A CN102035512B CN 102035512 B CN102035512 B CN 102035512B CN 201010552082 A CN201010552082 A CN 201010552082A CN 102035512 B CN102035512 B CN 102035512B
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Abstract
The invention relates to a digital time delay synchronous machine and a time delay method, in particular to a clock phase-splitting technology-based precise digital time delay synchronous machine and a time delay method. In order to solve the problems on complexity in setting up a charge-discharge constant-current source and a phase detection and phase compensation circuit in the prior art, the invention provides a precise digital time delay synchronous machine based on a clock phase-splitting technology, which ensures that precise time delay compensation of the time delay synchronous machine is achieved, and circuit setting-up is simple and reliable and is low in power consumption. In the technical scheme, the precise digital time delay synchronous machine comprises a front-end signal conditioning module, a delay synchronous control module, a signal driving module and an upper computer control module, and the delay synchronous control module comprises a clock phase-splitting circuit module, a counting delay circuit for accomplishing counting and data comparison and a communication interface module. Before synchronous signals enter each path, the digital time delay synchronous machine is applied to carry out predelay to compensate the nonuniformity of each path of system so that the output of each system is in an occasion of the synchronous signals.
Description
Technical field
The present invention relates to a kind of digital delay synchronous motor and time-delay method, particularly relate to a kind of digital delay synchronous motor and time-delay method based on clock phase-splitting technology.
Technical background
In the physical test of multiloop loop system, usually require the signal of each road system to arrive certain circuit node simultaneously, but because circuit element and mounting process that each system adopts can not be in full accord, so one group of synchronizing signal has just become nonsynchronous signal after the delay of each road system, this just needs a kind of instrument before synchronizing signal enters each road, to do delay in advance, to compensate the nonuniformity of each road system, Shi Ge road system is output as synchronizing signal, delay synchronizer that Here it is.Trigger error, time delay stepping and reference time delay are the important technology indexs of delay synchronizer.
Delivered " nuclear electronics and Detection Techniques " in November, 2006 and be entitled as " the impulsive synchronization machine development based on precision delay technology " employing analoging interpolation technology, i.e. large time delay employing is digital, and little time delay adopts analog variation formula.While utilizing capacitor charging to realize, width is changed, and detects the phase difference of triggering signal and counting clock, after counting, while utilizing again capacitor discharge to realize width, changes, and output pulse is carried out to time delay, thereby phase difference is compensated, and reduces trigger error.But this method requires the stray inductance of charge and discharge capacitance very little, and require insensitive to variations in temperature, also need to build simultaneously consistency very high discharge and recharge constant-current source and other phase-detection and phase compensating circuit, circuit complexity, and power consumption is higher.
Summary of the invention
The object of the invention is to overcome in prior art and build and discharge and recharge constant-current source, phase-detection, phase compensating circuit challenge, kind of a kind of digital delay synchronous motor and a time-delay method based on clock phase-splitting technology is provided, make the delay compensation of Lag synchronization machine comparatively accurate, build circuit simple and reliable, low in energy consumption.
For achieving the above object, the technical solution used in the present invention is:
A kind of digital delay synchronous motor based on clock phase-splitting technology, comprise the clock phase-splitting circuit module for realizing N level clock phase-splitting, also comprise: the count delay circuit module that completes counting and data comparison, in the time that count delay circuit module receives triggering signal, count delay circuit module starts to start counter, if the delayed data that touch-screen is set is D, pulse width data is W, in the time that counter data is less than D, this module output low level; When counter data is greater than D, and while being less than D+W, this module output high level; In the time that counter data is greater than D+W, this module output low level, wherein D is delayed data, and W is pulse width data, and wherein D is the delayed data that touch-screen is set, and W is the pulse width data that touch-screen is set; OR circuit module, detects the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, is the time delay output signal of trigger error minimum, as the last output of this triggering signal; Is set, the human-computer interactive control module of output pulse width the trigger delay time; Wherein, clock phase-splitting circuit module, count delay circuit module, the electrical connection of OR circuit sequence of modules, human-computer interactive control module is electrically connected with count delay circuit module.
Described count delay circuit module triggering signal input is as delay synchronizer input, and described OR circuit module output is as delay synchronizer time delayed signal output.
The described digital delay synchronous motor based on clock phase-splitting technology has multiple signals input, multiple signals output.
The described digital delay synchronous motor based on clock phase-splitting technology also comprises the communication interface circuit module for connecting human-computer interactive control module and the communication of count delay circuit module.
A kind of digital delay synchronous method based on clock phase-splitting technology, making the cycle is the clock of T, utilize clock phase-splitting technology, produce N the clock that phase place incremental change is T/N, it is characterized in that adopting N clock of clock phase-splitting circuit module to be input to count delay circuit module, in the time that count delay circuit module receives triggering signal, count delay circuit module starts to start counter simultaneously, in the time that counter data is less than the trigger delay time, this module output low level; When counter data is greater than the trigger delay time, and while being less than trigger delay time and output pulse width sum, this module output high level; In the time that counter data is greater than trigger delay time and output pulse width sum, this module output low level; Then adopt OR circuit to detect the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, be time delay output signal; The trigger error of the count delay output signal of time delay output signal is T/N, and described count delay circuit module completes counting and data comparing function, comprises that 3 tunnel input letters obtain the time delayed signal of trigger error minimum.
Can find out from the architectural feature of the invention described above, its advantage is:
(1) effectively reduce the trigger error of delay synchronizer.
(2) circuit is simple and reliable, low in energy consumption.
Brief description of the drawings
The present invention will illustrate by way of compared with accompanying drawings and combined with example:
Fig. 1 is system principle diagram of the present invention;
Fig. 2 is the structured flowchart of level Four clock phase-splitting single channel data processing in FPGA of the present invention;
Fig. 3 is the circuit design of level Four clock phase-splitting single channel data processing in FPGA of the present invention;
Fig. 3 (a) is clock phase-splitting circuit module circuit design;
Fig. 3 (b) is count delay circuit module and OR circuit Modular circuit design;
FPGA working timing figure when Fig. 4 is level Four clock phase-splitting single channel data processing of the present invention;
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
System principle is analyzed: the present invention adopts clock phase-splitting technology, utilizes VHDL language and schematic diagram hybrid programming to design the precision digital delay synchronizer design based on clock phase-splitting technology by FPGA (field programmable gate array).In the design, utilize low frequency, high-precision crystal oscillator as clock source, by a phase-locked loop (PLL), obtain a high stable through this low-frequency clock, point phase clock of low jitter.Utilize multistage point of phase clock to make the clock that the cycle is T pass through a series of delay units, produce N the clock that phase place incremental change is T/N, form clock phase-splitting circuit, the N of a clock phase-splitting circuit module clock is input to count delay circuit module simultaneously, in the time that count delay circuit module receives triggering signal, count delay circuit module starts to start counter, in the time that counter data is less than the trigger delay time, and this module output low level; When counter data is greater than the trigger delay time, and while being less than trigger delay time and output pulse width sum, this module output high level; In the time that counter data is greater than trigger delay time and output pulse width sum, this module output low level.Then adopt OR circuit to detect the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, be time delay output signal.The trigger error of the count delay output signal of time delay output signal is T/N.This has just reduced instrument trigger error N doubly under the condition that does not improve clock frequency.
Overall system design: system principle diagram as of the present invention in Fig. 1.System is by comprising clock phase-splitting circuit module, count delay circuit module, OR circuit module, communication interface module, human-computer interactive control module.Digital delay synchronous motor is mainly to utilize VHDL language and schematic diagram hybrid programming to carry out the design of hardware module by FPGA (field programmable gate array), has designed clock phase-splitting circuit module, count delay circuit module, OR circuit module, communication interface module.If Fig. 2 is the structured flowchart of level Four clock phase-splitting single channel data processing in FPGA.The trigger delay time of human-computer interaction interface and output pulse width parameter arrange, to be input in count delay circuit by parameter input port, triggering signal is input in count delay circuit module by triggering input signal port, clock phase-splitting circuit module has utilized clock phase-splitting technology exactly, forms 4 fraction phase clocks.0 phase difference counting delay circuit module, T/4 phase difference counting delay circuit module, T/2 phase difference counting delay circuit module, 3T/4 phase difference counting delay circuit module complete respectively counting and data comparison, and output delay signal.OR circuit module detects and obtains the inhibit signal of phase difference minimum and as final time delay output signal.
Modules composition and Functional Design
1. input, output signal, and the selection of parameter design
In system, the voltage of input, output signal is Transistor-Transistor Logic level, and pulse duration requires as 100ns～1000ns; Pulse duration is 100ns～500ns; The design objective of system is that delay scope is 100ns～1s, postpones output Transistor-Transistor Logic level, time delay output width 100～300ns, trigger error 5ns, postpones stepping 1ns.
The maximum operating frequency that in the present invention, FPGA is stable is that 200M～450M. optimum value is generally elected 250M as, and the trigger error that such 4 clock phase-splittings obtain is 1ns.
Digital delay synchronous motor based on clock phase-splitting technology can be processed multiple signals simultaneously, has multichannel input, multiple output function.
2. human-computer interactive control module
Human-computer interactive control module is mainly used in the delay stepping of the system that arranges, comprise time delay and pulse duration, the upper data that arrange of upper computer control module (touch-screen) are through PLC interface, according to the disposable data buffer storage that reads in time delay synchronization control module of 485 agreements, retardation is stepping amount, and pulse duration is output signal high level width.
3. clock phase-splitting circuit module
Utilize clock phase-splitting circuit, can form N level phase splitter, but in the design, utilize 4 grades of phase splitters just can complete design.So-called clock phase-splitting technology, is all used multiple phase places of clock cycle exactly, to reach higher temporal resolution.In conventionally designing, only use the rising edge (0 phase place) of clock, if the trailing edge of clock (180 ° of phase places) is also used, the time resolution of system just can double.In like manner, clock is divided into 4 phase places (0 °, 90 °, 180 ° and 270 °), the time resolution of system just can rise to original 4 times.
4. count delay circuit module
Count delay circuit module completes counting and data comparing function, comprise 3 road input signals, the triggering signal, the phase-splitting clock circuit of clock phase-splitting circuit input, the host computer that are respectively system input are input to the data-signal in counting delay circuit module by PLC interface by the amount of delay of setting and data pulse; Output signal is after tachnical delay circuit module, the time delayed signal of the trigger error minimum obtaining.
5. OR circuit module
Utilize the OR circuit of VHDL language design by FPGA, detect the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, be time delay output signal.
6. power supply and communication interface module
In FPGA hardware circuit design, signal with counting delay circuit module by BNC or SMA Interface realization be connected, upper microcomputer control module (touch-screen) with count delay circuit module be connected by PLC Interface realization.System provides the power module of normal power supply for FPGA carries out hardware circuit design, host computer circuit design etc.The 24V power supply that wherein host computer needs is changed by a 12W Switching Power Supply by 220V civil power; The 5V power supply that all the other modules need is changed by a 10W Switching Power Supply by 220V civil power; 3.3V and 1.2V power supply that FPGA needs are realized by a slice TPS70445 power conversion chip by this 5V power supply.
Specific design process: the circuit design while being level Four clock phase-splitting single channel data processing as Fig. 3 in FPGA.Fig. 3 (a) is clock phase-splitting circuit module circuit design.In the parameter list of the embedded phase-locked loop altpll of FPGA, Ratio is the multiple of clock multiplier, be made as 10, Ph (dg) is the phase place that corresponding output clock postpones with respect to input clock, be made as respectively 0 °, 90 °, 180 ° and 270 °, DC is the duty ratio of low and high level in output clock one-period, be made as 50%, like this, clock signal inclk1 (25MHz) by the outer high stability crystal oscillator input of sheet is 250MHz signal through phase-locked loop altpll frequency multiplication, after level Four postpones, in output one-period, low and high level duty ratio is 1:1 ratio, phase difference is 0 with respect to inclk1, T/4, the clk1 of T/2 and 3T/4 phase count delayed clock, clk2, clk3 and clk4, form clock phase-splitting circuit module.Fig. 3 (b) is count delay circuit module and OR circuit Modular circuit design.The N of a clock phase-splitting circuit module clock is input to count delay circuit module (delayControl module) simultaneously, in the time that count delay circuit module (delayControl module) receives triggering signal (triger signal), count delay circuit module (delayControl module) starts to start counter, if the delayed data that touch-screen is set is D, pulse width data is W, in the time that counter data is less than D, this module output low level; When counter data is greater than D, and while being less than D+W, this module output high level; In the time that counter data is greater than D+W, this module output low level.Then adopt four OR circuit (OR circuit) to detect the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, be the time delay output signal (output output signal) of trigger error minimum, as the last output of this triggering signal.
FPGA working timing figure when Fig. 4 is level Four clock phase-splitting single channel data processing.The trigger error of the count delay output signal of time delay output signal is T/N.If only utilize inclk1 clock directly to count time delay, trigger error is exactly the phase difference t1 of triggering signal (tirger signal) and counting clock inclk1, and its maximum equals the cycle T of counting clock.Adopt after clock phase-splitting, because the clock that in figure, rising edge arrives at first after triggering signal is clk3, so adopt clk3 counting time delay trigger error minimum, this trigger error represents with Δ t2, and its maximum equals the differential T/4 of point phase clock.Obviously the time delay control module output that rising edge clock arrives corresponding at first also arrives at first, adopts one four or a signal that this can be arrived at first to find out, and is exactly the time delay result of trigger error minimum.Four or door output signal (output output signal) trigger error reduced by 4 times with respect to the trigger error of direct count delay.
In this specification, disclosed all features, except mutually exclusive feature, all can be combined in any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.
Claims (4)
1. the digital delay synchronous motor based on clock phase-splitting technology, comprises the clock phase-splitting circuit module for realizing N level clock phase-splitting, characterized by further comprising:
The trigger delay time is set, the human-computer interactive control module of output pulse width, described human-computer interactive control module is touch-screen;
Complete the count delay circuit module of counting and data comparison, in the time that count delay circuit module receives triggering signal, count delay circuit module starts to start counter, if the delayed data that touch-screen is set is D, pulse width data is W, in the time that counter data is less than D, this module output low level; When counter data is greater than D, and while being less than D+W, this module output high level; In the time that counter data is greater than D+W, this module output low level;
OR circuit module, detects the triggering signal output pulse of triggering signal and clock phase-splitting module phase difference minimum, is the time delay output signal of trigger error minimum, as the last output of this triggering signal; The trigger error of the count delay output signal of time delay output signal is T/N, and described T is the clock cycle, and described N is positive integer;
Wherein, clock phase-splitting circuit module, count delay circuit module, the electrical connection of OR circuit sequence of modules, human-computer interactive control module is electrically connected with count delay circuit module.
2. a kind of digital delay synchronous motor based on clock phase-splitting technology according to claim 1, it is characterized in that described count delay circuit module triggering signal input is as delay synchronizer input, described OR circuit module output is as delay synchronizer time delayed signal output.
3. a kind of digital delay synchronous motor based on clock phase-splitting technology according to claim 1, is characterized in that the described digital delay synchronous motor based on clock phase-splitting technology has multiple signals input, multiple signals output.
4. a kind of digital delay synchronous motor based on clock phase-splitting technology according to claim 1, is characterized in that described delay synchronizer also comprises the communication interface circuit module for connecting human-computer interactive control module and the communication of count delay circuit module.
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| CN103701436B (en) * | 2012-09-27 | 2016-01-13 | 浙江大华技术股份有限公司 | A kind of generation method of outer synchronous triggering signal and the equipment of generation |
| CN103731136B (en) * | 2014-01-02 | 2017-05-24 | 西北核技术研究所 | Sequential equivalent sampling circuit and method based on delay signals |
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
| CN106656121A (en) * | 2016-11-30 | 2017-05-10 | 吉林大学 | Sub-nanosecond digital delay pulse generating device and operating method thereof |
| CN108599743A (en) * | 2018-05-11 | 2018-09-28 | 中国工程物理研究院流体物理研究所 | A kind of precision digital delay synchronous method based on phase compensation |
| CN108732912A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of measured signal edging trigger |
| CN109032023B (en) * | 2018-08-08 | 2021-03-09 | 上海精密计量测试研究所 | Built-in self-test method for DCM and PLL in FPGA |
| CN110492987B (en) * | 2019-09-11 | 2023-06-16 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Precision time prediction synchronous electronic system |
| CN110955179B (en) * | 2019-11-28 | 2022-09-06 | 电子科技大学 | Dual-channel shared clock trigger delay adjusting device based on PCI bus |
| CN113126527B (en) * | 2019-12-30 | 2022-07-26 | 国仪量子(合肥)技术有限公司 | Quantum measurement and control system |
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