CN102035512A - Clock phase-splitting technology-based precise digital time delay synchronous machine and time delay method - Google Patents
Clock phase-splitting technology-based precise digital time delay synchronous machine and time delay method Download PDFInfo
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Abstract
The invention relates to a digital time delay synchronous machine and a time delay method, in particular to a clock phase-splitting technology-based precise digital time delay synchronous machine and a time delay method. In order to solve the problems on complexity in setting up a charge-discharge constant-current source and a phase detection and phase compensation circuit in the prior art, the invention provides a precise digital time delay synchronous machine based on a clock phase-splitting technology, which ensures that precise time delay compensation of the time delay synchronous machine is achieved, and circuit setting-up is simple and reliable and is low in power consumption. In the technical scheme, the precise digital time delay synchronous machine comprises a front-end signal conditioning module, a delay synchronous control module, a signal driving module and an upper computer control module, and the delay synchronous control module comprises a clock phase-splitting circuit module, a counting delay circuit for accomplishing counting and data comparison and a communication interface module. Before synchronous signals enter each path, the digital time delay synchronous machine is applied to carry out predelay to compensate the nonuniformity of each path of system so that the output of each system is in an occasion of the synchronous signals.
Description
Technical field
The present invention relates to a kind of digital delay synchronous motor and time-delay method, particularly relate to a kind of precision digital delay synchronizer and time-delay method based on clock phase-splitting technology.
Technical background
In the physical test of multiloop loop system, usually require the signal of each road system to arrive certain circuit node simultaneously, but because circuit element that each system adopted and mounting process can not be in full accord, so one group of synchronizing signal has just become nonsynchronous signal through after the delay of each road system, this just needs a kind of instrument to do delay in advance before synchronizing signal enters each road, to compensate the nonuniformity of each road system, make each road system be output as synchronizing signal, delay synchronizer that Here it is.Trigger error, time-delay stepping and reference time delay are the important technology indexs of delay synchronizer.
Delivered and be entitled as " based on the impulsive synchronization machine development of precision delay technology " " nuclear electronics and Detection Techniques " in November, 2006 and adopted analoging interpolation technology, promptly big time delay adopts digital, postpones to adopt the analog variation formula between hour.The width of cloth is changed when utilizing the electric capacity charging to realize, detects the phase difference of triggering signal and counting clock, after counting finishes, changes when utilizing capacitor discharge to realize the width of cloth again, the output pulse is delayed time, thereby phase difference is compensated, and reduces trigger error.But this method requires the stray inductance of charge and discharge capacitance very little, and require insensitive to variations in temperature, also need simultaneously to build consistency very high discharge and recharge constant-current source and other phase-detection and phase compensating circuit, circuit complexity, and power consumption is higher.
Summary of the invention
The objective of the invention is to overcome to build in the prior art and discharge and recharge constant-current source, phase-detection, phase compensating circuit challenge, kind of a kind of a precision digital delay synchronizer and a time-delay method based on clock phase-splitting technology are provided, make and postpone comparatively precision of synchronous motor delay compensation, it is simple and reliable to build circuit, low in energy consumption.
For achieving the above object, the technical solution used in the present invention is:
A kind of precision digital delay synchronizer based on clock phase-splitting technology comprises the clock phase splitter module that is used to realize the phase-splitting of N level clock, also comprises: finish counting and data count delay circuit module relatively; The OR circuit module; Is set, the human-computer interactive control module of output pulse width the trigger delay time; Wherein, clock phase splitter module, count delay circuit module, OR circuit sequence of modules are electrically connected, and the human-computer interactive control module is electrically connected with the count delay circuit module.
Described count delay circuit module triggering signal input is as the delay synchronizer input, and described OR circuit module output is as delay synchronizer time delayed signal output.
Described precision digital delay synchronizer based on clock phase-splitting technology has the multiple signals input, the multiple signals output.
Described delay synchronizer also comprises the communication interface circuit module that is used to connect human-computer interactive control module and the communication of count delay circuit module.
A kind of precision digital delay synchronizer based on clock phase-splitting technology, making the cycle is the clock of T, utilize clock phase-splitting technology, producing the phase place incremental change is N the clock of T/N, be clock phase splitter module, N the clock that it is characterized in that clock phase splitter module is input to the count delay circuit module simultaneously, when the count delay circuit module receives triggering signal, the count delay circuit module begins the enabling counting device, when counter data less than trigger delay during the time, this module output low level; When counter data greater than the trigger delay time, and during less than trigger delay time and output pulse width sum, this module output high level; When counter data during greater than trigger delay time and output pulse width sum, this module output low level.Adopt OR circuit detection triggering signal and clock to divide the triggering signal output pulse of phase module phase difference minimum then, be the time-delay output signal.The trigger error of the count delay output signal of time-delay output signal then is T/N.
From the architectural feature of the invention described above as can be seen, its advantage is:
(1) effectively reduce the trigger error of delay synchronizer.
(2) circuit is simple and reliable, and is low in energy consumption.
Description of drawings
The present invention will illustrate by way of compared with accompanying drawings and combined with example:
Fig. 1 is a system principle diagram of the present invention;
Fig. 2 is the structured flowchart of level Four clock phase-splitting single channel data processing among the FPGA of the present invention;
Fig. 3 (a) is the clock phase splitter modular circuit design of the circuit of level Four clock phase-splitting single channel data processing among the FPGA of the present invention;
Fig. 3 (b) is the count delay circuit module and the design of OR circuit modular circuit of the circuit of level Four clock phase-splitting single channel data processing among the FPGA of the present invention;
FPGA working timing figure when Fig. 4 is a level Four clock phase-splitting single channel data processing of the present invention;
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
System principle is analyzed: the present invention adopts clock phase-splitting technology, and the precision digital delay synchronizer of utilizing VHDL language and the design of schematic diagram hybrid programming to finish based on clock phase-splitting technology by FPGA (field programmable gate array) designs.Among the design, utilize low frequency, high-precision crystal oscillator, by a phase-locked loop (PLL), obtain a high stable, the branch phase clock of low jitter through this low-frequency clock as the clock source.Utilize multistage minute phase clock make the cycle for the clock of T by a series of delay units, producing the phase place incremental change is N the clock of T/N, form the clock phase splitter, N clock of clock phase splitter module is input to the count delay circuit module simultaneously, when the count delay circuit module receives triggering signal, the count delay circuit module begins the enabling counting device, when counter data less than trigger delay during the time, this module output low level; When counter data greater than the trigger delay time, and during less than trigger delay time and output pulse width sum, this module output high level; When counter data during greater than trigger delay time and output pulse width sum, this module output low level.Adopt OR circuit detection triggering signal and clock to divide the triggering signal output pulse of phase module phase difference minimum then, be the time-delay output signal.The trigger error of the count delay output signal of time-delay output signal then is T/N.This has just reduced N doubly with the instrument trigger error under the condition that does not improve clock frequency.
Overall system design: as Fig. 1 system principle diagram of the present invention.System is by comprising clock phase splitter module, count delay circuit module, OR circuit module, communication interface module, human-computer interactive control module.The precision digital delay synchronizer mainly is to utilize VHDL language and schematic diagram hybrid programming to carry out the design of hardware module by FPGA (field programmable gate array), has designed clock phase splitter module, count delay circuit module, OR circuit module, communication interface module.As Fig. 2 is the structured flowchart of level Four clock phase-splitting single channel data processing among the FPGA.The trigger delay time of human-computer interaction interface and output pulse width parameter are provided with, be to be input in the count delay circuit by the parameter input port, triggering signal is input in the count delay circuit module by triggering the input signal port, clock phase splitter module has been utilized clock phase-splitting technology exactly, forms 4 fraction phase clocks.0 phase difference counting delay circuit module, T/4 phase difference counting delay circuit module, T/2 phase difference counting delay circuit module, 3T/4 phase difference counting delay circuit module are finished counting and data respectively relatively, and the output delay signal.The OR circuit module detects obtains the inhibit signal of phase difference minimum and as final time-delay output signal.
Each module is formed and the function design
1. input, output signal, and the selection of parameter design
The voltage of input, output signal is Transistor-Transistor Logic level in the system, and pulse duration requires to be 100ns～1000ns; Pulse duration is 100ns～500ns; The design objective of system is 100ns～1s, postpones output Transistor-Transistor Logic level, time-delay output width 100～300ns, trigger error 5ns, postpones stepping 1ns. for the delay scope
The maximum operating frequency that FPGA is stable among the present invention is that 200M～450M. optimum value is generally elected 250M as, and the trigger error that such 4 clock phase-splittings obtain is 1ns.
Precision digital delay synchronizer based on clock phase-splitting technology can be handled multiple signals simultaneously, has the multichannel input, multiple output function.
2. human-computer interactive control module
The human-computer interactive control module is mainly used in the delay stepping of the system of setting, comprise time delay and pulse duration, upper computer control module (touch-screen) goes up the data process PLC interface that is provided with, according to the disposable metadata cache that reads in the time-delay synchronization control module of 485 agreements, retardation is the stepping amount, and pulse duration is an output signal high level width.
3. clock phase splitter module
Utilize the clock phase splitter, can form N level phase splitter, but among the design, utilize 4 grades of phase splitters just can finish design.So-called clock phase-splitting technology all is used a plurality of phase places of clock cycle exactly, to reach higher temporal resolution.In designing usually, only use the rising edge (0 phase place) of clock, if the trailing edge of clock (180 ° of phase places) also is used, the time resolution of system just can double.In like manner, clock is divided into 4 phase places (0 °, 90 °, 180 ° and 270 °), the time resolution of system just can rise to original 4 times.
4. count delay circuit module
The count delay circuit module is finished counting and data comparing function, comprise 3 road input signals, the triggering signal, the phase-splitting clock circuit of clock phase splitter input, the host computer that are respectively system's input are input to the data-signal of counting in the delay circuit module by the PLC interface with amount of delay and the data pulse of setting; Output signal is through behind the tachnical delay circuit module, the time delayed signal of the trigger error minimum that obtains.
5. OR circuit module
By the OR circuit that FPGA utilizes VHDL language to design, detect the triggering signal output pulse that triggering signal and clock divide phase module phase difference minimum, be the time-delay output signal.
6. power supply and communication interface module
In the FPGA hardware circuit design, signal is realized being connected, is gone up system controlled by computer module (touch-screen) with counting delay circuit module by BNC or SMA interface and realizes being connected by the PLC interface with counting delay circuit module.System carries out the power module that hardware circuit design, host computer circuit design etc. provide normal power supply for FPGA.Wherein the 24V power supply of host computer needs is changed by a 12W Switching Power Supply by the 220V civil power; The 5V power supply that all the other modules need is changed by a 10W Switching Power Supply by the 220V civil power; 3.3V that FPGA needs and 1.2V power supply are realized by a slice TPS70445 power conversion chip by this 5V power supply.
Specific design process: shown in Fig. 3 (a), in the parameter list of the embedded phase-locked loop altpll of FPGA, Ratio is the multiple of clock multiplier, be made as 10, Ph (dg) is the phase place that corresponding output clock postpones with respect to input clock, be made as 0 ° respectively, 90 °, 180 ° and 270 °, DC is the duty ratio of high-low level in the output clock one-period, be made as 50%, like this, the clock signal inclk1 (25MHz) that is imported by the outer high stability crystal oscillator of sheet is the 250MHz signal through phase-locked loop altpll frequency multiplication, after level Four postpones, the high-low level duty ratio is 1: 1 ratio in the output one-period, and phase difference is 0 with respect to inclk1, T/4, the clk1 of T/2 and 3T/4 phase count delayed clock, clk2, clk3 and clk4 form clock phase splitter module.Shown in Fig. 3 (b), N clock of clock phase splitter module is input to count delay circuit module (delayControl module) simultaneously, when count delay circuit module (delayControl module) receives triggering signal (triger signal), count delay circuit module (delayControl module) beginning enabling counting device, if the delayed data that touch-screen is set is D, pulse width data is W, when counter data during less than D, and this module output low level; When counter data greater than D, and during less than D+W, this module output high level; When counter data during greater than D+W, this module output low level.Adopt four OR circuit (OR circuit) detection triggering signal and clock to divide the triggering signal of phase module phase difference minimum to export pulse then, be the time-delay output signal (output output signal) of trigger error minimum, as the last output of this triggering signal.
FPGA working timing figure when Fig. 4 is level Four clock phase-splitting single channel data processing.The trigger error of the count delay output signal of time-delay output signal then is T/N.If only utilize the time-delay of inclk1 clock direct count, trigger error is exactly the phase difference t1 of triggering signal (tirger signal) and counting clock inclk1, and its maximum equals the period T of counting clock.After adopting the clock phase-splitting, because the clock that rising edge arrives at first after triggering signal among the figure is clk3, so adopt clk3 counting time-delay trigger error minimum, this trigger error represents that with Δ t2 its maximum equals the differential T/4 of branch phase clock.Obviously rising edge clock arrives the output of time-delay control module at first corresponding and also arrives at first, adopts one four or a signal that this can be arrived at first to find out, and is exactly the time-delay result of trigger error minimum.Four or the trigger error of door output signal (output output signal) reduced by 4 times with respect to the trigger error that direct count postpones.
Disclosed all features except mutually exclusive feature, all can be combined in any way in this specification.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
Claims (5)
1. the precision digital delay synchronizer based on clock phase-splitting technology comprises the clock phase splitter module that is used to realize the phase-splitting of N level clock, it is characterized in that also comprising:
Finish counting and data count delay circuit module relatively;
The OR circuit module;
Is set, the human-computer interactive control module of output pulse width the trigger delay time;
Wherein, clock phase splitter module, count delay circuit module, OR circuit sequence of modules are electrically connected, and the human-computer interactive control module is electrically connected with the count delay circuit module.
2. a kind of precision digital delay synchronizer according to claim 1 based on clock phase-splitting technology, it is characterized in that described count delay circuit module triggering signal input as the delay synchronizer input, described OR circuit module output is as delay synchronizer time delayed signal output.
3. a kind of precision digital delay synchronizer based on clock phase-splitting technology according to claim 1 is characterized in that described precision digital delay synchronizer based on clock phase-splitting technology has the multiple signals input, the multiple signals output.
4. a kind of precision digital delay synchronizer based on clock phase-splitting technology according to claim 1 is characterized in that described delay synchronizer also comprises the communication interface circuit module that is used to connect human-computer interactive control module and the communication of count delay circuit module.
5. one kind based on the precision digital of clock phase-splitting technology time-delay method for synchronous, making the cycle is the clock of T, utilize clock phase-splitting technology, producing the phase place incremental change is N the clock of T/N, it is characterized in that adopting N clock of clock phase splitter module to be input to the count delay circuit module simultaneously, when the count delay circuit module received triggering signal, the count delay circuit module began the enabling counting device, when counter data less than trigger delay during the time, this module output low level; When counter data greater than the trigger delay time, and during less than trigger delay time and output pulse width sum, this module output high level; When counter data during greater than trigger delay time and output pulse width sum, this module output low level; Adopt OR circuit detection triggering signal and clock to divide the triggering signal output pulse of phase module phase difference minimum then, be the time-delay output signal; The trigger error of the count delay output signal of time-delay output signal then is T/N.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103701436A (en) * | 2012-09-27 | 2014-04-02 | 浙江大华技术股份有限公司 | External synchronous trigger signal generating method and equipment |
| CN103731136A (en) * | 2014-01-02 | 2014-04-16 | 西北核技术研究所 | Sequential equivalent sampling circuit and method based on delay signals |
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
| CN106656121A (en) * | 2016-11-30 | 2017-05-10 | 吉林大学 | Sub-nanosecond digital delay pulse generating device and operating method thereof |
| CN108599743A (en) * | 2018-05-11 | 2018-09-28 | 中国工程物理研究院流体物理研究所 | A kind of precision digital delay synchronous method based on phase compensation |
| CN108732912A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of measured signal edging trigger |
| CN109032023A (en) * | 2018-08-08 | 2018-12-18 | 上海精密计量测试研究所 | A kind of built-in self-test method of FPGA internal DC M, PLL |
| CN110492987A (en) * | 2019-09-11 | 2019-11-22 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Chronometer time predicts synchronous electronic system |
| CN110955179A (en) * | 2019-11-28 | 2020-04-03 | 电子科技大学 | Dual-channel shared clock trigger delay adjusting device based on PCI bus |
| CN113126527A (en) * | 2019-12-30 | 2021-07-16 | 国仪量子(合肥)技术有限公司 | Quantum measurement and control system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2660787Y (en) * | 2003-10-15 | 2004-12-01 | 中国电子科技集团公司第四十一研究所 | Precision delayer |
| CN1881797A (en) * | 2005-06-14 | 2006-12-20 | 三星电子株式会社 | Synchronization circuits and methods |
| CN201918968U (en) * | 2010-11-19 | 2011-08-03 | 中国工程物理研究院流体物理研究所 | Precision digital delay synchronizer based on clock phase-splitting technology |
-
2010
- 2010-11-19 CN CN201010552082.2A patent/CN102035512B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2660787Y (en) * | 2003-10-15 | 2004-12-01 | 中国电子科技集团公司第四十一研究所 | Precision delayer |
| CN1881797A (en) * | 2005-06-14 | 2006-12-20 | 三星电子株式会社 | Synchronization circuits and methods |
| CN201918968U (en) * | 2010-11-19 | 2011-08-03 | 中国工程物理研究院流体物理研究所 | Precision digital delay synchronizer based on clock phase-splitting technology |
Non-Patent Citations (2)
| Title |
|---|
| 彭能岭 等: "惯性约束聚变实验中全程控终端同步机的研制", 《核技术》, vol. 30, no. 1, 31 January 2007 (2007-01-31), pages 71 - 72 * |
| 高辉 等: "可编程器件在纳秒级多通道数字延迟/脉冲发生器中的应用", 《分析仪器》, no. 3, 31 December 2002 (2002-12-31) * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103701436A (en) * | 2012-09-27 | 2014-04-02 | 浙江大华技术股份有限公司 | External synchronous trigger signal generating method and equipment |
| CN103701436B (en) * | 2012-09-27 | 2016-01-13 | 浙江大华技术股份有限公司 | A kind of generation method of outer synchronous triggering signal and the equipment of generation |
| CN103731136A (en) * | 2014-01-02 | 2014-04-16 | 西北核技术研究所 | Sequential equivalent sampling circuit and method based on delay signals |
| CN103731136B (en) * | 2014-01-02 | 2017-05-24 | 西北核技术研究所 | Sequential equivalent sampling circuit and method based on delay signals |
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
| CN106656121A (en) * | 2016-11-30 | 2017-05-10 | 吉林大学 | Sub-nanosecond digital delay pulse generating device and operating method thereof |
| CN108599743A (en) * | 2018-05-11 | 2018-09-28 | 中国工程物理研究院流体物理研究所 | A kind of precision digital delay synchronous method based on phase compensation |
| CN108732912A (en) * | 2018-05-28 | 2018-11-02 | 哈尔滨工业大学 | The clock phase-splitting method of measured signal edging trigger |
| CN109032023A (en) * | 2018-08-08 | 2018-12-18 | 上海精密计量测试研究所 | A kind of built-in self-test method of FPGA internal DC M, PLL |
| CN110492987A (en) * | 2019-09-11 | 2019-11-22 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Chronometer time predicts synchronous electronic system |
| CN110492987B (en) * | 2019-09-11 | 2023-06-16 | 吉林省广播电视研究所(吉林省广播电视局科技信息中心) | Precision time prediction synchronous electronic system |
| CN110955179A (en) * | 2019-11-28 | 2020-04-03 | 电子科技大学 | Dual-channel shared clock trigger delay adjusting device based on PCI bus |
| CN110955179B (en) * | 2019-11-28 | 2022-09-06 | 电子科技大学 | Dual-channel shared clock trigger delay adjusting device based on PCI bus |
| CN113126527A (en) * | 2019-12-30 | 2021-07-16 | 国仪量子(合肥)技术有限公司 | Quantum measurement and control system |
| CN113126527B (en) * | 2019-12-30 | 2022-07-26 | 国仪量子(合肥)技术有限公司 | Quantum measurement and control system |
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