CN110492987B - Precision time prediction synchronous electronic system - Google Patents
Precision time prediction synchronous electronic system Download PDFInfo
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- CN110492987B CN110492987B CN201910857260.3A CN201910857260A CN110492987B CN 110492987 B CN110492987 B CN 110492987B CN 201910857260 A CN201910857260 A CN 201910857260A CN 110492987 B CN110492987 B CN 110492987B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
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Abstract
The invention provides a precise time prediction synchronization electronic system, relates to the field of electronic control technology and broadcast television, solves the problem that the existing prediction synchronization system cannot realize real synchronization, and provides the precise time prediction synchronization electronic system. I.e. it is not necessary to measure how long the actual cable is, nor how much the signal delay time is. The various subsystems being synchronized are independent of each other, and no change to any single subsystem is necessary to adjust the other subsystems. Either a synchronization signal with no delay or no phase difference from the synchronization source can be generated or a synchronization signal with a fixed amount of lead or lag from the source can be generated. The invention adopts the mode of equal amount compensation of advance and delay to realize that the synchronized system and the original synchronous signal are accurately synchronized without delay; no adjustment is required in practical applications.
Description
Technical Field
The invention relates to the field of electronic control technology and broadcast television, and the device predicts that the synchronous signal reproduced by the device is synchronous with the original signal and does not delay due to long-distance transmission.
Background
Systems such as radio positioning, navigation and broadcast television synchronous transmission all need uniform time synchronization, and a large system needs to uniformly synchronize a plurality of subsystems by using one synchronization signal. In most cases, 1PPS pulse signals from the beidou, GPS or atomic clocks are used. In a cable, the speed of the electromagnetic wave is about 2/3 of the speed of vacuum light, that is to say, the synchronization signal has a significant delay of about 1 microsecond for every 200 meters of cable length increase. Because the synchronous source is different from the line length of each subsystem, the same synchronous signal has time difference when reaching each subsystem and cannot be truly synchronized. Since the vacuum light velocity is the cosmic limit velocity, the propagation velocity of the synchronization information is also unlikely to exceed the light velocity. In order to achieve synchronization of all subsystems, a time delay method is adopted currently. Because the synchronization signal arrives earlier for systems closer to the source, it is delayed to synchronize with other systems further away. In engineering implementations, it is necessary to measure the delay value of the furthest subsystem and then delay the signals of the other subsystems with a delay. If a new subsystem is added, adjustments must be made. Because the proximity is already occupied by the original subsystem, the new subsystem is often the furthest subsystem. The furthest delay change of the whole system has to adjust the delays of all subsystems.
Disclosure of Invention
The invention provides a precise time prediction synchronization electronic system, which aims to solve the problem that the existing prediction synchronization system can not realize real synchronization.
The precise time prediction synchronous electronic system comprises a synchronous information source input end, a first equal-length cable, a second equal-length cable, a third equal-length cable, a synchronous signal output end, an information source end circuit and a receiving end circuit;
the synchronous signal source input end is connected with the input end of the signal source end circuit, the output end A of the signal source end circuit is connected with the input end A of the receiving end circuit through a first equal-length cable, the input end B of the signal source end circuit is connected with the output end B of the receiving end circuit through a second equal-length cable, the output end C of the signal source end circuit is connected with the input end C of the receiving end circuit through a third equal-length cable, and the output end OUT of the receiving end circuit is connected with the synchronous signal output end;
setting an advance half-ratio phase-locked circuit in the information source end circuit, predicting and generating a synchronous signal with the advance time of T through the advance half-ratio phase-locked circuit, transmitting the synchronous signal to a receiving end circuit through a first equal-length cable for delaying the synchronous signal by T time, and obtaining a synchronous signal which has no delay with an original synchronous signal PX at an OUT output end of the receiving end circuit; the implementation process is as follows:
the original synchronous signal PX input by the synchronous signal source input end is changed into an output signal PA0 through an A output end of the signal source end circuit, the output signal PA0 is transmitted to an A input end of the receiving end circuit through a first equal-length cable and is changed into an input signal PA1, the delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is output a signal PB0 through a B output end of the receiving end circuit, the output signal PB0 is fed back to a B input end of the signal source end circuit through a second equal-length cable and is changed into an input signal PB1, and the delay between the input signal PB1 and the original synchronous signal PX is 2T;
the advanced half-ratio phase-locked circuit predicts and generates an output signal PC0 with an advanced time of T compared with the original synchronous signal PX by utilizing the original synchronous signal PX and an input signal PB1 with a delay of 2T, the advanced synchronous signal PC0 is output from the C output end of the source end circuit and is transmitted to the C input end of the receiving end circuit through a third equal-length cable to become the input signal PC1, the delay between the input signal PC1 and the output signal PC0 is T, and the receiving end circuit obtains the input signal PC1 which has no delay with the original synchronous signal PX;
the advanced half-ratio phase-locked circuit comprises an input end INA, an input end INB, an output end, a clock input end, a first D trigger, a second D trigger, a fourth D trigger, a first AND gate, a second AND gate, a third AND gate, an NOT gate, a first data latch, a second data latch, a third data latch, a reversible counter, a subtracter, a first comparator, a second comparator, a first OR gate, a second OR gate, a first T trigger and a second T trigger;
the input end INA is connected with the C input end of the first D trigger, the input end INB is connected with the C input end of the fourth D trigger, and the clock input end is respectively connected with the CLK input end of the reversible counter, the C input end of the second T trigger, the CP input end of the counter and the C input end of the first T trigger;
VCC is connected with the D input end of the first D trigger, the D input end of the second D trigger, the D input end of the third D trigger, the T input end of the second T trigger and the D input end of the fourth D trigger respectively;
the output end of the first AND gate is respectively connected with the CLR asynchronous input end of the first D trigger and the CLR asynchronous input end of the second D trigger, and the output end of the second AND gate is respectively connected with the CLR asynchronous input end of the third D trigger and the CLR asynchronous input end of the fourth D trigger;
the Q end of the first D trigger is connected with the A input end of the first AND gate, and the Q end of the second D trigger is respectively connected with the B input end of the first AND gate, the B input end of the second OR gate and the input end of the NOT gate;
the Q end of the third D trigger is respectively connected with the A input end of the second AND gate, the C input end of the first data latch, the C input end of the second data latch and the B input end of the third AND gate, and the Q end of the fourth D trigger is connected with the B input end of the second AND gate;
the Q end of the second T trigger is connected with the A input end of the third AND gate;
the output end of the third AND gate is connected with the A input end of the second OR gate, and the output end of the second OR gate is reversible
The output end of the NOT gate is connected with the I/D input end of the reversible counter, the output end Q [ N.0 ] of the reversible counter is connected with the D [ N.0 ] input end of the first data latch through N+1 data lines, the Q [ N.0 ] output end of the first data latch is connected with the A input end of the subtracter through a data bus D [ N.0 ], the QN output end of the first data latch is connected with the D [ N-1.0 ] input end of the second data latch through a data bus D [ N.1 ], and the Q [ N.0 ] output end of the second data latch is connected with the B input end of the subtracter through N+1 data buses;
the output end of the subtractor is connected with the input end of the third data latch D [ N.0 ], and the output end of the third data latch Q [ N.0 ] is connected with the input end of the first comparator A through a data bus P [ N.0 ];
the Q [ N.0 ] output end of the counter is connected with the B input end of the first comparator through a data bus Q [ N.0 ], and the Q [ N-1.0 ] output end of the counter is connected with the A input end of the second comparator through a data bus Q [ N-1.0 ];
the Q [ N.1 ] output end of the first data latch is connected with the B input end of the second comparator through a data bus P [ N.1 ]; the output end of the first comparator is respectively connected with the CLR input end of the counter and the A input end of the first OR gate; the output end of the second comparator is connected with the B input end of the first OR gate, and the output end of the first OR gate is connected with the T input end of the first T trigger; the Q output end of the first T trigger is respectively connected with the C input end of the first data latch, the C input end of the second D trigger, the C input end of the third D trigger and the output end.
The invention has the beneficial effects that: according to the predictive synchronization system disclosed by the invention, the delay of a synchronization signal sent from a source to a receiving end is T, the delay of the synchronization signal reflected back to the source is 2T, the total delay of the reflected delayed signals reaching the receiving end again is 3T, and the time difference of each signal is proportional to the transmission delay; thus, a precise time synchronization signal can be predicted.
In the predictive synchronization system of the invention, the synchronization signal obtained at the receiving end is not obtained from transmission, but is predicted and generated in advance by taking the transmitted synchronization signal as a reference. The system can automatically adapt to and accurately predict the time delay generated by long-distance transmission of the transmission link, and the transmission distance does not need to be measured or circuit parameters need to be adjusted in the implementation and installation process, and all the synchronous information passing through different transmission distances can be automatically kept synchronous and consistent with the original synchronous signal.
The prediction synchronization system provided by the invention can automatically match the length of the transmission cable, and reconstruct synchronization signals for all subsystems according to the delay proportion. I.e. it is not necessary to measure how long the actual cable is, nor how much the signal delay time is. The various subsystems being synchronized are independent of each other, and no change to any single subsystem is necessary to adjust the other subsystems. Either a synchronization signal with no delay or no phase difference from the synchronization source can be generated or a synchronization signal with a fixed amount of lead or lag from the source can be generated.
The invention can automatically measure the delay of the signal in the line and predicts and generates a signal advanced than the original synchronous signal, and adopts the mode of equal compensation of the advance and the delay to realize the accurate synchronization of the synchronized system and the original synchronous signal without delay; no adjustment is required in practical applications.
Drawings
FIG. 1 is a schematic circuit diagram of a precision time-predicted synchronous electronic system according to the present invention;
FIG. 2 is a schematic circuit diagram of a lead half-ratio phase lock circuit in a precision time-predicted synchronous electronic system according to the present invention;
FIG. 3 is a schematic circuit diagram of a center-to-center phase lock circuit in a precision time-predicted synchronous electronic system according to the present invention;
FIG. 4 is a waveform diagram of three signals in a centered ratio synchronization mode in a precision time-predicted synchronous electronic system according to the present invention; waveform diagrams of INA, INB and OUT; in the figure, the sequence of the arrival of the edges of the three signals a, b and the output signal out is that of the signals a, out and b, and the time difference ta=tb;
FIG. 5 is a waveform diagram of a precise time-predicted synchronous electronic system in advance half-ratio synchronous mode according to the present invention; in the figure, the sequence of the arrival of the three signal edges of the signal a, the signal b and the output signal out is that of the output signal out, the signal a and the signal b, and the time difference is 2ta=tb.
Detailed Description
The first embodiment, referring to fig. 1 and fig. 2, describes a precise time prediction synchronization electronic system, which includes a synchronization source input end SIN, a first equal-length cable, a second equal-length cable, a third equal-length cable, a synchronization signal output end SOUT, a source circuit SND and a receiving circuit REC;
the synchronous signal source input end SIN is connected with the input end of the signal source end circuit SND, the A output end of the signal source end circuit SND is connected with the A input end of the receiving end circuit REC through a first equal-length cable, the B input end of the signal source end circuit SND is connected with the B output end of the receiving end circuit REC through a second equal-length cable, the C output end of the signal source end circuit SND is connected with the C input end of the receiving end circuit REC through a third equal-length cable, and the OUT output end of the receiving end circuit REC is connected with the synchronous signal output end SOUT;
the signal source end circuit SND comprises an advance half-ratio phase-locked circuit, the signal source end circuit SND predicts and generates a synchronous signal with the advance time of T, the synchronous signal is transmitted to the receiving end circuit REC through a first equal-length cable and delayed for a period of time of T, and a synchronous signal which is not delayed with the original synchronous signal PX is obtained at an OUT output end of the receiving end circuit REC; the implementation process is as follows:
the original synchronous signal PX input by the synchronous signal source input end SIN is changed into an output signal PA0 through an A output end of the signal source end circuit SND, the output signal PA0 is transmitted to an A input end of the receiving end circuit REC through a first equal-length cable and becomes an input signal PA1, the delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is output a signal PB0 through a B output end of the receiving end circuit REC, the output signal PB0 is fed back to a B input end of the signal source end circuit SND through a second equal-length cable and becomes an input signal PB1, and the delay between the input signal PB1 and the original synchronous signal PX is 2T;
the lead half-ratio phase-locked circuit predicts and generates an output signal PC0 with a lead time of T compared with the original synchronous signal PX by utilizing the original synchronous signal PX and an input signal PB1 with a delay of 2T, the output signal PC0 is output from a C output end of an information source end circuit SND and is transmitted to a C input end of a receiving end circuit REC through a third equal-length cable to become the input signal PC1, the delay of the input signal PC1 and the output signal PC0 is T, the lead amount and the delay amount can be mutually offset, and the receiving end circuit REC obtains the input signal PC1 which has no delay with the original synchronous signal PX;
referring to fig. 2, the half-advanced phase lock circuit includes the half-advanced phase lock circuit including an input terminal INA, an input terminal INB, an output terminal OUT, a clock input terminal OSC, a first D flip-flop U1, a second D flip-flop U2, a second D flip-flop U10, a fourth D flip-flop U4, a first and gate U3, a second and gate U11, a third and gate U19, an not gate U5, a first data latch U7, a second data latch U8, a third data latch U12, a reversible counter U6, a counter U15, a subtractor U9, a first comparator U13, a second comparator U14, a first or gate U16, a second or gate U20, a first T flip-flop U17, and a second T flip-flop U18;
the input end INA is connected with the C input end of the first D trigger U1, the input end INB is connected with the C input end of the fourth D trigger U4, the clock input end OSC is respectively connected with the CLK input end of the reversible counter U6, the C input end of the second T trigger U18, the CP input end of the counter U15 and the C input end of the first T trigger U17;
VCC is connected with the D input end of the first D trigger U1, the D input end of the second D trigger U2, the D input end of the third D trigger U10, the T input end of the second T trigger U18 and the D input end of the fourth D trigger U4 respectively;
the output end of the first AND gate U3 is respectively connected with the CLR asynchronous input end of the first D trigger U1 and the CLR asynchronous input end of the second D trigger U2, and the output end of the second AND gate U11 is respectively connected with the CLR asynchronous input end of the third D trigger U10 and the CLR asynchronous input end of the fourth D trigger U4;
the Q end of the first D trigger U1 is connected with the A input end of the first AND gate U3, the Q end of the second D trigger U2 is respectively connected with the B input end of the first AND gate U3, the B input end of the second OR gate U20 and the input end of the NOT gate U5;
the Q end of the third D trigger U10 is respectively connected with the A input end of the second AND gate U11, the C input end of the first data latch U7, the C input end of the second data latch U8 and the B input end of the third AND gate U19, and the Q end of the fourth D trigger U4 is connected with the B input end of the second AND gate U11;
the Q end of the second T trigger U18 is connected with the A input end of the third AND gate U19;
the output end of the third AND gate U19 is connected with the A input end of the second OR gate U20, the-output end of the second OR gate U20 is connected with the CE end of the reversible counter U6, the output end of the NOT gate U5 is connected with the I/D input end of the reversible counter U6, the output end Q [ N..0] of the reversible counter U6 is connected with the D [ N..0] input end of the first data latch U7 through an N+1 data line, the Q [ N..0] output end of the first data latch U7 is connected with the A input end of the subtracter U9 through a data bus D [ N..0], the QN output end of the first data latch U7 is connected with the D [ N-1..0] input end of the second data latch U8 through a data bus D [ N..1], and the Q [ N..0] output end of the second data latch U8 is connected with the B input end of the subtracter U9 through an N+1 data bus;
the Y output end of the subtracter U9 is connected with the D [ N.0 ] input end of the third data latch U12, and the Q [ N.0 ] output end of the third data latch U12 is connected with the A input end of the first comparator U13 through a data bus P [ N.0 ];
the output end of the Q [ N.0 ] of the counter U15 is connected with the input end B of the first comparator U13 through a data bus Q [ N.0 ], and the output end Q [ N-1.0 ] of the counter U15 is connected with the input end A of the second comparator U14 through a data bus Q [ N-1.0 ];
the Q [ N.1 ] output end of the first data latch U12 is connected with the B input end of the second comparator (U14) through a data bus P [ N.1 ]; the output end of the first comparator U13 is respectively connected with the CLR input end of the counter U15 and the A input end of the first OR gate U16; the output end of the second comparator U14 is connected with the B input end of the first OR gate U16, and the output end of the first OR gate U16 is connected with the T input end of the first T trigger U17; the Q output terminal of the first T flip-flop U17 is connected to the C input terminal of the first data latch U12, the C input terminal of the second D flip-flop U2, the C input terminal of the third D flip-flop U10, and the output terminal OUT, respectively.
In this embodiment, the signal output from the a output end of the source end circuit SND is PA0, the signal transmitted to the a input end of the receiving end circuit REC through the first equal-length cable is PA1, the delay time between PA1 and PA0 is T1, and the value is equal to the propagation time of the electromagnetic wave in the cable a plus the delay of the interface circuit element; the output signal of the B output end of the receiving end circuit REC is PB0, the B input end of the signal transmitted to the information source end circuit SND through the second equal-length cable signal is PB1, and the delay time between PB1 and PB0 is T2; the output signal of the C output end of the information source end circuit SND is PC0, the C input end which is transmitted to the receiving end circuit REC through the third equal-length cable C becomes PC1, and the delay time between PC1 and PC0 is T3; the source side circuit SND and the receiver side circuit REC use the same circuit elements to design signal transmitting and receiving circuits, and use three cables with equal lengths to transmit signals, so that the three signal delay times T1, T2 and T3 are equal, and the value is T.
In this embodiment, the lengths of the first equal-length cable, the second equal-length cable and the third equal-length cable are equal, and in practical application, the three cables may be three core wires in a multi-core cable, or three pairs of twisted core wires, or may be a single-core or multi-core wire or optical fiber capable of multiplexing and transmitting three groups of information; several core wires in one multi-core cable are used as the three equal-length cables, and only the equal lengths of the three equal-length cables are ensured without measuring the real lengths.
In the second embodiment, the receiver circuit REC is provided with a half-advanced phase-locked circuit instead of the first embodiment, and the receiver circuit REC predicts and generates a precise time synchronization signal without delay from the original synchronization signal, which is as follows:
the method comprises the steps that an original synchronous signal input by a synchronous source input end SIN is PX, an output signal of the synchronous source input end SIN is PA0 and is directly sent to an A input end of a receiving end circuit REC through a first equal-length cable, the input signal is PA1, delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is changed into an output signal PB0 from a B output end of the receiving end circuit REC, the output signal PBO is fed back to a B input end of the source circuit SND through a second equal-length cable, and the delay between the input signal PB1 and the end of the original synchronous signal PX is 2T; the input signal PB1 is changed into an output signal PC0 from the C output end of the information source end circuit SND, the output signal PCO is transmitted to the C input end of the receiving end circuit REC through a third equal-length cable and is changed into an input signal PC1, and a delay of 3T exists between the input signal PC1 and the original synchronous signal PX; the receiving end circuit REC receives two signals, namely a signal PA1 with a delay of T and a signal PC1 with a delay of 3T, wherein the time difference of the two signals is in direct proportion to the transmission delay; the synchronous signal PZ generated by the advanced half-ratio phase-locked circuit has no delay with the original synchronous signal PX.
In the third embodiment, a middle equal ratio phase-locking circuit is arranged in the information source end circuit SND to replace the advanced half ratio phase-locking circuit of the information source end circuit SND in the first embodiment; generating a leading synchronous signal in the SND prediction of the source end circuit, wherein the leading synchronous signal has no delay with the original synchronous signal when reaching the REC; the specific implementation mode is as follows:
the original synchronous signal input by the synchronous information source input end SIN is PX; a phase-locked loop PLL is arranged in the information source end circuit SND, a voltage-controlled oscillator VCO output signal of the phase-locked loop PLL is output to an A output end output signal PA0 of the information source end circuit SND, the A input end of the signal source end circuit SND is transmitted to a receiving end circuit REC through a first equal-length cable to be changed into an input signal PA1, delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is changed into an output signal PB0 through a B output end of the receiving end circuit REC, the output signal PA1 is fed back to a B input end of the information source end circuit SND through a second equal-length cable to be changed into an input signal PB1, and the delay between the input signal PB1 and an original synchronous signal PX is 2T; the original synchronous signal PX and the input signal PB1 are respectively connected to two input ends of the phase discriminator in the phase-locked loop PLL, and if the phase-locked loop PLL enters a locked state, the signal PA0 leads the original synchronous signal PX to be 2T;
predicting an output signal PA0 with a lead of 2T and an original synchronous signal PX by using a centering equal ratio phase-locking circuit to generate a lead synchronous signal PC0 with a lead time of T compared with the original synchronous signal; the advanced synchronization signal PCO is sent to the C input end of the receiving end circuit REC through a third equal-length cable to become an input signal PC1; the delay of the input signal PC1 and the advanced synchronous signal PC0 is T, and the advanced synchronous signal PC0 advances the original synchronous signal PX to be T; the input signal PC1 is not delayed from the original synchronization signal PX.
In this embodiment, referring to fig. 3, the intermediate equal ratio phase lock circuit includes an input terminal INA, an input terminal INB, an output terminal OUT, a clock input terminal OSC, a first D flip-flop U1, a second D flip-flop U2, a third D flip-flop U10, a fourth D flip-flop U4, a first and gate U3, a second and gate U11, a second or gate U18, an not gate U5, a first data latch U7, a second data latch U8, a third data latch U12, a reversible counter U6, a counter U15, a subtractor U9, a first comparator U13, a second comparator U14, a first or gate U16 and a T flip-flop U17;
the input end INA is connected with the C input end of the first D trigger U1, and the input end INB is connected with the C input end of the fourth D trigger U4;
the clock input end OSC is respectively connected with the CLK input end of the reversible counter U6, the CP input end of the counter U15 and the C input end of the T trigger U17;
VCC is connected with the D input end of the first D trigger U1, the D input end of the second D trigger U2, the D input end of the third D trigger U10 and the D input end of the fourth D trigger U4 respectively;
the output end of the first AND gate U3 is respectively connected with the CLR asynchronous input end of the first D trigger U1 and the CLR asynchronous input end of the second D trigger U2, and the output end of the second AND gate U11 is respectively connected with the CLR asynchronous input end of the third D trigger U10 and the CLR asynchronous input end of the fourth D trigger U4;
the Q end of the first D trigger U1 is respectively connected with the A input end of the first AND gate U3, the input end of the NOT gate U5 and the A input end of the second OR gate U18, the Q end of the second D trigger U2 is connected with the B input end of the first AND gate U3, the Q end of the third D trigger U10 is respectively connected with the A input end of the second AND gate U11 and the B input end of the second OR gate U18, the Q end of the fourth D trigger U4 is connected with the B input end of the first AND gate U11, and the output end of the second OR gate U18 is respectively connected with the CE input end of the reversible counter U6, the C input end of the first data latch U7 and the C input end of the second data latch U8;
the output of the NOT gate U5 and the up-down counter U6
The input end is connected, and the output end Q [ N..0 of the reversible counter U6]D [ n..0] with the first data latch U7 through n+1 data lines]The input terminal is connected, Q [ N..0] of the first data latch U7]The output end passes through D [ N. ] 0]The data bus is connected to the A input of the subtractor U9, Q [ N..1] of the first data latch U7]The output end passes through D [ N. ] 1]Data bus and second data latchU8D [ N-1..0]]The input end is connected;
the Q n.0 output of the second data latch U8 is connected to the B input of the subtractor U9,
the Y output of subtractor U9 is connected to the D n.0 input of a third data latch U12,
the Q n.0 output of the third data latch U12 is connected to the a input of the first comparator U13 via a P n.0 data bus,
the Q [ N.0 ] output end of the third data latch U12 is connected with the B input end of the second comparator U14 through a data bus P [ N.1 ], and the output end of the second comparator U14 is connected with the B input end of the first OR gate U16;
the output end of the Q [ N.0 ] of the counter U15 is connected with the input end B of the first comparator U13 through a data bus Q [ N.0 ], and the output end Q [ N-1.0 ] of the counter U15 is connected with the input end A of the second comparator U14 through a data bus Q [ N-1.0 ]; the output end of the first comparator U13 is respectively connected with the CLR input end of the counter U15 and the A input end of the first OR gate U16, and the output end of the first OR gate U16 is connected with the T input end of the T trigger U17; the Q output terminal of the T flip-flop U17 is connected to the C input terminal of the third data latch U12, the C input terminal of the second D flip-flop U2, the C input terminal of the third D flip-flop U10, and the output terminal OUT, respectively.
In the fourth embodiment, a centered equal-ratio phase-locked circuit is arranged in the receiving-end circuit REC to replace the centered equal-ratio phase-locked circuit of the information source end circuit SND in the third embodiment; the circuit REC at the receiving end predicts and generates a precise time synchronizing signal which has no delay with the original synchronizing signal, and the specific implementation mode is as follows:
an original synchronous signal PX input by a synchronous signal source input end SIN is directly transmitted to a C input end of a receiving end circuit REC through a third equal-length cable from an output signal PC0 output by an SNDC output end of a signal source end circuit SNDC to be changed into an input signal PC1, and the input signal PC1 and the original synchronous signal PX have delay of T; a phase-locked loop PLL is arranged in the information source end circuit SND, a voltage-controlled oscillator VCO output signal of the phase-locked loop PLL is output to an A output end output signal PA0 of the information source end circuit SND, the output signal PA0 is sent to an A input end of the receiving end circuit REC through a first equal-length cable to be changed into an input signal PA1, delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is output to a signal PB0 from a B output end of the receiving end circuit REC, the output signal PB0 is fed back to a B input end of the information source end circuit SND through a second equal-length cable to be changed into an input signal PB1, and delay between the input signal PB1 and an original synchronous signal PX is 2T; the original synchronous signal PX and the input signal PB1 are respectively connected to two input ends of a phase discriminator in the phase-locked loop PLL, if the phase-locked loop PLL enters a locking state, the output signal PA0 signal leads the original synchronous signal PX by 2T, and the input signal PA1 leads the original synchronous signal PX by T; the generated synchronization signal PZ is predicted by a centered equal-ratio phase-locked circuit with an output signal PA1 advanced by T from the original synchronization signal PX and an input signal PC1 delayed by the same T as the original synchronization signal PX, the synchronization signal PZ being not delayed from the original synchronization signal PX.
In the advanced half-ratio phase-locked circuit according to this embodiment, two signals a and b with frequencies f are input through the input terminal INA and the input terminal INB respectively, and the rising edge of the signal a arrives before the rising edge of the signal b, and after the circuit finishes synchronous locking, a signal out is output, the frequency of the input signal out is automatically equal to f, and the input signal out advances the signal a and has a time difference TA, and a time difference TB exists between the signal a and the signal b; the time difference TA and the time difference TB have a double proportional relationship. The double proportional relation can be always kept in a phase-locked mode, and is irrelevant to the absolute magnitude of the frequency or time difference of the INA signal and the INB signal;
in the intermediate equal ratio phase-locked circuit according to the present embodiment, two signals a and b with frequencies f are input through the input terminal INA and the input terminal INB respectively, and the rising edge of the signal a arrives before the rising edge of the signal b, after the circuit finishes synchronous locking, the signal out is output, the frequency is automatically equal to f, the signal a leads the output signal out and has a time difference TA, and the output signal out leads the signal b and has a time difference TB; the time difference TA is equal to the time difference TB in value. This equal ratio relationship can be maintained at all times regardless of the absolute magnitude of the difference in frequency or time between the INA and INB signals.
Claims (5)
1. The precise time prediction synchronous electronic system comprises a synchronous information source input end (SIN), a first equal-length cable, a second equal-length cable, a third equal-length cable, a synchronous signal output end (SOUT), an information source end circuit (SND) and a Receiving End Circuit (REC); the method is characterized in that;
the synchronous signal source input end (SIN) is connected with the input end of the signal source end circuit (SND), the A output end of the signal source end circuit (SND) is connected with the A input end of the Receiving End Circuit (REC) through a first equal-length cable, the B input end of the signal source end circuit (SND) is connected with the B output end of the Receiving End Circuit (REC) through a second equal-length cable, the C output end of the signal source end circuit (SND) is connected with the C input end of the Receiving End Circuit (REC) through a third equal-length cable, and the OUT output end of the Receiving End Circuit (REC) is connected with the synchronous signal output end (SOUT);
setting a half-advanced phase-locked circuit (SND) at the source end circuit (SND), predicting and generating a synchronous signal with the advanced time of T through the half-advanced phase-locked circuit, wherein the synchronous signal is transmitted to a Receiving End Circuit (REC) through a first equal-length cable for a delay time of T, and acquiring a synchronous signal which has no delay with an original synchronous signal PX at an OUT output end of the Receiving End Circuit (REC); the implementation process is as follows:
the original synchronous signal PX input by the synchronous signal source input end (SIN) is changed into an output signal PA0 through an A output end of the signal source end circuit (SND), the output signal PA0 is transmitted to an A input end of the Receiving End Circuit (REC) through a first equal-length cable and becomes an input signal PA1, the delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is output with a signal PB0 through a B output end of the Receiving End Circuit (REC), the output signal PB0 is fed back to a B input end of the signal source end circuit (SND) through a second equal-length cable and becomes an input signal PB1, and the delay between the input signal PB1 and the original synchronous signal PX is 2T;
the advanced half-ratio phase-locked circuit predicts and generates an output signal PC0 with an advanced time T compared with the original synchronous signal PX by utilizing the original synchronous signal PX and an input signal PB1 with a delay of 2T, the advanced synchronous signal PC0 is output from a C output end of an information source end circuit (SND) and is transmitted to a C input end of a Receiving End Circuit (REC) through a third equal-length cable to become the input signal PC1, the delay of the input signal PC1 and the output signal PC0 is T, and the Receiving End Circuit (REC) obtains the input signal PC1 which has no delay with the original synchronous signal PX;
the lead half-ratio phase-locked circuit comprises an input end INA, an input end INB, an output end (OUT), a clock input end (OSC), a first D trigger (U1), a second D trigger (U2), a third D trigger (U10), a fourth D trigger (U4), a first AND gate (U3), a second AND gate (U11), a third AND gate (U19), a NOT gate (U5), a first data latch (U7), a second data latch (U8), a third data latch (U12), a reversible counter (U6), a counter (U15), a subtracter (U9), a first comparator (U13), a second comparator (U14), a first OR gate (U16), a second OR gate (U20), a first T trigger (U17) and a second T trigger (U18); the input end INA is connected with the C input end of the first D trigger (U1), the input end INB is connected with the C input end of the fourth D trigger (U4), the clock input end (OSC) is respectively connected with the CLK input end of the reversible counter (U6), the C input end of the second T trigger (U18), the CP input end of the counter (U15) and the C input end of the first T trigger (U17);
VCC is respectively connected with the D input end of the first D trigger (U1), the D input end of the second D trigger (U2), the D input end of the third D trigger (U10), the T input end of the second T trigger (U18) and the D input end of the fourth D trigger (U4);
the output end of the first AND gate (U3) is respectively connected with the CLR asynchronous input end of the first D trigger (U1) and the CLR asynchronous input end of the second D trigger (U2), and the output end of the second AND gate (U11) is respectively connected with the CLR asynchronous input end of the third D trigger (U10) and the CLR asynchronous input end of the fourth D trigger (U4);
the Q end of the first D trigger (U1) is connected with the A input end of the first AND gate (U3), the Q end of the second D trigger (U2) is respectively connected with the B input end of the first AND gate (U3), the B input end of the second OR gate (U20) and the input end of the NOT gate (U5);
the Q end of the third D trigger (U10) is respectively connected with the A input end of the second AND gate (U11), the C input end of the first data latch (U7), the C input end of the second data latch (U8) and the B input end of the third AND gate (U19), and the Q end of the fourth D trigger (U4) is connected with the B input end of the second AND gate (U11);
the Q end of the second T trigger (U18) is connected with the A input end of the third AND gate (U19);
the output end of the third AND gate (U19) is connected with the A input end of the second OR gate (U20), the output end of the second OR gate (U20) is connected with the CE end of the reversible counter (U6), and the output end of the NOT gate (U5) is connected with
The I/D input end of the reversible counter (U6) is connected, the output end Q [ N.0 ] of the reversible counter (U6) is connected with the D [ N.0 ] input end of the first data latch (U7) through N+1 data lines, the Q [ N.0 ] output end of the first data latch (U7) is connected with the A input end of the subtracter (U9) through a data bus D [ N.0 ], the QN output end of the first data latch (U7) is connected with the D [ N-1.0 ] input end of the second data latch (U8) through a data bus D [ N.1 ], and the Q [ N.0 ] output end of the second data latch (U8) is connected with the B input end of the subtracter (U9) through N+1 data buses;
the Y output end of the subtracter (U9) is connected with the D [ N..0] input end of the third data latch (U12), and the Q [ N..0] output end of the third data latch (U12) is connected with the A input end of the first comparator (U13) through a data bus P [ N..0 ];
the Q [ N.0 ] output end of the counter (U15) is connected with the B input end of the first comparator (U13) through a data bus Q [ N.0 ], and the Q [ N-1.0 ] output end of the counter (U15) is connected with the A input end of the second comparator (U14) through a data bus Q [ N-1.0 ];
the Q [ N..1] output end of the first data latch (U12) is connected with the B input end of the second comparator (U14) through a data bus P [ N..1 ];
the output end of the first comparator (U13) is respectively connected with the CLR input end of the counter (U15) and the A input end of the first OR gate (U16);
the output end of the second comparator (U14) is connected with the B input end of the first OR gate (U16), and the output end of the first OR gate (U16) is connected with the T input end of the first T trigger (U17);
the Q output end of the first T trigger (U17) is respectively connected with the C input end of the first data latch (U12), the C input end of the second D trigger (U2), the C input end of the third D trigger (U10) and the output end (OUT);
the advanced half-ratio phase-locked circuit of the Receiving End Circuit (REC) is adopted to replace the advanced half-ratio phase-locked circuit of the information source end circuit (SND), and the advanced half-ratio phase-locked circuit of the Receiving End Circuit (REC) predicts and generates a precise time synchronizing signal which has no delay with an original synchronizing signal, and the specific implementation mode is as follows:
an original synchronous signal input by a synchronous signal source input end (SIN) is PX, an output signal of PA0 is directly output from an A output end of a signal source end circuit (SND), the signal is sent to an A input end of a Receiving End Circuit (REC) through a first equal-length cable and becomes an input signal PA1, delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is changed into an output signal PB0 from a B output end of the Receiving End Circuit (REC), the output signal PB0 is fed back to a B input end of the signal source end circuit (SND) through a second equal-length cable and becomes an input signal PB1, and delay between the input signal PB1 and the end of the original synchronous signal PX is 2T; changing the input signal PB1 from the C output end of the source end circuit (SND) to an output signal PC0, transmitting the output signal PC0 to the C input end of the Receiving End Circuit (REC) through a third equal-length cable to become an input signal PC1, wherein a delay of 3T exists between the input signal PC1 and the original synchronous signal PX; the Receiving End Circuit (REC) receives two signals, namely a signal PA1 with a delay of T and a signal PC1 with a delay of 3T, wherein the time difference of the two signals is in direct proportion to the transmission delay; the synchronous signal PZ generated by the advanced half-ratio phase-locked circuit and the original synchronous signal PX have no delay;
adopting a middle equal ratio phase-locked circuit arranged in the information source end circuit (SND) to replace an advanced half ratio phase-locked circuit of the information source end circuit (SND);
generating a leading synchronization signal in the source side circuit (SND) by prediction, wherein the leading synchronization signal has no delay with the original synchronization signal when reaching the receiving side circuit (REC); the specific implementation mode is as follows:
an original synchronous signal input by a synchronous information source input end (SIN) is PX; a phase-locked loop (PLL) is arranged in the source end circuit (SND), a voltage-controlled oscillator (VCO) output signal of the phase-locked loop (PLL) is output to an A output end output signal (PA 0) of the source end circuit (SND), the A input end output signal (PA 0) is transmitted to a Receiving End Circuit (REC) through a first equal-length cable and becomes an input signal (PA 1), delay between the input signal (PA 1) and the output signal (PA 0) is T, the input signal (PA 1) is changed into an output signal (PB 0) through a B output end of the Receiving End Circuit (REC), the B input end output signal (PB 1) fed back to the source end circuit (SND) through a second equal-length cable is changed into an input signal (PB 1), and delay between the input signal (PB 1) and an original synchronous signal (PX) is 2T; the original synchronous signal PX and the input signal PB1 are respectively connected to two input ends of the phase discriminator in the phase-locked loop (PLL), and if the phase-locked loop (PLL) enters a locked state, the signal of the output signal PA0 leads the original synchronous signal PX to be 2T;
predicting an output signal PA0 with a lead of 2T and an original synchronous signal PX by using a centering equal ratio phase-locking circuit to generate a lead synchronous signal PC0 with a lead time of T compared with the original synchronous signal; the advanced synchronization signal PC0 is sent to the C input end of the Receiving End Circuit (REC) through a third equal-length cable to become an input signal PC1; the delay of the input signal PC1 and the advanced synchronous signal PC0 is T, and the advanced synchronous signal PC0 advances the original synchronous signal PX to be T; the input signal PC1 and the original synchronization signal PX have no delay;
the intermediate equal ratio phase-locked circuit comprises an input end INA, an input end INB, an output end (OUT), a clock input end (OSC), a first D trigger (U1), a second D trigger (U2), a third D trigger (U10), a fourth D trigger (U4), a first AND gate (U3), a second AND gate (U11), a second OR gate (U18), a NOT gate (U5), a first data latch (U7), a second data latch (U8), a third data latch (U12), a reversible counter (U6), a counter (U15), a subtracter (U9), a first comparator (U13), a second comparator (U14), a first OR gate (U16) and a T trigger (U17); the input end INA is connected with the C input end of the first D trigger (U1), and the input end INB is connected with the C input end of the fourth D trigger (U4);
the clock input end (OSC) is respectively connected with the CLK input end of the reversible counter (U6), the CP input end of the counter (U15) and the C input end of the T trigger (U17);
VCC is respectively connected with the D input end of the first D trigger (U1), the D input end of the second D trigger (U2), the D input end of the third D trigger (U10) and the D input end of the fourth D trigger (U4);
the output end of the first AND gate (U3) is respectively connected with the CLR asynchronous input end of the first D trigger (U1) and the CLR asynchronous input end of the second D trigger (U2), and the output end of the second AND gate (U11) is respectively connected with the CLR asynchronous input end of the third D trigger (U10) and the CLR asynchronous input end of the fourth D trigger (U4);
the Q end of the first D trigger (U1) is respectively connected with the A input end of the first AND gate (U3), the input end of the NOT gate (U5) and the A input end of the second OR gate (U18), the Q end of the second D trigger (U2) is connected with the B input end of the first AND gate (U3), the Q end of the third D trigger (U10) is respectively connected with the A input end of the second AND gate (U11) and the B input end of the second OR gate (U18), the Q end of the fourth D trigger (U4) is connected with the B input end of the first AND gate (U11), the output end of the second OR gate (U18) is respectively connected with the CE input end of the reversible counter (U6), the C input end of the first data latch (U7) and the C input end of the second data latch (U8);
the output of the NOT gate (U5) and the reversible counter (U6)
The input end is connected with the output end Q [ N..0] of the reversible counter (U6)]D [ N..0] with the first data latch (U7) through N+1 data lines]The input terminal is connected to Q [ N..0] of the first data latch (U7)]The output end passes through D [ N. ] 0]The data bus is connected to the A input of the subtractor (U9), Q [ N..1] of the first data latch (U7)]The output end passes through D [ N. ] 1]D [ N-1..0 of the data bus and the second data latch (U8)]The input end is connected;
the Q [ N..0] output end of the second data latch (U8) is connected with the B input end of the subtracter (U9), the Y output end of the subtracter (U9) is connected with the D [ N..0] input end of the third data latch (U12),
the Q [ N.0 ] output end of the third data latch (U12) is connected with the A input end of the first comparator (U13) through a P [ N.0 ] data bus,
the Q [ N..0] output end of the third data latch (U12) is connected with the B input end of the second comparator (U14) through the data bus P [ N..1], the output end of the second comparator (U14) is connected with the B input end of the first OR gate (U16);
the Q [ N.0 ] output end of the counter (U15) is connected with the B input end of the first comparator (U13) through a data bus Q [ N.0 ], and the Q [ N-1.0 ] output end of the counter (U15) is connected with the A input end of the second comparator (U14) through a data bus Q [ N-1.0 ];
the output end of the first comparator (U13) is respectively connected with the CLR input end of the counter (U15) and the A input end of the first OR gate (U16), and the output end of the first OR gate (U16) is connected with the T input end of the T trigger (U17);
the Q output end of the T trigger (U17) is respectively connected with the C input end of the third data latch (U12), the C input end of the second D trigger (U2), the C input end of the third D trigger (U10) and the output end (OUT).
2. The precision time-predicted synchronous electronic system of claim 1 wherein; replacing the centered equal ratio phase-locked circuit of the source end circuit (SND) by setting the centered equal ratio phase-locked circuit in the Receiving End Circuit (REC);
the method for predicting and generating a precise time synchronizing signal without delay with an original synchronizing signal by a centered equal ratio phase-locked circuit of a Receiving End Circuit (REC) comprises the following specific implementation modes:
an original synchronous signal PX input by a synchronous signal source input end (SIN), an output signal PC0 directly output from a C output end of a signal source end circuit (SND) is transmitted to a C input end of a Receiving End Circuit (REC) through a third equal-length cable to be changed into an input signal PC1, and the input signal PC1 and the original synchronous signal PX have delay of T; a phase-locked loop (PLL) is arranged in the source end circuit (SND), a voltage-controlled oscillator (VCO) output signal of the phase-locked loop (PLL) is output to an A output end of the source end circuit (SND) to output a signal PA0, the output signal PA0 is sent to an A input end of the Receiving End Circuit (REC) through a first equal-length cable to become an input signal PA1, delay between the input signal PA1 and the output signal PA0 is T, the input signal PA1 is output to the PB0 from a B output end of the Receiving End Circuit (REC), the output signal PB0 is fed back to a B input end of the source end circuit (SND) through a second equal-length cable to become an input signal PB1, and delay between the input signal PB1 and an original synchronous signal PX is 2T; the original synchronous signal PX and the input signal PB1 are respectively connected to two input ends of the phase discriminator in the phase-locked loop (PLL), if the phase-locked loop (PLL) enters a locked state, the signal PA0 leads the original synchronous signal PX by 2T, and the signal PA1 leads the original synchronous signal PX by T; the generated synchronization signal PZ is predicted by a centered equal-ratio phase-locked circuit with an output signal PA1 advanced by T from the original synchronization signal PX and an input signal PC1 delayed by the same T as the original synchronization signal PX, the synchronization signal PZ being not delayed from the original synchronization signal PX.
3. The precision time-predicted synchronous electronic system of claim 1 wherein; in the advanced half-ratio phase-locked circuit, a signal a and a signal b with the frequencies f are respectively input through an input end INA and an input end INB, the rising edge of the signal a arrives before the rising edge of the signal b, a signal out is output after the circuit finishes synchronous locking, the frequency of the input signal out is automatically equal to f, the input signal out is advanced to the signal a and has a time difference TA, and a time difference TB exists between the signal a and the signal b; the time difference TA and the time difference TB have a double proportional relationship.
4. The precision time-predicted synchronous electronic system of claim 1 wherein; in the intermediate equal ratio phase-locked circuit, two signals a and b with the frequency f are input through an input end INA and an input end INB respectively, the rising edge of the signal a arrives before the rising edge of the signal b, a signal out is output after the circuit finishes synchronous locking, the frequency is automatically equal to f, the signal a leads the output signal out and has a time difference TA, and the output signal out leads the signal b and has a time difference TB; the time difference TA is equal to the time difference TB in value.
5. The precision time-predicted synchronous electronic system of claim 1 wherein; the lengths of the first equal-length cable, the second equal-length cable and the third equal-length cable are equal, the three equal-length cables are three core wires in the multi-core cable, three pairs of twisted core wires and wires or optical fibers which can multiplex and transmit three groups of information and are single-core or multi-core.
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