CN103592881A - Multi-path signal synchronous sampling control circuit based on FPGA - Google Patents
Multi-path signal synchronous sampling control circuit based on FPGA Download PDFInfo
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Abstract
The invention discloses a multi-path signal synchronous sampling control circuit based on an FPGA. The circuit at least comprises a multi-path signal sampling port circuit, a crystal oscillator circuit, an FPGA chip and a microprocessor, wherein the FPGA chip at least comprises a multi-path signal sampling parallel processing module, a synchronous latch module, an output control module, an address decoding module and a synchronous latch signal generation module. A synchronous latch signal SYNL output by the synchronous latch signal generation module controls the synchronous latch module to carry out synchronous latch on multi-path data output by the multi-path signal sampling parallel processing module so that the multi-path data at the same moment output by the multi-path signal sampling parallel processing module can keep unchanged, and synchronism of the multi-path data read by a micro processor one by one from the FPGA chip is guaranteed. The multi-path signal synchronous sampling control circuit is suitable for a control system requiring synchronous sampling of multi-path signals, is especially suitable for a control system of synchronous sampling of multi-path pulse signals or multi-path digital signals, and is flexible, convenient to use and high in practicability.
Description
Technical field
The present invention relates to signals collecting and transmission technique field, be specifically related to a kind of multiple signals synchronized sampling control circuit based on FPGA.
Background technology
In modern control system, signal acquiring system has been widely used in the fields such as electronic surveying, communication, radar, Aero-Space, Industry Control.Signal can be divided into simulating signal and digital signal.Collection to simulating signal, need to be used analog-digital converter (ADC) to gather.In prior art, multichannel analog signals synchronized sampling has been carried out to large quantity research.Chinese patent literature ZL200810240063.9, ZL201010577253.7, ZL201310087071.5, ZL200720311326.1 etc. are that how synchronized sampling has carried out invention design to multichannel analog signals, but can not as simulating signal, use ADC to carry out the synchronized sampling of multiple signals to the digital pulse signal with some non-simulating signals.For example, in digital control system and Optical Coatings for Photolithography, for making system obtain more accurate positioning precision and synchronization accuracy, except needs carry out synchro control each kinematic axis, also need the synchronous sensor signal that is arranged on each kinematic axis of detecting in real time to obtain the information such as position, speed or angle of the synchronization of each kinematic axis, but the signal that is mounted in the sensor output on kinematic axis does not belong to simulating signal, but digital pulse signal.So be necessary to design a kind of synchronized sampling device or synchronized sampling control circuit, the non-simulating signal of multichannel carried out to synchronized sampling.
Summary of the invention
The present invention seeks in order to solve the synchronized sampling problem of the non-simulating signal of multichannel, thereby proposed a kind of multiple signals synchronized sampling control circuit based on FPGA.
Technical scheme of the present invention is summarized as follows:
A kind of multiple signals synchronized sampling control circuit (as shown in Figure 1) based on FPGA, at least comprise multiple signals sampling interface circuit 1, crystal oscillating circuit 2, fpga chip 3 and micro-processing 4, it is characterized in that: described fpga chip 3 at least comprises multiple signals sample-parallel processing module 31, synchrolock storing module 32, output control module 33, address decoding module 34 and synchronously latchs signal generator module 35.
The input end of described multiple signals sample-parallel processing module 31 is connected with the output terminal of multiple signals sampling interface circuit 1; The output terminal of described multiple signals sample-parallel processing module 31 is connected with the input end of synchrolock storing module 32; The output terminal of described synchrolock storing module 32 is connected with the input end of output control module 33; The data d of described multiple signals sample-parallel processing module 31 outputs
1, d
2..., d
nbe input to synchrolock storing module 32; The data sd of described synchrolock storing module 32 outputs
1, sd
2..., sd
nbe input to output control module 33; The data way of described synchrolock storing module 32 outputs equates with the data way that multiple signals sample-parallel processing module 31 is exported, i.e. data d
nwith data sd
nin subscript n equate, n is positive integer and n>=2.
The output terminal of the address decoding module 34 of described fpga chip 3 respectively with the input end of output control module 33 with synchronize the input end that latchs signal generator module 35 and be connected; The decoded signal a of described address decoding module 34 outputs
1, a
2..., a
nbe input to output control module 33, the control signal CTL of described address decoding module 34 outputs and synchronizing signal SYN2 are input to and synchronously latch signal generator module 35.The decoded signal number of described address decoding module 34 outputs equates with the data way that synchrolock storing module 32 is exported, i.e. decoded signal a
n, data d
nwith data sd
nin subscript n equate, n is positive integer and n>=2.The decoded signal a of described address decoding module 34 outputs
1, a
2..., a
ndata sd with 32 outputs of synchrolock storing module
1, sd
2..., sd
ncorresponding one by one, i.e. the identical decoded signal a of subscript
nwith data sd
ncorresponding; As decoded signal a
nin the time of effectively, microprocessor 4 is reading out data sd from output control module 33
n.
Described micro-processing 4 is connected with the output control module 33 of fpga chip 3 with read control signal by data bus; Described micro-processing 4 is connected with the address decoding module 34 of fpga chip 3 by address bus; Described micro-processing 4 is latched signal generator module 35 with output holding signal HOLD with synchronizeing of fpga chip 3 by data bus, read control signal, write control signal, synchronizing signal SYN3 and is connected;
The clock signal clock of described crystal oscillating circuit 2 outputs is input to respectively multiple signals sample-parallel processing module 31, the synchrolock storing module 32 of fpga chip 3 and synchronously latchs signal generator module 35.
The described synchronous latch signal SYNL that synchronously latchs signal generator module 35 outputs is input to synchrolock storing module 32; Described synchronous latch signal SYNL controls synchrolock storing module 32 by the data d of the synchronization of multiple signals sample-parallel processing module 31 outputs
1, d
2..., d
nsynchrolock saves as the data sd of synchrolock storing module 32 outputs
1, sd
2..., sd
n.
Described synchronously latch signal generator module 35 (as shown in Figure 2) at least comprise Sheffer stroke gate, with door or door, control register, frequency divider, Logical processing unit, synchronizer and chronotron; An input end of described Sheffer stroke gate is connected with the read control signal of micro-processing 4 outputs, and another input end of described Sheffer stroke gate is connected with the write control signal of micro-processing 4 outputs; Input end of described and door and the output terminal of Sheffer stroke gate are connected, and are describedly connected with the control signal CTL of address decoding module 34 outputs with another input end of door; The input end EN of described control register be connected with the output terminal of door; The input end D of described control register is connected with the data bus of micro-processing 4 outputs; The input end D of described frequency divider is connected with the output terminal Q of control register; The input end D of described Logical processing unit is connected with the synchronizing signal SYN2 of address decoding module 34 outputs; The input end D of described synchronizer is connected with the synchronizing signal SYN3 of micro-processing 4 outputs; Input end described or door is connected with synchronizing signal SYN1, the output terminal of Logical processing unit and the output terminal of synchronizer of frequency divider output respectively; The input end D of described chronotron with or door output terminal be connected; The clock signal clock of described crystal oscillating circuit 2 outputs respectively with the input end Clk of controller, the input end Clk of the input end Clk of frequency divider, Logical processing unit, the input end Clk of the input end Clk of synchronizer and chronotron be connected; Signal described or gate output terminal output is described synchronous latch signal SYNL; The signal of described chronotron output terminal output is described output holding signal HOLD.When described output holding signal HOLD is effective, show that synchrolock storing module 32 that synchronous latch signal SYNL controlled fpga chip 3 is by the data d of the synchronization of multiple signals sample-parallel processing module 31 outputs
1, d
2..., d
nsynchrolock saves as the data sd of synchrolock storing module 32 outputs
1, sd
2..., sd
n.
Described synchrolock storing module 32 (as shown in Figure 3) comprises two latchs or two above latchs; The number of described latch equates with the data way of multiple signals sample-parallel processing module 31 outputs; The input end Clk of each latch is connected with the clock signal clock of crystal oscillating circuit 2 outputs; The latching control end Clk-EN and synchronize the synchronous latch signal SYNL that latchs signal generator module 35 output and be connected of each latch; The input end D of each latch is connected with the data of multiple signals sample-parallel processing module 31 outputs, and the data of the output terminal Q output of each latch are connected with the input end of output control module 33.
The described synchronous latch signal SYNL producing method that synchronously latchs signal generator module 35 outputs has three kinds: first kind of way is that the described frequency divider that synchronously latchs signal generator module 35 carries out K frequency division according to the divide ratio K of control register output to the clock signal clock of crystal oscillating circuit 2 outputs, the synchronizing signal SYN1 of frequency divider output is the K fractional frequency signal of clock signal clock, and synchronizing signal SYN1 passes through or export behind the door synchronous latch signal SYNL; The second way is that the synchronizing signal SYN2 of described address decoding module 34 outputs is input to the Logical processing unit that synchronously latchs signal generator module 35, and the signal of Logical processing unit output terminal output passes through or export behind the door synchronous latch signal SYNL; The third mode is that the synchronizing signal SYN3 of described microprocessor 4 outputs is input to the synchronizer that synchronously latchs signal generator module 35, and the signal of microsyn output end output passes through or export behind the door synchronous latch signal SYNL; When described divide ratio K equals zero, first kind of way is inoperative; When described synchronizing signal SYN2 is low level always, the described second way is inoperative; When described synchronizing signal SYN3 is low level, described the third mode is inoperative.
As the data d that need to export multiple signals sample-parallel processing module 31
1, d
2..., d
nwhile carrying out synchronized sampling, described microprocessor 4 selects wherein a kind of mode of synchronous latch signal SYNL producing method to make the signal generator module 35 that synchronously latchs of fpga chip 3 produce synchronous latch signal SYNL, when the output holding signal HOLD that synchronously latchs signal generator module 35 output of fpga chip 3 is effective, show that synchrolock storing module 32 that synchronous latch signal SYNL controlled fpga chip 3 is by the data d of the synchronization of multiple signals sample-parallel processing module 31 outputs
1, d
2..., d
nsynchrolock saves as the data sd of synchrolock storing module 32 outputs
1, sd
2..., sd
n, at this moment microprocessor 4 can pass through data bus, address bus and read control signal from the output control module 33 of fpga chip 3 reading out data sd one by one
1, sd
2..., sd
n; Microprocessor 4 is one by one in reading out data process, the data sd of synchrolock storing module 32 outputs of fpga chip 3
1, sd
2..., sd
nremain unchanged, show that the multichannel data that microprocessor 4 reads is the data of synchronization, thereby reach the object of synchronized sampling multiple signals.
As the data d not needing 31 outputs of multiple signals sample-parallel processing module
1, d
2..., d
nwhile carrying out synchronized sampling, shown in microprocessor 4 can to the control register that synchronously latchs signal generator module 35 of fpga chip 3, write zero by data bus, address bus and write control signal, the divide ratio K of control register output is equalled zero, microprocessor 4 also makes synchronizing signal SYN2 and synchronizing signal SYN3 always in low level state simultaneously, thereby make synchronous latch signal SYNL producing method all inoperative, at this moment synchronous latch signal SYNL controls the data d that synchrolock storing module 32 does not latch 31 outputs of multiple signals sample-parallel processing module
1, d
2..., d
nso, microprocessor 4 by data bus, address bus and read control signal from the output control module 33 of fpga chip 3 reading out data sd one by one
1, sd
2..., sd
nnonsynchronous.
The invention provides a kind of multiple signals synchronized sampling control circuit based on FPGA, the synchronous latch signal SYNL that synchronously latchs signal generator module 35 generations by fpga chip 3 synchronously latchs after processing to the multichannel data of multiple signals sample-parallel processing module 31 outputs, by micro-processing 4, from fpga chip, read one by one, thereby the synchronized sampling of realizing the non-simulating signal of multichannel is controlled.The present invention can provide the producing method of three kinds of synchronous latch signal SYNL, and can realize the switching of synchronized sampling and non-synchronous sampling, flexible, practical.
Accompanying drawing explanation
Fig. 1 is a kind of technical scheme the general frame of the multiple signals synchronized sampling control circuit based on FPGA
Fig. 2 is technical scheme figure and the enforcement illustration that synchronously latchs signal generator module of the present invention
Fig. 3 is the technical scheme figure of synchrolock storing module of the present invention
Fig. 4 is an a kind of specific embodiment figure of the multiple signals synchronized sampling control circuit based on FPGA
Fig. 5 is a specific embodiment figure of synchrolock storing module of the present invention
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Be a kind of technical scheme the general frame of the multiple signals synchronized sampling control circuit based on FPGA as shown in Figure 1, the signal way of multiple signals sampling interface circuit 1 input can be the Any Digit pulse signal that is greater than 2 roads or equals 2 tunnels.The signal way of multiple signals sampling interface circuit 1 input of take is example during as three railway digital pulse signals, a specific embodiment of design a kind of multiple signals synchronized sampling control circuit based on FPGA as shown in Figure 4, this control circuit at least comprises three road signal sampling interface circuits 1, crystal oscillating circuit 2, fpga chip 3 and micro-processing 4; Described fpga chip 3 at least comprises three road signal sampling parallel processing modules 31, synchrolock storing module 32, output control module 33, address decoding module 34 and synchronously latchs signal generator module 35.
As shown in Figure 2, for synchronously latching the enforcement illustration of signal generator module 35, which comprises at least Sheffer stroke gate, with door or door, control register, frequency divider, Logical processing unit, synchronizer and chronotron; An input end of described Sheffer stroke gate is connected with the read control signal of micro-processing 4 outputs, and another input end of described Sheffer stroke gate is connected with the write control signal of micro-processing 4 outputs; Input end of described and door and the output terminal of Sheffer stroke gate are connected, and are describedly connected with the control signal CTL of address decoding module 34 outputs with another input end of door; The input end EN of described control register be connected with the output terminal of door; The input end D of described control register is connected with the data bus of micro-processing 4 outputs; The input end D of described frequency divider is connected with the output terminal Q of control register; The input end D of described Logical processing unit is connected with the synchronizing signal SYN2 of address decoding module 34 outputs; The input end D of described synchronizer is connected with the synchronizing signal SYN3 of micro-processing 4 outputs; Input end described or door is connected with synchronizing signal SYN1, the output terminal of Logical processing unit and the output terminal of synchronizer of frequency divider output respectively; The input end D of described chronotron with or door output terminal be connected; The clock signal clock of described crystal oscillating circuit 2 outputs respectively with the input end Clk of controller, the input end Clk of the input end Clk of frequency divider, Logical processing unit, the input end Clk of the input end Clk of synchronizer and chronotron be connected; Signal described or gate output terminal output is described synchronous latch signal SYNL; The signal of described chronotron output terminal output is described output holding signal HOLD.
Shown in Fig. 3, be the technical scheme figure of the synchrolock storing module of fpga chip 3 of the present invention, described synchrolock storing module 32 comprises two latchs or two above latchs; The number of described latch equates with the data way n (n is positive integer and n >=2) of multiple signals sample-parallel processing module 31 outputs.In conjunction with the specific embodiment of Fig. 4 and the technical scheme figure of Fig. 3, when n equals 3, a specific embodiment of the synchrolock storing module 32 of design fpga chip 3 as shown in Figure 5, it comprises three latchs, the input end Clk of each latch is connected with the clock signal clock of crystal oscillating circuit 2 outputs; The latching control end Clk-EN and synchronize the synchronous latch signal SYNL that latchs signal generator module 35 output and be connected of each latch; The input end D of each latch is connected with the data of multiple signals sample-parallel processing module 31 outputs, and the data of the output terminal Q output of each latch are connected with the input end of output control module 33.
In Fig. 4, described three road signal sampling interface circuits 1 are the sampling interface circuits of three optical-electricity encoder output signals, the signal of each optical-electricity encoder output is input to fpga chip 3 San road signal sampling parallel processing module 31， tri-road signal sampling parallel processing modules 31 after three road signal sampling interface circuits 1 to carry out parallel processing and exports three circuit-switched data d each road optical-electricity encoder output signal signal
1, d
2, d
3; Three circuit-switched data d
1, d
2, d
3be input to synchrolock storing module 32; The synchronous latch signal SYNL that synchronously latchs signal generator module 35 outputs controls the data sd of synchrolock storing module 32 outputs
1, sd
2, sd
3be input to output control logic 34.
When needing the data d1 of Dui San road signal sampling parallel processing module 31 outputs, d2, when d3 carries out synchronized sampling, described microprocessor 4 selects wherein a kind of mode of synchronous latch signal SYNL producing method to make the signal generator module 35 that synchronously latchs of fpga chip 3 produce synchronous latch signal SYNL, when the output holding signal HOLD that synchronously latchs signal generator module 35 output of fpga chip 3 is effective, show that synchronous latch signal SYNL has controlled the data d of synchronization of synchrolock storing module 32Jiang tri-road signal sampling parallel processing modules 31 outputs of fpga chip 3
1, d
2, d
3synchrolock saves as the data sd of synchrolock storing module 32 outputs
1, sd
2, sd
3, at this moment microprocessor 4 can pass through data bus, address bus and read control signal from the output control module 33 of fpga chip 3 reading out data sd one by one
1, sd
2, sd
3; Microprocessor 4 is one by one in reading out data process, the data sd of synchrolock storing module 32 outputs of fpga chip 3
1, sd
2, sd
3remain unchanged, show that three circuit-switched data that microprocessor 4 reads are data of synchronization, thereby reach the object of synchronized sampling multiple signals.
When not needing the data d of Dui San road signal sampling parallel processing module 31 outputs
1, d
2, d
3while carrying out synchronized sampling, shown in microprocessor 4 can to the control register that synchronously latchs signal generator module 35 of fpga chip 3, write zero by data bus, address bus and write control signal, the divide ratio K of control register output is equalled zero, microprocessor 4 also makes synchronizing signal SYN2 and synchronizing signal SYN3 always in low level state simultaneously, thereby make synchronous latch signal SYNL producing method all inoperative, at this moment synchronous latch signal SYNL controls the data d that synchrolock storing module 32 does not latch three road signal sampling parallel processing module 31 outputs
1, d
2, d
3so, microprocessor 4 by data bus, address bus and read control signal from the output control module 33 of fpga chip 3 reading out data sd one by one
1, sd
2, sd
3nonsynchronous.
In this instructions, it should be pointed out that above embodiment is only an object lesson of the present invention.Obviously, the present invention is not limited to above-mentioned specific embodiment, can also make various modifications, conversion and distortion.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.Any simple modification, equivalent variations and modification that every foundation technical spirit of the present invention is done above embodiment, all should think and belong to protection scope of the present invention.
Claims (9)
1. the multiple signals synchronized sampling control circuit based on FPGA, at least comprise multiple signals sampling interface circuit (1), crystal oscillating circuit (2), fpga chip (3) and micro-processing (4), it is characterized in that: described fpga chip (3) at least comprises multiple signals sample-parallel processing module (31), synchrolock storing module (32), output control module (33), address decoding module (34) and synchronously latchs signal generator module (35).
2. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: the input end of described multiple signals sample-parallel processing module (31) is connected with the output terminal of multiple signals sampling interface circuit (1); The output terminal of described multiple signals sample-parallel processing module (31) is connected with the input end of synchrolock storing module (32); The output terminal of described synchrolock storing module (32) is connected with the input end of output control module (33); The data d of described multiple signals sample-parallel processing module (31) output
1, d
2..., d
nbe input to synchrolock storing module (32); The data sd of described synchrolock storing module (32) output
1, sd
2..., sd
nbe input to output control module (33).
3. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: the output terminal of the address decoding module (34) of described fpga chip (3) respectively with the input end of output control module (33) with synchronize the input end that latchs signal generator module (35) and be connected; The decoded signal a of described address decoding module (34) output
1, a
2..., a
nbe input to output control module (33), the control signal CTL of described address decoding module (34) output and synchronizing signal SYN2 are input to and synchronously latch signal generator module (35).
4. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: described micro-processing (4) is connected with the output control module (33) of fpga chip (3) with read control signal by data bus; Described micro-processing (4) is connected with the address decoding module (34) of fpga chip (3) by address bus; Described micro-processing (4) is latched signal generator module (35) with output holding signal HOLD with synchronizeing of fpga chip (3) by data bus, read control signal, write control signal, synchronizing signal SYN3 and is connected.
5. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: the clock signal clock of described crystal oscillating circuit (2) output is input to respectively multiple signals sample-parallel processing module (31), the synchrolock storing module (32) of fpga chip (3) and synchronously latchs signal generator module (35).
6. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1 and 2, is characterized in that: the described synchronous latch signal SYNL that synchronously latchs signal generator module (35) output is input to synchrolock storing module (32); Described synchronous latch signal SYNL controls synchrolock storing module (32) by the data d of multiple signals sample-parallel processing module (31) output
1, d
2..., d
nsynchrolock saves as the data sd of synchrolock storing module (32) output
1, sd
2..., sd
n.
7. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: described synchronously latch signal generator module (35) at least comprise Sheffer stroke gate, with door or door, control register, frequency divider, Logical processing unit, synchronizer and chronotron; An input end of described Sheffer stroke gate is connected with the read control signal of micro-processing (4) output, and another input end of described Sheffer stroke gate is connected with the write control signal of micro-processing (4) output; Input end of described and door and the output terminal of Sheffer stroke gate are connected, and the described control signal CTL exporting with address decoding module (34) with another input end of door is connected; The input end EN of described control register be connected with the output terminal of door; The input end D of described control register is connected with the data bus of micro-processing (4) output; The input end D of described frequency divider is connected with the output terminal Q of control register; The input end D of described Logical processing unit is connected with the synchronizing signal SYN2 of address decoding module (34) output; The input end D of described synchronizer is connected with the synchronizing signal SYN3 of micro-processing (4) output; Input end described or door is connected with synchronizing signal SYN1, the output terminal of Logical processing unit and the output terminal of synchronizer of frequency divider output respectively; The input end D of described chronotron with or door output terminal be connected; The clock signal clock of described crystal oscillating circuit (2) output respectively with the input end Clk of controller, the input end Clk of the input end Clk of frequency divider, Logical processing unit, the input end Clk of the input end Clk of synchronizer and chronotron be connected; Signal described or gate output terminal output is described synchronous latch signal SYNL; The signal of described chronotron output terminal output is described output holding signal HOLD.
8. a kind of multiple signals synchronized sampling control circuit based on FPGA according to claim 1, is characterized in that: described synchrolock storing module (32) comprises two latchs or two above latchs; The number of described latch equates with the data way of multiple signals sample-parallel processing module (31) output; The input end Clk of each latch is connected with the clock signal clock of crystal oscillating circuit (2) output; The latching control end Clk-EN and synchronize the synchronous latch signal SYNL that latchs signal generator module (35) output and be connected of each latch; The input end D of each latch is connected with the data of multiple signals sample-parallel processing module (31) output, and the data of the output terminal Q output of each latch are connected with the input end of output control module (33).
9. according to a kind of multiple signals synchronized sampling control circuit based on FPGA described in claim 6 or 7, it is characterized in that: the described synchronous latch signal SYNL producing method that synchronously latchs signal generator module (35) output has three kinds: first kind of way is that the described frequency divider that synchronously latchs signal generator module (35) carries out K frequency division according to the divide ratio K of control register output to the clock signal clock of crystal oscillating circuit (2) output, the synchronizing signal SYN1 of frequency divider output is the K fractional frequency signal of clock signal clock, synchronizing signal SYN1 passes through or exports behind the door synchronous latch signal SYNL, the second way is that the synchronizing signal SYN2 of described address decoding module (34) output is input to the Logical processing unit that synchronously latchs signal generator module (35), and the signal of Logical processing unit output terminal output passes through or export behind the door synchronous latch signal SYNL, the third mode is that the synchronizing signal SYN3 of described microprocessor (4) output is input to the synchronizer that synchronously latchs signal generator module (35), and the signal of microsyn output end output passes through or export behind the door synchronous latch signal SYNL, when described divide ratio K equals zero, first kind of way is inoperative, when described synchronizing signal SYN2 is low level always, the described second way is inoperative, when described synchronizing signal SYN3 is low level, described the third mode is inoperative.
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| CN111157917A (en) * | 2020-02-27 | 2020-05-15 | 石家庄嘉硕电子技术有限公司 | Low-current grounding line selection system and device and grounding fault positioning method |
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